CN104133798A - Big data high-speed storage system and implementation method - Google Patents

Big data high-speed storage system and implementation method Download PDF

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CN104133798A
CN104133798A CN201410377547.3A CN201410377547A CN104133798A CN 104133798 A CN104133798 A CN 104133798A CN 201410377547 A CN201410377547 A CN 201410377547A CN 104133798 A CN104133798 A CN 104133798A
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data
module
storage
flash
memory board
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CN104133798B (en
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何国经
肖佳
栗旭光
谢世熊
白鑫鹏
林先萌
薄振桐
余坦秀
邓启亮
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Xidian University
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Xidian University
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Abstract

The invention provides a big data high-speed storage system and an implementation method. The big data high-speed storage system comprises a power supply management module, a system main control board and a system storage module. The system main control board transmits received data to a storage plate in the system storage module after receiving the data. If the storage plate is not full of information, the information is stored in the storage plate; if the storage plate is full of information, the data are transmitted to a next storage plate, and meanwhile the information embodying that the storage plate is full of the information is fed back to an FPGA main controller; in this way, operation is conducted till the last storage plate is full of information, and big data storage is achieved. An FPGA serves as the core controller, and therefore the 400 MB/s real-time bandwidth is achieved. The data storage capacity can be unlimited in theory. Due to the cascading connection method between the plates, the system structure is made simple, the size and the weight are greatly reduced, and the big data high-speed storage system and the implementation method are suitable for special application occasions such as the occasion where mass data need to be unceasingly stored at a high speed in airborne aerial photography.

Description

A kind of large data high-speed storage system and implementation method
Technical field
The invention belongs to large data high-speed technical field of memory, be specifically related to a kind of large data high-speed storage system and implementation method.
Background technology
Flash memory (FLASH) has that non-volatile (after power down, still can keep data), read or write speed are fast, low-power consumption and portable etc. advantage, as a kind of important storage media, is applied in the middle of product data storage.According to internal framework and the difference that realizes technology, present main flow FLASH mainly contains NOR and NAND FLASH.The feature of NOR is that a plurality of storage unit are parallel, can realize quick random bytes access, is suitable for capacity requirement little, the application that random read-write is fast.The feature of NAND FLASH is to write with the speed of erase operation soon, and chip area is little, is very suitable for mass storage design.
NAND FLASH can be divided into again SLC (Single-level cell, single-order storage unit) and MLC (Multi-level cell, multi-level cell memory).NAND FLASH is stored in data in the mnemon array being comprised of floating dam transistor, and in SLC chip, the information of 1bit is only stored in each unit.And in MLC chip, utilize the control of multiple charge value to allow each unit can store 2bits and above data, reach higher packing density, so unit cost is low, just because of this advantage is more suitable for for mass memory unit MLC.And use MLC NAND FLASH to become a major challenge in the hope of reaching higher data bandwidth.
At present, data are stored in view data storage, the storage of magnanimity data, magnanimity server data stores, in military affairs such as database data storage and civilian each field, have obtained applying very widely.And at present, a lot of storage systems still adopt disk and disk array storage, and use the storage system of FLASH mostly to use asynchronous operation pattern.Its memory capacity is little, and storage speed is low, and data bandwidth is little.
List in detail the major defect of available data storage system below:
1) capacity is less or have a theoretical upper limit, cannot the storage of satisfying magnanimity data;
2) real-time bandwidth is lower, cannot meet the high speed storing of real time data;
3) size is larger, and space hold is large, is not suitable for the equipment that some volumes are little;
4) weight is larger, is not easy to the application of some special occasions.
Summary of the invention
The object of the invention is in order to overcome the defect of above-mentioned prior art, a kind of large data high-speed storage system and implementation method are provided, in the time of the capacity of raising storage system and data storage real-time bandwidth, reduce size and the weight of system.
For achieving the above object, the present invention adopts following technical scheme:
A large data high-speed storage system, comprises power management module, for receiving the systematic master control board of large data and the system storage module being connected with systematic master control board, and system storage module comprises the memory board that several are identical;
Described systematic master control board will be stored in data transmission in system storage module in PC by USB module.
Described power management module is connected with systematic master control board, system storage module for power supply.
Described systematic master control board comprises FPGA master controller, MCU module and USB module, systematic master control board encapsulates packing by received data after receiving data, then send a memory board in system storage module to, if this memory board information is not also filled with, information is stored in to this memory board, if this memory board information is filled with, data are sent to next memory board, the information exchange being filled with is crossed to MCU module simultaneously and feed back to FPGA master controller, the rest may be inferred, until last memory board is filled with; Thereby realized the storage of large data.
Described memory board comprises main system control module, and read-write FLASH data level connects administration module, FIFO cache module, ping-pong operation module, capacity management module, streamline administration module, FLASH interface sequence module and DDR tfi module;
Described main system control module is used for receiving external data and responds PC instruction, and connects administration module to read-write FLASH data level the data transmission of acceptance;
Described read-write FLASH data level connects administration module for the data of receiving system main control module, receives the information of next stage memory board simultaneously, and by the data that receive and communication to FIFO cache module;
Described FIFO cache module is for carrying out buffer memory by data and the information of the read-write FLASH data level gang mould piece of reception;
Described table tennis module, for the data of FIFO cache module buffer memory and information are carried out to ping-pong operation, realizes the piece of data stream and stablizes input and output;
Described capacity management one-chip computer module is for realizing the capacity management of whole memory board;
Described streamline administration module is wide for improving the data tape of whole memory board;
Described FLASH sequential interface module is for generation of the bottom sequential of FLASH operation;
Described DDR tfi module is for becoming DDR data SDR data-switching.
Described memory board also comprises some FLASH storeies, the MCU being connected with FLASH storer, and for storing the EEPROM of the storage capacity information of FLASH storer.
Described FLASH storer adopts the MLC NAND FLASH of monolithic 256Gb, and model is MT29F256G08CJAAB.
Described single memory comprises 10 FLASH, and every 5 FLASH storage that walks abreast, and between 5 FLASH, adopts pipelining to operate.
Between described some memory boards, adopt LVDS interface to carry out data transmission.
An implementation method for large data high-speed storage, comprises the following steps:
After large data start, data constantly enter systematic master control board, systematic master control board encapsulates packing these data after receiving a certain amount of data, then by LVDS interface, send memory board to and store in the middle of the FLASH of memory board, this memory board, after receiving these data, first judges whether this memory board is filled with; If storage is not full, continues the then memory address of last time and store; If be filled with, the state this memory board being filled with sends to MCU module, and then MCU module is stored full information this memory board and stored in the middle of EEPROM, and corresponding levels storage is set to write; The data transfer receiving, give next memory board simultaneously, the like, until all memory boards all store full after, the full status information of storage is returned to main system control module, by main system control module, return to user, make user be made in time corresponding processing.
Compared with prior art, the beneficial effect that the present invention has: the present invention selects FPGA as core controller, has realized the real-time bandwidth of 400MB/s.And data storage capacity, due to the cascade expansion that the stack manner using is realized, it is unlimited to reach in theory.The connected mode that adopts cascade between plate, makes system architecture simple, and size and weight reduce greatly, and the high speed that is applicable to the mass datas such as storage in airborne taking photo by plane continues the particular application of storage.Implementation method of the present invention is simple, is beneficial to operation.
Further, the present invention has used the synchronous mode of operation of MCL NAND FLASH, and the pipelining of using multi-disc to walk abreast between storage and multi-disc, make native system small volume, weight alleviates greatly, has realized the high speed storing of large data, and system is simple, be easy to realize the high speed storing of large data, adopt plate level cascade technology, its memory capacity can be expanded close to limitless volumes.
Further, FLASH adopts the MLC NAND FLASH of monolithic 256Gb, and model is MT29F256G08CJAAB, and this model is in the market than the MLCNAND FLASH of the max cap. that is easier to obtain.The data volume of its program operation is up to 8KB.
Adopt the synchronous mode of operation of NAND FLASH.Compared to the asynchronous mode data throughout of 50MT/s only, the data throughout of synchronous mode, up to 200MT/s, is 4 times of asynchronous mode.
Adopt the exclusive Multi-Plane operator scheme of MLC NAND FLASH, improved the read or write speed of monolithic NANDFLASH.Although in the inner bandwidth improving of monolithic, not clearly, after the multistage water operation through below, suitable remarkable of the raising of this bandwidth.
Adopt 10 NAND FLASH of veneer, realize the mass memory of veneer 320GB.
The front and back data path design of memory board can be docked, and the logical design of system is completely compatible.Like this, the capacity of system just can be expanded by increasing the data of memory board.
Between memory board and memory board, adopt LVDS interface to carry out data transmission, the data transfer bandwidth of LVDS, up to 1Gbps, has improved storage speed.
Adopt 10 NAND FLASH of veneer, and be divided into two groups of each 5 NAND FLASH storage that walks abreast.Between 5 NAND FLASH in each group, use pipelining simultaneously, greatly improved data bandwidth, finally up to 400MB/s.
Adopt the stacking hardware expanding mode of level, the volume of whole storage system is reduced greatly.Take 3TB memory capacity as example, need to want 9 memory boards, its volume taking is only 100mm * 100mm * 100mm.
Accompanying drawing explanation
Fig. 1 is entire system structural drawing;
Fig. 2 is the workflow diagram of single memory board;
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described.
Shown in Fig. 1 and Fig. 2, the present invention includes power management module, for receiving the systematic master control board of large data and the system storage module being connected with systematic master control board, system storage module comprises the memory board that several are identical;
Described systematic master control board will be stored in data transmission in system storage module in PC by USB module.
Described power management module is connected with systematic master control board, system storage module for power supply.
Described systematic master control board comprises FPGA master controller, MCU module and USB module, systematic master control board encapsulates packing by received data after receiving data, then send a memory board in system storage module to, if this memory board information is not also filled with, information is stored in to this memory board, if this memory board information is filled with, data are sent to next memory board, the information exchange being filled with is crossed to MCU module simultaneously and feed back to FPGA master controller, the rest may be inferred, until last memory board is filled with; Thereby realized the storage of large data.
Described main system control module is used for receiving external data and responds PC instruction, and connects administration module to read-write FLASH data level the data transmission of acceptance;
Described read-write FLASH data level connects administration module for the data of receiving system main control module, receives the information of next stage memory board simultaneously, and by the data that receive and communication to FIFO cache module, realize the communication between many plates, realize the expansion of capacity;
Described FIFO cache module is for carrying out buffer memory by data and the information of the read-write FLASH data level gang mould piece of reception;
Described table tennis module, for the data of FIFO cache module buffer memory and information are carried out to ping-pong operation, realizes the piece of data stream and stablizes input and output;
Described capacity management one-chip computer module is for realizing the capacity management of whole memory board;
Described streamline administration module is wide for improving the data tape of whole memory board;
Described FLASH sequential interface module is for generation of the bottom sequential of FLASH operation;
Described DDR tfi module is for becoming DDR data SDR data-switching.
Described memory board also comprises some FLASH storeies.
Described FLASH storer adopts the MLC NAND FLASH of monolithic 256Gb, and model is MT29F256G08CJAAB.
Between described some memory boards, adopt LVDS interface to carry out data transmission.
The present invention selects FPGA as core controller, has realized the real-time bandwidth of 400MB/s.And data storage capacity, due to the cascade expansion that the stack manner using is realized, it is unlimited to reach in theory.The connected mode that adopts cascade between plate, makes system architecture simple, and size and weight reduce greatly, and the high speed that is applicable to the mass datas such as storage in airborne taking photo by plane continues the particular application of storage.
Whole operating process is divided into data receiver layer, Pipeline control layer, data-interface switchable layer and FLASH physical interface layer by the course of work simultaneously.
1. the overall work process of large data high-speed storage system
As shown in Figure 1, after powering on, memory board carries out from detecting.Whether the FLASH that detects oneself capacity that whether master control system normally works, detection of stored plate has been used now on normal, detection of stored plate; So, self-detection result is sent to main system control module, by main system control module, the result of self check is sent to user.User just can directly monitor the state of whole storage system like this.If it is bad to find that there is FLASH, or whole plank is while having problem, processes timely.Complete after self check, the operation of the oper signal of memory board monitoring system main control module to determine that master control borad will carry out memory board is now reading and writing, any operation in wiping.Then memory board enters corresponding operator scheme.If write operation, memory board carries out write operation pattern so.
As shown in Figure 1, after large data start, data constantly enter systematic master control board with a high speed.Systematic master control board for example, encapsulates packing these data according to the agreement of inside definition after receiving a certain amount of data (8KB), then by LVDS interface at a high speed, according to certain address addressing mode, sends No. 1 plate of storage to and stores in the middle of the FLASH of No. 1 plate of storage.For example store No. 1 plate, after receiving these data (8K), first judge whether this memory board (storing No. 1 plate) is filled with.If storage is not full, continues the then memory address of last time and store.If be filled with, the state this memory board being filled with sends to MCU, and then MCU stores full information this memory board and stores in the middle of EEPROM, and corresponding levels storage is set to write.Give storage No. 2 plates the data transfer receiving simultaneously.The like, until all memory boards all store full after, the full status information of storage is returned to main system control module, by main system control module, return to user, make user be made in time corresponding processing.
2. the course of work of memory board
Referring to Fig. 2, the course of work of memory board comprises the following steps:
2.1 configurations after powering on
After powering on, MEM memory board enters waiting status.Wait for the order of data interface module.When being operating as of giving of data interface module write FLASH operation, the FPGA starting capacity management one-chip computer module of MEM plate, obtains the address of writing FLASH of recording last time in the EEPROM of the single-chip microcomputer of capacity management one-chip computer module from memory board.Then the data that obtain from data interface module are ceaselessly stored in the middle of FLASH.When the order of data-interface is when reading FLASH, the FPGA starting capacity management one-chip computer module of MEM plate, the single-chip microcomputer of capacity management one-chip computer module from memory board obtains the address of the FLASH that will read.Then enter read data state, and data are read endlessly from FLASH, and the USB interface by data-interface uploads in the middle of PC.
2.2 data writing operation
When main system control module sends write operation order, memory board FPGA obtains after corresponding configuration, first judges that whether memory board at the corresponding levels is stored completely, if storage is full, switches the interface with main system control module to next stage memory board.Otherwise memory board at the corresponding levels enters write operation.
Enter after write operation, read FLASH data level and connect administration module and the data that obtain are write to the corresponding levels write FLASHFIFO buffer memory.Then, ping-pong operation module writes the data in FIFO in the middle of RAM, and this part has two RAM to carry out ping-pong operation.In these two RAM, when one of them is when writing state, another is in read states.After RAM writes completely, give commencing signal of streamline administration module.Then streamline administration module starts, by interface management module, the interface of writing of FLASH tfi module is switched to corresponding FLASH chip, then the data in current full RAM is distributed to corresponding FLASH according to pre-designed mode.Then, FLASH interface sequence module just generates corresponding FLASH interface sequence the data in RAM, and data are sent to DDR tfi module, and data are converted to DDR from SDR, then gives FLASH chip.So just completed write operation one time.
2.3 read data operations
When main system control module sends read operation order, memory board FPGA starting capacity management one-chip computer module is to obtain the address of the read data transmitting from PC.Then enter read data state.Then streamline administration module sends corresponding read operation order through FLASH interface sequence module, then from FLASH, obtains the data that store FLASH inside.And data to ping-pong operation module, by it, write in the middle of RAM, then data removed from RAM and write the corresponding levels and read in the middle of FIFO buffer memory.Then by read-write FLASH data level, connect administration module data are sent to main system control module, then by main control module, data are sent to PC by USB interface.
2.4 capacity management
After powering on, MCU reads the correlation behavior information of memory board at the corresponding levels in the middle of EEPROM, and by EMIF interface, sends to FPGA as basis for estimation these status informations.All status informations in the middle of EEPROM on MCU on memory board are all original state at the beginning.These status informations comprise whether memory board at the corresponding levels stores full, the current memory location of memory board at the corresponding levels, the memory capacity of memory board at the corresponding levels etc.When memory board at the corresponding levels receives after data, first judge whether memory board at the corresponding levels is stored completely, and storage is not full in this way, the then memory address of last time continuation storage.Stored in this way and expired, the data transfer that the FPGA handle on memory board at the corresponding levels receives is to next stage memory board.The capacity of memory board and the management of memory location have so just been realized.Read data in like manner.
The above, it is only better case study on implementation of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with better implementation method, yet not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the method for above-mentioned announcement and technology contents to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be the content that does not depart from technical solution of the present invention, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, still belong in the scope of technical solution of the present invention.

Claims (7)

1. a large data high-speed storage system, is characterized in that, comprises power management module, for receiving the systematic master control board of large data and the system storage module being connected with systematic master control board, and system storage module comprises the memory board that several are identical;
Described systematic master control board will be stored in data transmission in system storage module in PC by USB module;
Described power management module is connected with systematic master control board, system storage module for power supply;
Described systematic master control board comprises FPGA master controller, MCU module and USB module, systematic master control board encapsulates packing by received data after receiving data, then send a memory board in system storage module to, if this memory board information is not also filled with, information is stored in to this memory board, if this memory board information is filled with, data are sent to next memory board, the information exchange being filled with is crossed to MCU module simultaneously and feed back to FPGA master controller, the rest may be inferred, until last memory board is filled with; Thereby realized the storage of large data.
2. a kind of large data high-speed storage system according to claim 1, it is characterized in that, described memory board comprises main system control module, read-write FLASH data level connects administration module, FIFO cache module, ping-pong operation module, capacity management module, streamline administration module, FLASH interface sequence module and DDR tfi module;
Described main system control module is used for receiving external data and responds PC instruction, and connects administration module to read-write FLASH data level the data transmission of acceptance;
Described read-write FLASH data level connects administration module for the data of receiving system main control module, receives the information of next stage memory board simultaneously, and by the data that receive and communication to FIFO cache module;
Described FIFO cache module is for carrying out buffer memory by data and the information of the read-write FLASH data level gang mould piece of reception;
Described table tennis module, for the data of FIFO cache module buffer memory and information are carried out to ping-pong operation, realizes the piece of data stream and stablizes input and output;
Described capacity management one-chip computer module is for realizing the capacity management of whole memory board;
Described streamline administration module is wide for improving the data tape of whole memory board;
Described FLASH sequential interface module is for generation of the bottom sequential of FLASH operation;
Described DDR tfi module is for becoming DDR data SDR data-switching.
3. a kind of large data high-speed storage system according to claim 1, is characterized in that, described memory board also comprises some FLASH storeies, the MCU being connected with FLASH storer, and for storing the EEPROM of the storage capacity information of FLASH storer.
4. a kind of large data high-speed storage system according to claim 3, is characterized in that, described FLASH storer adopts the MLC NAND FLASH of monolithic 256Gb, and model is MT29F256G08CJAAB.
5. a kind of large data high-speed storage system according to claim 4, is characterized in that, described single FLASH storer comprises 10 FLASH, and every 5 FLASH storage that walks abreast, and between 5 FLASH, adopts pipelining to operate.
6. a kind of large data high-speed storage system according to claim 1, is characterized in that, between described some memory boards, adopts LVDS interface to carry out data transmission.
7. an implementation method for the large data high-speed storage based on system claimed in claim 1, is characterized in that, comprises the following steps:
After large data start, data constantly enter systematic master control board, systematic master control board encapsulates packing these data after receiving a certain amount of data, then by LVDS interface, send memory board to and store in the middle of the FLASH of memory board, this memory board, after receiving these data, first judges whether this memory board is filled with; If storage is not full, continues the then memory address of last time and store; If be filled with, the state this memory board being filled with sends to MCU module, and then MCU module is stored full information this memory board and stored in the middle of EEPROM, and corresponding levels storage is set to write; The data transfer receiving, give next memory board simultaneously, the like, until all memory boards all store full after, the full status information of storage is returned to main system control module, by main system control module, return to user, make user be made in time corresponding processing.
CN201410377547.3A 2014-08-01 2014-08-01 A kind of big data high-speed memory system and implementation method Expired - Fee Related CN104133798B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104317748A (en) * 2014-11-22 2015-01-28 成都锦江电子系统工程有限公司 Multi-MCU-and-FPGA collaboration processing and touch display master monitoring system and image interface design and control method of multi-MCU-and-FPGA collaboration processing and touch display master monitoring system
CN105718219A (en) * 2016-01-19 2016-06-29 浙江大学 Method and module for high-speed data transmission and storage based on USB3.0
CN107102813A (en) * 2016-02-19 2017-08-29 合肥君正科技有限公司 A kind of sensor data acquisition method for being classified storage

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1967713A (en) * 2006-11-27 2007-05-23 华为技术有限公司 High-capacity cache memory
JP2007274036A (en) * 2006-03-30 2007-10-18 Nec Commun Syst Ltd Communication terminal equipment, and control method thereof
US7616508B1 (en) * 2006-08-10 2009-11-10 Actel Corporation Flash-based FPGA with secure reprogramming
CN201465566U (en) * 2009-07-10 2010-05-12 北京国科环宇空间技术有限公司 Data storage device
CN102202171A (en) * 2011-04-21 2011-09-28 北京理工大学 Embedded high-speed multi-channel image acquisition and storage system
CN102520892A (en) * 2012-01-02 2012-06-27 西安电子科技大学 Multifunctional solid state data storage playback instrument

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007274036A (en) * 2006-03-30 2007-10-18 Nec Commun Syst Ltd Communication terminal equipment, and control method thereof
US7616508B1 (en) * 2006-08-10 2009-11-10 Actel Corporation Flash-based FPGA with secure reprogramming
CN1967713A (en) * 2006-11-27 2007-05-23 华为技术有限公司 High-capacity cache memory
CN201465566U (en) * 2009-07-10 2010-05-12 北京国科环宇空间技术有限公司 Data storage device
CN102202171A (en) * 2011-04-21 2011-09-28 北京理工大学 Embedded high-speed multi-channel image acquisition and storage system
CN102520892A (en) * 2012-01-02 2012-06-27 西安电子科技大学 Multifunctional solid state data storage playback instrument

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104317748A (en) * 2014-11-22 2015-01-28 成都锦江电子系统工程有限公司 Multi-MCU-and-FPGA collaboration processing and touch display master monitoring system and image interface design and control method of multi-MCU-and-FPGA collaboration processing and touch display master monitoring system
CN105718219A (en) * 2016-01-19 2016-06-29 浙江大学 Method and module for high-speed data transmission and storage based on USB3.0
CN105718219B (en) * 2016-01-19 2018-12-04 浙江大学 The method and module of high speed data transfer storage based on USB3.0
CN107102813A (en) * 2016-02-19 2017-08-29 合肥君正科技有限公司 A kind of sensor data acquisition method for being classified storage
CN107102813B (en) * 2016-02-19 2020-08-18 合肥君正科技有限公司 Sensor data acquisition method for classified storage

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