CN104133798A - Big data high-speed storage system and implementation method - Google Patents

Abstract

A large data high-speed storage system and its implementation method, including a power management module, a system main control board and a system storage module; after receiving data, the system main control board transmits the received data to a storage board in the system storage module, If the memory board information is not full, store the information in the memory board, if the memory board information is full, then transfer the data to the next memory board, and feed back the full information to the FPGA main controller , and so on, until the last storage board is full; thereby realizing the storage of large data. The present invention selects FPGA as the core controller, and realizes the real-time bandwidth of 400MB/s. And the data storage capacity can theoretically reach unlimited. The cascading connection method between boards makes the system structure simple, and the size and weight are greatly reduced. It is suitable for special applications of high-speed continuous storage of massive data such as storage in airborne aerial photography.

Description

A large data high-speed storage system and its implementation method

technical field

The invention belongs to the technical field of large data high-speed storage, and in particular relates to a large data high-speed storage system and an implementation method.

Background technique

Flash memory (FLASH) has the advantages of non-volatility (data can be retained after power failure), fast read and write speed, low power consumption, and easy portability. It has been used as an important storage medium in data storage products. According to the difference in internal architecture and implementation technology, the current mainstream FLASH mainly includes NOR and NAND FLASH. The characteristic of NOR is that multiple storage units are parallel, which can realize fast random byte access, and is suitable for applications with small capacity requirements and fast random read and write. NAND FLASH is characterized by fast writing and erasing operations and small chip area, which is very suitable for large-capacity memory design.

NAND FLASH can be divided into SLC (Single-level cell, single-level storage unit) and MLC (Multi-level cell, multi-level storage unit). NAND FLASH stores data in an array of memory cells composed of floating gate transistors. In an SLC chip, each cell only stores 1 bit of information. In the MLC chip, the control of various charge values is used to allow each unit to store data of 2 bits or more to achieve a high data density, so the unit cost is low. Because of this advantage, MLC is more suitable for mass storage. in the storage device. However, using MLC NAND FLASH to achieve higher data bandwidth has become a big challenge.

At present, data storage has been widely used in military and civilian fields such as image data storage, massive research data storage, massive server data storage, and database data storage. At present, many storage systems still use disks and disk arrays for storage, and most storage systems using FLASH use asynchronous operation modes. Its storage capacity is small, storage speed is low, and data bandwidth is small.

The main disadvantages of existing data storage systems are detailed below:

1) The capacity is small or has a theoretical upper limit, which cannot meet the storage of massive data;

2) The real-time bandwidth is low, which cannot meet the high-speed storage of real-time data;

3) Large size, large space occupation, not suitable for some small equipment;

4) The weight is relatively large, which is inconvenient for some special occasions.

Contents of the invention

The purpose of the present invention is to overcome the defects of the above-mentioned prior art, provide a large data high-speed storage system and its implementation method, increase the capacity of the storage system and the real-time bandwidth of data storage, and reduce the size and weight of the system.

To achieve the above object, the present invention adopts the following technical solutions:

A large data high-speed storage system, including a power management module, a system main control board for receiving big data, and a system storage module connected to the system main control board, the system storage module includes several identical storage boards;

The system main control board transmits the data stored in the system storage module to the PC through the USB module.

The power management module is connected with the system main control board and the system storage module for power supply.

Described system main control board comprises FPGA master controller, MCU module and USB module, and system main control board packs the received data after receiving data, then sends to a storage board in the system storage module, if the If the storage board information is not full, store the information in the storage board, if the storage board information is full, then transfer the data to the next storage board, and at the same time feed back the full information to the FPGA main control through the MCU module device, and so on, until the last storage board is full; thereby realizing the storage of large data.

The storage board includes a system main control module, a read-write FLASH data cascade management module, a FIFO cache module, a ping-pong operation module, a capacity management module, a pipeline management module, a FLASH interface timing module and a DDR timing module;

The system main control module is used to receive external data and respond to PC instructions, and transmit the received data to the read-write FLASH data cascading management module;

The read-write FLASH data cascading management module is used to receive the data of the system main control module, and simultaneously receive the information of the next-level storage board, and transmit the received data and information to the FIFO cache module;

The FIFO cache module is used to cache the data and information of the received read-write FLASH data cascading module;

The ping-pong module is used to perform a ping-pong operation on the data and information cached in the FIFO cache module to realize block stable input and output of data streams;

The capacity management single-chip microcomputer module is used to realize the capacity management of the entire storage board;

The pipeline management module is used to improve the data storage bandwidth of the entire storage board;

The FLASH timing interface module is used to generate the underlying timing of the FLASH operation;

The DDR timing module is used to convert SDR data into DDR data.

The storage board also includes several FLASH memories, an MCU connected to the FLASH memories, and an EEPROM for storing storage capacity information of the FLASH memories.

The FLASH memory adopts a single-chip 256Gb MLC NAND FLASH, the model is MT29F256G08CJAAB.

The single memory includes 10 pieces of FLASH, and every 5 pieces of FLASH are stored in parallel, and pipeline technology is used to operate among the 5 pieces of FLASH.

The LVDS interface is used for data transmission among the plurality of storage boards.

A method for realizing high-speed storage of big data, comprising the following steps:

After the big data starts, the data continuously enters the main control board of the system. After receiving a certain amount of data, the main control board of the system packages and packages the data, and then transmits it to the storage board through the LVDS interface and stores it in the FLASH of the storage board. After the storage board receives these data, it first judges whether the storage board is full; if it is not full, it continues to store at the last storage address; if it is full, it sends the status of the storage board full to MCU module, and then the MCU module stores the full information of the storage board in the EEPROM, and sets the storage of the current level as non-writable; at the same time, it transfers the received data to the next storage board, and so on, until all the storage boards After the storage is full, the full storage status information is returned to the system main control module, and the system main control module returns it to the user, so that the user can make corresponding processing in time.

Compared with the prior art, the present invention has beneficial effects: the present invention selects FPGA as the core controller and realizes a real-time bandwidth of 400MB/s. And the data storage capacity, due to the cascading expansion achieved by the stacking method used, can theoretically reach unlimited. The cascading connection method between boards makes the system structure simple, and the size and weight are greatly reduced. It is suitable for special applications of high-speed continuous storage of massive data such as storage in airborne aerial photography. The realization method of the present invention is simple and convenient for operation.

Further, the present invention uses the synchronous operation mode of MCL NAND FLASH, and uses multi-chip parallel storage and multi-chip pipeline technology, so that the system is small in size, greatly reduced in weight, and realizes high-speed storage of large data, and The system is simple, easy to realize high-speed storage of large data, and adopts board-level cascading technology, so that its storage capacity can be expanded close to unlimited capacity.

Furthermore, the FLASH uses a single-chip 256Gb MLC NAND FLASH, the model is MT29F256G08CJAAB, which is the largest capacity MLCNAND FLASH that is relatively easy to obtain on the market. The data volume of one program operation is as high as 8KB.

Adopt the synchronous operation mode of NAND FLASH. Compared with the data throughput of only 50MT/s in the asynchronous mode, the data throughput of the synchronous mode is as high as 200MT/s, which is 4 times that of the asynchronous mode.

Using the unique Multi-Plane operation mode of MLC NAND FLASH, the reading and writing speed of single-chip NAND FLASH is improved. Although the increased bandwidth within a single chip is not very obvious, after the subsequent multi-stage pipeline operation, the increase in bandwidth is quite significant.

Using 10 pieces of NAND FLASH on a single board to achieve a massive storage of 320GB on a single board.

The front and back data path design of the memory board can be connected, and the logic design of the system is fully compatible. In this way, the capacity of the system can be expanded by adding data on the memory board.

The LVDS interface is used for data transmission between the storage board and the storage board. The data transmission bandwidth of LVDS is as high as 1Gbps, which improves the storage speed.

10 pieces of NAND FLASH are used on a single board, and are evenly divided into two groups of 5 pieces of NAND FLASH for parallel storage. At the same time, pipeline technology is used between the 5 pieces of NAND FLASH in each group, which greatly improves the data bandwidth, and finally reaches 400MB/s.

The hardware expansion method of hierarchical stacking makes the volume of the entire storage system greatly reduced. Taking the 3TB storage capacity as an example, 9 storage boards are required, and the occupied volume is only 100mm×100mm×100mm.

Description of drawings

Figure 1 is the overall structure diagram of the system;

Fig. 2 is the work flowchart of single memory board;

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings.

Referring to Figures 1 and 2, the present invention includes a power management module, a system main control board for receiving large data, and a system storage module connected to the system main control board, and the system storage module includes several identical storage boards;

The system main control board transmits the data stored in the system storage module to the PC through the USB module.

The power management module is connected with the system main control board and the system storage module for power supply.

Described system main control board comprises FPGA master controller, MCU module and USB module, and system main control board packs the received data after receiving data, then sends to a storage board in the system storage module, if the If the storage board information is not full, store the information in the storage board, if the storage board information is full, then transfer the data to the next storage board, and at the same time feed back the full information to the FPGA main control through the MCU module device, and so on, until the last storage board is full; thereby realizing the storage of large data.

The system main control module is used to receive external data and respond to PC instructions, and transmit the received data to the read-write FLASH data cascading management module;

The read-write FLASH data cascading management module is used to receive the data of the system main control module, and at the same time receive the information of the next-level storage board, and transmit the received data and information to the FIFO cache module, so as to realize the communication between multiple boards , to achieve capacity expansion;

The FIFO cache module is used to cache the data and information of the received read-write FLASH data cascading module;

The ping-pong module is used to perform a ping-pong operation on the data and information cached in the FIFO cache module to realize block stable input and output of data streams;

The capacity management single-chip microcomputer module is used to realize the capacity management of the entire storage board;

The pipeline management module is used to improve the data storage bandwidth of the entire storage board;

The FLASH timing interface module is used to generate the underlying timing of the FLASH operation;

The DDR timing module is used to convert SDR data into DDR data.

The storage board also includes several FLASH memories.

The FLASH memory adopts a single-chip 256Gb MLC NAND FLASH, the model is MT29F256G08CJAAB.

The LVDS interface is used for data transmission among the plurality of storage boards.

The present invention selects FPGA as the core controller, and realizes the real-time bandwidth of 400MB/s. And the data storage capacity, due to the cascading expansion achieved by the stacking method used, can theoretically reach unlimited. The cascading connection method between boards makes the system structure simple, and the size and weight are greatly reduced. It is suitable for special applications of high-speed continuous storage of massive data such as storage in airborne aerial photography.

At the same time, the entire operation process is divided into data receiving layer, pipeline control layer, data interface switching layer, and FLASH physical interface layer according to the working process.

1. The overall working process of the big data high-speed storage system

As shown in Figure 1, after power-on, the memory board performs self-test. Check whether your own FLASH is normal, check whether the main control system on the storage board is working normally, check the capacity of the storage board that has been used now; then send the self-test result to the system main control module, and the system main control module will send the self-test The result is sent to the user. In this way, users can directly monitor the status of the entire storage system. If it is found that some FLASH is broken, or the whole board has a problem, deal with it in time. After completing the self-test, the storage board monitors the oper signal of the main control module of the system to determine which operation the main control board is going to perform on the storage board, which is read, write, and erase. The memory board then enters the corresponding operating mode. If it is a write operation, then the memory board performs a write operation mode.

As shown in Figure 1, after the start of big data, data continuously enters the system main control board at a high rate. After receiving a certain amount of data (such as 8KB), the main control board of the system packages the data according to the internally defined protocol, and then transmits it to the storage No. 1 board through the high-speed LVDS interface according to a certain address addressing method and stores it in the It is stored in the FLASH of No. 1 board. After receiving these data (for example, 8K), the No. 1 storage board first judges whether the storage board (Storage No. 1 board) is full. If the storage is not full, continue to store at the last storage address. If it is full, then send the full state of the storage board to the MCU, and then the MCU stores the full information of the storage board in the EEPROM, and sets the storage at this level as non-writable. At the same time, the received data is transferred to the No. 2 storage board. By analogy, until all the storage boards are full, the full storage status information is returned to the system main control module, and the system main control module returns it to the user, so that the user can make corresponding processing in time.

2. The working process of the memory board

Referring to Figure 2, the working process of the memory board includes the following steps:

2.1 Configuration after power-on

After power-on, the MEM storage board enters the waiting state. Waiting for commands from the data interface module. When the operation given by the data interface module is a write FLASH operation, the FPGA of the MEM board starts the capacity management single-chip microcomputer module, and the capacity management single-chip microcomputer module obtains the last recorded write FLASH address from the EEPROM of the single-chip microcomputer on the storage board. Then store the data obtained from the data interface module into the FLASH continuously. When the command of the data interface is to read FLASH, the FPGA of the MEM board starts the capacity management single-chip microcomputer module, and the capacity management single-chip microcomputer module obtains the address of the FLASH to be read from the single-chip microcomputer on the storage board. Then enter the state of reading data, and continuously read the data from the FLASH, and upload it to the PC through the USB interface of the data interface.

2.2 Write data operation

When the main control module of the system sends a write operation command, after the FPGA of the storage board obtains the corresponding configuration, it first judges whether the storage board of this level is full. If the storage is full, the interface with the main control module of the system is switched to the storage board of the next level. Otherwise, the storage board of the current level enters the write operation.

After entering the write operation, the read FLASH data cascade management module writes the obtained data into the write FLASHFIFO cache of the current level. Then, the ping-pong operation module writes the data in the FIFO into the RAM, and this part has two RAMs for the ping-pong operation. When one of the two RAMs is in the write state, the other is in the read state. When the RAM is full, give the pipeline management module a start signal. Then the pipeline management module starts to switch the write interface of the FLASH timing module to the corresponding FLASH chip through the interface management module, and then distributes the data in the currently full RAM to the corresponding FLASH in a pre-designed manner. Then, the FLASH interface timing module generates the corresponding FLASH interface timing from the data in RAM, and sends the data to the DDR timing module, converts the data from SDR to DDR, and then sends it to the FLASH chip. This completes a write operation.

2.3 Read data operation

When the system main control module issues a read operation command, the storage board FPGA starts the capacity management single-chip microcomputer module to obtain the address of the read data transmitted from the PC. Then enter the read data state. Then the pipeline management module sends the corresponding read operation command through the timing module of the FLASH interface, and then obtains the data stored inside the FLASH from the FLASH. And the data is given to the ping-pong operation module, which is written into the RAM, and then the data is moved from the RAM to the read FIFO cache of the current level. Then the management module transmits the data to the system main control module by reading and writing the FLASH data, and then the main control module sends the data to the PC through the USB interface.

2.4 Capacity Management

After power-on, the MCU reads the relevant status information of the storage board at this level from the EEPROM, and sends the status information to the FPGA through the EMIF interface as a basis for judgment. At the beginning, all state information in the EEPROM on the MCU on the storage board is the initial state. The status information includes whether the storage board of the current level is full, the current storage position of the storage board of the current level, the storage capacity of the storage board of the current level, and the like. When the storage board of this level receives the data, it first judges whether the storage board of the current level is full. If it is not full, it continues to store at the last storage address. If the storage is full, the FPGA on the current storage board transfers the received data to the next storage board. In this way, the management of the capacity and storage location of the storage board is realized. Read data in the same way.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with a preferred implementation method, it is not intended to limit the present invention. Anyone who is familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, can use the method and technical content disclosed above to make some changes or modifications to equivalent embodiments with equivalent changes, but all without departing from the content of the technical solution of the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still belong to the scope of the technical solutions of the present invention.

Claims (7)

1. A large data high-speed storage system, characterized in that it includes a power management module, a system main control board for receiving large data and a system storage module connected to the system main control board, and the system storage module includes several identical storage plate; The system main control board transmits the data stored in the system storage module to the PC through the USB module; The power management module is connected to the system main control board and the system storage module for power supply; Described system main control board comprises FPGA master controller, MCU module and USB module, and system main control board packs the received data after receiving data, then sends to a storage board in the system storage module, if the If the storage board information is not full, store the information in the storage board, if the storage board information is full, then transfer the data to the next storage board, and at the same time feed back the full information to the FPGA main control through the MCU module device, and so on, until the last storage board is full; thereby realizing the storage of large data. 2. A kind of big data high-speed storage system according to claim 1, it is characterized in that, described storage board comprises system main control module, reading and writing FLASH data cascading management module, FIFO cache module, ping-pong operation module, capacity management module, pipeline management module, FLASH interface timing module and DDR timing module; The system main control module is used to receive external data and respond to PC instructions, and transmit the received data to the read-write FLASH data cascading management module; The read-write FLASH data cascading management module is used to receive the data of the system main control module, and simultaneously receive the information of the next-level storage board, and transmit the received data and information to the FIFO cache module; The FIFO cache module is used to cache the data and information of the received read-write FLASH data cascading module; The ping-pong module is used to perform a ping-pong operation on the data and information cached in the FIFO cache module to realize block stable input and output of data streams; The capacity management single-chip microcomputer module is used to realize the capacity management of the entire storage board; The pipeline management module is used to improve the data storage bandwidth of the entire storage board; The FLASH timing interface module is used to generate the underlying timing of the FLASH operation; The DDR timing module is used to convert SDR data into DDR data. 3. A kind of big data high-speed storage system according to claim 1, it is characterized in that, described memory board also comprises some FLASH memories, the MCU that links to each other with FLASH memories, and the EEPROM that is used to store the storage capacity information of FLASH memories . 4. A kind of big data high-speed storage system according to claim 3, is characterized in that, described FLASH memory adopts the MLC NAND FLASH of monolithic 256Gb, and model is MT29F256G08CJAAB. 5. A kind of big data high-speed storage system according to claim 4, it is characterized in that, described single FLASH memory comprises 10 pieces of FLASH, and every 5 pieces of FLASH carry out parallel storage, adopt pipeline technology to operate between 5 pieces of FLASH . 6. A large data high-speed storage system according to claim 1, characterized in that, LVDS interfaces are used for data transmission between the plurality of storage boards. 7. A method for realizing high-speed storage of large data based on the system according to claim 1, comprising the following steps: After the big data starts, the data continuously enters the main control board of the system. After receiving a certain amount of data, the main control board of the system packages and packages the data, and then transmits it to the storage board through the LVDS interface and stores it in the FLASH of the storage board. After the storage board receives these data, it first judges whether the storage board is full; if it is not full, it continues to store at the last storage address; if it is full, it sends the status of the storage board full to MCU module, and then the MCU module stores the full information of the storage board in the EEPROM, and sets the storage of the current level as non-writable; at the same time, it transfers the received data to the next storage board, and so on, until all the storage boards After the storage is full, the full storage status information is returned to the system main control module, and the system main control module returns it to the user, so that the user can make corresponding processing in time.