CN107608654A - The transmission control unit and method of multi-path asynchronous information - Google Patents
The transmission control unit and method of multi-path asynchronous information Download PDFInfo
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Abstract
A kind of transmission control unit of multi-path asynchronous information, including：Data integrator, it is connected with memory modules and processor interface, including at least two ping-pong operation modules, the data integrator is used to receive the multi-path asynchronous information of extraneous output and integrated, information is integrated all the way, asynchronous information includes asynchronous data and asynchronous control signal, and integrating information includes integral data and synchronous control signal；Memory modules, for according to synchronous control signal, reading and/or writing integral data；Processor interface, it is connected with data integrator, memory modules and the processor in the external world, for obtaining the integration information of data integrator output and obtaining the integral data being had been written into memory modules.Present invention also offers a kind of corresponding method.The present invention is applied to pipeline system algorithm, realizes seamless buffering and the processing of asynchronous information, can also save cushion space, reaches the effect of low-speed module processing high-speed data-flow.
Description
Technical field
The present invention relates to the communications field, more particularly to a kind of transmission control unit and method of multi-path asynchronous information.
Background technology
With continuous increase of the arrival and people in big data epoch for various information demand in life, data acquisition
More and more extensive application has been obtained in life, education, scientific research etc..With the development of technology, obtained data fineness
Gradually while increase, uncompressed data volume is also more and more huger, this control speed and transmission for data-interface
Speed proposes a higher and higher requirement, in the case where single-pass data interface can not meet speed transmission requirement, typically
People can be completed using multichannel data interface.
In the prior art, generally carried out data transmission with following manner and its controlled.First will with external clock frequency
The data of upper computer end are write in FPGA SRAM in a manner of fixed byte, are afterwards passed data with internal system clock frequency
Handled to processor.
Using the above method, there are following shortcomings：Internal system needs to wait when by digital independent into processor
Position generator terminal could be carried out after entering completion to SRAM write, therefore longer waiting period be present, so as to which speed is slow；Incoming data
It is transferred directly to processor so that processor, which can only be handled, is currently entering data, and data before are not preserved；Simultaneity factor
Flow is excessively simple, it is difficult to meet the requirement compared with complication system for data flow control.
The content of the invention
(1) technical problems to be solved
It is above-mentioned to solve it is an object of the invention to provide a kind of transmission control unit and method of multi-path asynchronous information
At least one technical problem.
(2) technical scheme
The invention provides a kind of transmission control unit of multi-path asynchronous information, including data integrator, memory modules and
Processor interface, wherein,
Data integrator, it is connected with memory modules and processor interface, including at least two ping-pong operation modules, the data
Integrator is used to receive the multi-path asynchronous information of extraneous output and integrated, and is integrated information, the asynchronous information all the way
Including asynchronous data and asynchronous control signal, the integration information includes integral data and synchronous control signal, ping-pong operation mould
The number of block is consistent with the number of multi-path asynchronous information；
Memory modules, for according to the synchronous control signal, reading and/or writing integral data；
Processor interface, it is connected with data integrator, memory modules and the processor in the external world, for obtaining data integrator
The integral data being had been written into the integration information and acquisition memory modules of output.
In some embodiments of the invention, the ping-pong operation module includes：Input data selector, output data choosing
Device and at least two FIFO arrays are selected, wherein, input data selector, for selecting a FIFO array to carry out multichannel
The caching of asynchronous data all the way in asynchronous data；Output data selector, it is different all the way for being cached in input data selector
While step data, selection removes remaining FIFO array of the FIFO array, and reading has wherein cached asynchronous
Data, and the asynchronous data read is synchronized into processing and splicing, obtain integral data all the way.
In some embodiments of the invention, the data integrator also includes：Control signal synchronization unit, including with institute
The consistent register of ping-pong operation number of modules is stated, the asynchronous control signal of multichannel corresponding to register record, when each deposit
When device is all in recording status, exports synchronous control signal all the way and delete the recording status in each register.
In some embodiments of the invention, the synchronous control signal includes：Line synchronising signal, first dielectric signal,
Row count signal, frame count signal, end signal, write control level signal, write commencing signal, write initial address, write-in length,
Control level signal is read, commencing signal is read, read initial address and reads length.
In some embodiments of the invention, the memory modules include：Signal controller, it is connected with data integrator,
For obtaining the integration information；Read-write controller, according to integrate information in synchronous control signal, internally deposit into row read and/
Or write integral data.
In some embodiments of the invention, in addition to：Transport module, including multiple transmission units, the transport module are used
In the multi-path asynchronous information for receiving extraneous output, and the number of transmission unit is consistent with the number of multi-path asynchronous information.
Based on same inventive concept, present invention also offers a kind of transfer control method of multi-path asynchronous information, it is applied to
The transmission control unit of foregoing multi-path asynchronous information, including：
Receive the multi-path asynchronous information of extraneous output and integrated, integrated information, the asynchronous information bag all the way
Asynchronous data and asynchronous control signal are included, the integration information includes integral data and synchronous control signal, ping-pong operation module
Number it is consistent with the number of multi-path asynchronous information；
According to the synchronous control signal, integral data is read and/or write；
Obtain the integration information of data integrator output and obtain the integral data being had been written into memory modules.
In some embodiments of the invention, the synchronous control signal includes：Line synchronising signal, first dielectric signal,
Row count signal, frame count signal, end signal, write control level signal, write commencing signal, write initial address, write-in length,
Control level signal is read, commencing signal is read, read initial address and reads length.
In some embodiments of the invention, write in the integration information of acquisition data integrator output and memory modules
The integral data entered, specifically includes step：When it is high that writing in synchronous control signal, which controls level signal, read-write controller root
According to writing commencing signal, writing initial address and writing length, integral data is write into internal memory；When the reading control in synchronous control signal
When level signal processed is high, read-write controller is read according to commencing signal, reading initial address and reading length is read from internal memory
Integral data, and output this to processor interface.
(3) beneficial effect
The transmission control unit and method of the multi-path asynchronous information of the present invention are compared to prior art, at least with following excellent
Point：
1st, data integrator has at least two ping-pong operation modules, when the asynchronous information all the way in multi-path asynchronous information delays
Deposit in a ping-pong operation module, can be read simultaneously in remaining ping-pong operation module and be buffered in other asynchronous informations therein, no
The stand-by period is needed, speed faster, to reach data cached and read data continuously effect, is calculated suitable for pipeline system
Method, seamless buffering and the processing of asynchronous information are realized, cushion space can also be saved, reach low-speed module processing high-speed data-flow
Effect.
2nd, by the data synchronisation unit in data integrator and control signal synchronization unit, multi-path asynchronous information is carried out
Integrate, integrated information all the way, facilitate the transmission of multiline message, and transmission error can be reduced.
3rd, processor interface can not only receive the current integration information of data integrator output, moreover it is possible to from memory modules
The integration information before memory modules storage is read, realizes the integration information backup of different times.
4th, simple in construction, cost is cheap, and speed is fast, can be widely applied to need high-speed, multi-path to transmit and needs to realize one
The data transfer occasion of complexity logic is determined, especially suitable for high-speed lossless Image Data Compression application.
Brief description of the drawings
Fig. 1 is the structural representation of the transmission control unit of the multi-path asynchronous information of the embodiment of the present invention.
Fig. 2 is the structural representation of the transmission control unit of the multi-path asynchronous information of a specific embodiment of the invention.
Fig. 3 is the structural representation of the ping-pong operation module of the embodiment of the present invention.
Fig. 4 is the step schematic diagram of the transfer control method of the multi-path asynchronous information of the embodiment of the present invention.
Embodiment
In general, there is following technological deficiency in prior art：The waiting period of multi-channel data transmission is longer, and speed is slow；
Processor can only handle current data, and data before are not preserved；System flow is excessively simple, it is difficult to meets compared with complication system
Control for data flow.
In view of this, the invention provides a kind of transmission control unit and method of multi-path asynchronous information.Apparatus of the present invention
In data integrator there are at least two ping-pong operation modules, when in multi-path asynchronous information asynchronous information all the way cache one
In ping-pong operation module, it can be read simultaneously in remaining ping-pong operation module and be buffered in other asynchronous informations therein, to reach slow
Deposit data and data continuously effect is read, suitable for pipeline system algorithm, realize seamless buffering and the place of asynchronous information
Reason, can also save cushion space, reach the effect of low-speed module processing high-speed data-flow.Wherein, multiline message refers at least two
Road information, the data and control signal of multi-path asynchronous information Zhi Mei roads information are nonsynchronous.
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in more detail.
The one side of the embodiment of the present invention, there is provided a kind of transmission control unit of multi-path asynchronous information, Fig. 1 are the present invention
The structural representation of the transmission control unit of the multi-path asynchronous information of embodiment, as shown in figure 1, the device includes data integrator
1st, memory modules 2 and processor interface 3.
Data integrator 1, it is connected with memory modules 2 and processor interface 3, including at least two ping-pong operation modules.Should
Data integrator 1 receives the multi-path asynchronous information of extraneous output and integrated, and is integrated information all the way, facilitates multiline message
Transmission, and transmission error can be reduced.Asynchronous information includes asynchronous data and asynchronous control signal, and the integration information includes
Integral data and synchronous control signal, the number of ping-pong operation module are consistent with the number of multi-path asynchronous information.
Memory modules 2, the synchronous control signal exported according to the Data Integration phase, read and/or write integral data.
Processor interface 3, it is connected with the processor of data integrator 1, memory modules 2 and the external world, obtains data integrator 1
The integral data being had been written into the integration information and acquisition memory modules 2 of output.Processor interface can be chip internal
Physical circuit line or the pin used with device external communication, generally comprise data transfer path, and passed
The supplementary structure of defeated operation.
It is understood that processor interface 3 can not only receive the current integration information of the output of data integrator 1, also
Can be read from memory modules 2 memory modules 2 store before integration information, realize different times integration information it is standby
Part.
Fig. 2 is the structural representation of the transmission control unit of the multi-path asynchronous information of an of the invention specific embodiment, such as Fig. 2
Shown, the device is in addition to data integrator 1, memory modules 2 and processor interface 3, in addition to is used to receive extraneous output
Multi-path asynchronous information transport module 4, the transport module 4 includes multiple transmission units.In order to facilitate the transmission of multiline message,
Avoid disturbing, set the number of transmission unit consistent with the number of multi-path asynchronous information herein, that is, each transmission unit
Transmission of one line asynchronous information.It is understood that the transmission unit includes but is not limited to optical transmission unit.
Data integrator 1 includes at least two ping-pong operation modules 11 and control signal synchronization unit 12.In general, table tennis
The number of pang operation module 11 should be consistent with the number of multi-path asynchronous information, to prevent from producing interference in message transmitting procedure.Control
Signal synchronization unit 12 processed, including the register consistent with the number of ping-pong operation module 11, the register record corresponding to
The asynchronous control signal of multichannel, when each register is all in recording status, output synchronous control signal and by each deposit all the way
Recording status in device is deleted.That is, when each register receives the asynchronous control signal of whole multichannels, it is all located
In recording status, the asynchronous control signal all the way received the latest is now selected, and be set to multiplexing conformity data only
One synchronous control signal, then, then the recording status deletion by actual registers, so as to be the multi-path asynchronous of synchronous subsequent time
Control signal is prepared.
Memory modules 2 include signal controller 21, internal memory 22 and read-write controller, and the memory modules 2 can be in DDR3
Storing module 2, other memory modules 2 can also be selected according to the actual requirements.Signal controller 21 is connected with data integrator 1,
Obtain and integrate information：The Synchronization Control letter that the integrated signal and control signal synchronization unit 12 that ping-pong operation module 11 exports export
Number.Read-write controller, according to the synchronous control signal integrated in information, internal memory 22 is read and/or write integral data.Its
In, synchronous control signal includes：Line synchronising signal, first dielectric signal, row count signal, frame count signal, end signal, write
Control level signal, commencing signal is write, initial address is write, writes length, read control level signal, read commencing signal, read initially
Address and reading length.
Fig. 3 is the structural representation of the ping-pong operation module of the embodiment of the present invention, as shown in figure 3, ping-pong operation module bag
Include：Input data selector 111, the FIFO array 112 of output data selector 113 and at least two.Implement in the present invention
In example, it is contemplated that power problemses, select two FIFO arrays 112, the FIFO array of other numbers can also be selected.
Input data selector 111, a FIFO array 112 is selected to carry out in multi-path asynchronous data asynchronous data all the way
Caching.
Output data selector 113, while caching asynchronous data all the way in input data selector 111, selection is another
One FIFO array 112, read the asynchronous data wherein cached.It should be noted that in multiple ping-pong operation modules just
Synchronous clock is employed in the FIFO array 112 being read, the asynchronous data read can be synchronized processing
With the splicing of digit so that the output data of different ping-pong operation modules turns into an entirety, obtains integral data all the way, can be with
Save the stand-by period of read-write.
Below, the idiographic flow of data transfer in ping-pong operation module is described with reference to Fig. 3：
When the first circuit-switched data arrives, by input data selector, by first via data buffer storage to No. 1 FIFO battle array
In row；When the second circuit-switched data arrives, because now No. 1 FIFO array has been cached with the first circuit-switched data, therefore input
Second circuit-switched data is cached in No. 2 FIFO arrays by data selector, while will have been cached in No. 1 FIFO array
First circuit-switched data is exported by output data selector.When 3rd circuit-switched data arrives, by input data selector, by the 3rd tunnel
Data buffer storage passes through output into No. 1 FIFO array, while by the second circuit-switched data cached in No. 2 FIFO arrays
Data selector exports, by that analogy.When carrying out output operation, for each FIFO array, when all feeding identical
Clock, and the output data that parallel connection is obtained is grouped together by way of splicing so that output data selector final output
Signal be changed into the one-channel signal exported simultaneously.
The another aspect of the embodiment of the present invention, a kind of transfer control method of multi-path asynchronous information is additionally provided, is applied to
The transmission control unit of foregoing multi-path asynchronous information, Fig. 4 are the transmission controlling party of the multi-path asynchronous information of the embodiment of the present invention
The step schematic diagram of method, as shown in figure 4, this method comprises the following steps：
Step S1, receive the multi-path asynchronous information of extraneous output and integrated, integrated information all the way, it is described asynchronous
Information includes asynchronous data and asynchronous control signal, and the integration information includes integral data and synchronous control signal, table tennis behaviour
The number for making module is consistent with the number of multi-path asynchronous information；
Step S2, according to the synchronous control signal, read and/or write integral data.Wherein, the synchronous control signal bag
Include：Line synchronising signal, first dielectric signal, row count signal, frame count signal, end signal, write control level signal, write out
Beginning signal, initial address, write-in length are write, control level signal is read, read commencing signal, read initial address and reads length.
Step S3, obtain the integration information of data integrator output and obtain the integration number being had been written into memory modules
According to.It is concretely comprised the following steps：
When it is high that writing in synchronous control signal, which controls level signal, read-write controller is according at the beginning of writing commencing signal, write
Beginning address and write-in length, integral data is write into internal memory：Now read-write controller, which receives, writes commencing signal, initial from writing
Address starts the data that write-in is equal to the write-in length received, and the mode for writing internal memory is initially to enter row write in initial address
Enter, writing address is added forward 1 when often receiving a data, deposited so as to which the integral data of data integrator output is replicated into portion
Enter internal memory.
When it is high that the reading in synchronous control signal, which controls level signal, read-write controller is first according to reading commencing signal, reading
Beginning address and read length, integral data is read from internal memory, and output this to processor interface：Read-write controller receives
To commencing signal is read, the data for being equal to the length signals received are read since being read initial address, reading manner is initially to exist
Read initial address to be read out, address will be read when often receiving a data and adds 1 forward, so as to write what is read from internal memory
The data entered are transmitted to processor interface.
The transmission control unit and method of the multi-path asynchronous information of the present invention, simple in construction, cost is cheap, and speed is fast, can
To be widely used in the data transfer occasion for needing high-speed, multi-path to transmit and needing to realize certain complexity logic, especially suitable for
High-speed lossless Image Data Compression application.
Particular embodiments described above, the purpose of the present invention, technical scheme and beneficial effect are carried out further in detail
Describe in detail it is bright, should be understood that the foregoing is only the present invention specific embodiment, be not intended to limit the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc., it should be included in the guarantor of the present invention
Within the scope of shield.
Claims (9)
1. a kind of transmission control unit of multi-path asynchronous information, including data integrator, memory modules and processor interface, its
In,
Data integrator, it is connected with memory modules and processor interface, including at least two ping-pong operation modules, the Data Integration
Device is used to receive the multi-path asynchronous information of extraneous output and integrated, and is integrated information all the way, the asynchronous information includes
Asynchronous data and asynchronous control signal, the integration information include integral data and synchronous control signal, ping-pong operation module
Number is consistent with the number of multi-path asynchronous information；
Memory modules, for according to the synchronous control signal, reading and/or writing integral data；
Processor interface, it is connected with data integrator, memory modules and the processor in the external world, for obtaining data integrator output
Integration information and obtain the integral data that has been written into memory modules.
2. device according to claim 1, wherein, the ping-pong operation module includes：Input data selector, output number
According to selector and at least two FIFO arrays, wherein,
Input data selector, for selecting a FIFO array to carry out in multi-path asynchronous data the slow of asynchronous data all the way
Deposit；
Output data selector, while for caching asynchronous data all the way in input data selector, selection remove this one
Remaining FIFO array of FIFO array, read the asynchronous data wherein cached, and the asynchronous data that will be read
Processing and splicing are synchronized, obtains integral data all the way.
3. device according to claim 2, the data integrator also includes：
Control signal synchronization unit, including the register consistent with the ping-pong operation number of modules, register record are corresponding
Multichannel asynchronous control signal, when each register is all in recording status, output synchronous control signal and will be posted respectively all the way
Recording status in storage is deleted.
4. device according to claim 1, wherein, the synchronous control signal includes：Line synchronising signal, first dielectric letter
Number, row count signal, frame count signal, end signal, write control level signal, write commencing signal, write initial address, write-in length
Degree, control level signal is read, read commencing signal, read initial address and reads length.
5. device according to claim 1, the memory modules include：
Signal controller, it is connected with data integrator, for obtaining the integration information；
Read-write controller, according to the synchronous control signal integrated in information, internally deposit into row and read and/or write integral data.
6. device according to claim 1, in addition to：
Transport module, including multiple transmission units, the transport module is used for the multi-path asynchronous information for receiving extraneous output, and transmits
The number of unit is consistent with the number of multi-path asynchronous information.
A kind of 7. transfer control method of multi-path asynchronous information, suitable for the multi-path asynchronous letter as described in claim 1 to 5 is any
The transmission control unit of breath, including：
Receive the multi-path asynchronous information of extraneous output and integrated, integrated information all the way, the asynchronous information includes different
Step data and asynchronous control signal, the integration information include integral data and synchronous control signal, the number of ping-pong operation module
Mesh is consistent with the number of multi-path asynchronous information；
According to the synchronous control signal, integral data is read and/or write；
Obtain the integration information of data integrator output and obtain the integral data being had been written into memory modules.
8. according to the method for claim 7, wherein, the synchronous control signal includes：Line synchronising signal, first dielectric letter
Number, row count signal, frame count signal, end signal, write control level signal, write commencing signal, write initial address, write-in length
Degree, control level signal is read, read commencing signal, read initial address and reads length.
9. the method according to claim 11, wherein, in the integration information and the memory modules that obtain data integrator output
The integral data having been written into, specifically includes step：
When writing in synchronous control signal control level signal for it is high when, read-write controller is according to writing commencing signal, write initially
Location and write-in length, internal memory is write by integral data；
When the reading in synchronous control signal control level signal for it is high when, read-write controller according to read commencing signal, read initially
Location and reading length, read integral data, and output this to processor interface from internal memory.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116719755A (en) * | 2023-08-10 | 2023-09-08 | 浪潮电子信息产业股份有限公司 | Method, device and equipment for multi-application memory access |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7111093B2 (en) * | 2003-06-23 | 2006-09-19 | Intel Corporation | Ping-pong buffer system having a buffer to store a subset of data from a data source |
| CN202929411U (en) * | 2012-12-10 | 2013-05-08 | 威海北洋电气集团股份有限公司 | FPGA-based continuous uploaded high speed data acquisition device |
| CN104935885A (en) * | 2015-06-04 | 2015-09-23 | 电子科技大学 | AXI bus based extensible multi-channel image acquisition device |
-
2017
- 2017-09-14 CN CN201710831338.5A patent/CN107608654B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7111093B2 (en) * | 2003-06-23 | 2006-09-19 | Intel Corporation | Ping-pong buffer system having a buffer to store a subset of data from a data source |
| CN202929411U (en) * | 2012-12-10 | 2013-05-08 | 威海北洋电气集团股份有限公司 | FPGA-based continuous uploaded high speed data acquisition device |
| CN104935885A (en) * | 2015-06-04 | 2015-09-23 | 电子科技大学 | AXI bus based extensible multi-channel image acquisition device |
Non-Patent Citations (1)
| Title |
|---|
| 杨林楠: "基于FPGA的高速多路数据采集系统的设计", 《开发研究与设计技术》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116719755A (en) * | 2023-08-10 | 2023-09-08 | 浪潮电子信息产业股份有限公司 | Method, device and equipment for multi-application memory access |
| CN116719755B (en) * | 2023-08-10 | 2023-11-07 | 浪潮电子信息产业股份有限公司 | Method, device and equipment for multi-application memory access |
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