CN106886177A - A kind of Radar Signal Processing System - Google Patents
A kind of Radar Signal Processing System Download PDFInfo
- Publication number
- CN106886177A CN106886177A CN201611169624.1A CN201611169624A CN106886177A CN 106886177 A CN106886177 A CN 106886177A CN 201611169624 A CN201611169624 A CN 201611169624A CN 106886177 A CN106886177 A CN 106886177A
- Authority
- CN
- China
- Prior art keywords
- fpga
- control unit
- module
- radar
- dsp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/21—Pc I-O input output
- G05B2219/21037—Serial time multiplex bus, programming each module with one delayed line TDM
Abstract
The present invention relates to a kind of Radar Signal Processing System, the FPGA pretreatment modules, for being pre-processed to radar information；The DSP processes array, for processing pretreated radar information；The multimode load-on module, for different preprocessor to be loaded into FPGA pretreatment modules according to different instruction；The power managed module, is managed for the power supply power consumption to system；The state administration module, for the status information of the system to be sent to the main control unit of radar system, and receives the feedback information of the main control unit.The system plays the features of FPGA and DSP using the hardware handles framework of FPGA+DSP, completes Complex Radar information processing algorithm real-time operation, is capable of achieving the maximum efficiency-cost ratio of dense information treatment；The memory bottleneck of DSP and FPGA is solved the problems, such as using DDR3 and high-speed SRAM technology.
Description
Technical field
The invention belongs to digital processing field, it is related to a kind of Radar Signal Processing System, more particularly to one kind to be used for
C6678 the and Xilinx companies high-performance FPGA-V6 chips of TI companies are the signal processing system of primary processor.
Background technology
With the introducing of complex radar signal Processing Algorithm, the computing capability and real-time of hardware system are proposed higher
Requirement.Currently, it is an important channel of raising process performance using parallel processing technique.In order to meet signal transacting for
Process performance increasing need, parallel multiprocessor collaboration treatment is the effective ways for improving system processing power.
One important development trend of radar system is the real-time of computing and the high-throughput of data, particularly in SAR
In imaging radar system, the computing of data, transmission, storage have turned into one of critical bottleneck of restriction performance indications with reading.Pass
The Radar Signal Processing System function limitation of system, poor compatibility and equipment scale is larger has had a strong impact on versatility, the spirit of system
Activity and extended capability, cannot meet modern radar real-time signal transacting demand at a high speed.
Signal processing system as whole digital information processing system core, it is desirable to have high operational capability and data
Handling capacity.The features such as high bandwidth of high-speed serial data transmission technology, low bit error, high flexibility, becomes New Type Radar letter
The parallel shared bus standards such as the main flow of number processing system bussing technique, traditional PCI/CPCI cannot meet high accuracy, high score
The mass data transfers of resolution radar need.
The content of the invention
For problem above, the present invention uses the Keystone series high-performance multi-core DSP processors TMS320C6678 of TI
And the large-scale F PGA-V6 chips of Xilinx companies constitute the high-performance based on 4DSP+FPGA frameworks, high integration, height
Density, the hardware system of low-power consumption, can be applied to the radars such as SAR/ISAR imagings, pulse detection, SAR image match cognization letter
Number process field.The hardware system hardware logic aboundresources, disposal ability is powerful, by SRIO, GTX, PCIe and
Various advanced HSSI High-Speed Serial Interfaces such as Heyperlink realize the data communication and interconnection between processor and equipment, reserve
Various external interfaces are used for strengthening the versatility and expandability of the signal processing system including LVDS, TTL etc..External storage
Array extends memory capacity and improves access rate using DDR3 technologies.It is mutual by high-performance treatments array, high-speed bus
Even built with storage array ground, the system can realize mass data processing, storage and transmit.
Technical scheme is as follows：
A kind of Radar Signal Processing System, including：FPGA pretreatment modules, DSP treatment array, storage array, multimode add
Carry module, power managed module and state administration module；Wherein,
The FPGA pretreatment modules, for being pre-processed to radar information；
The DSP processes array, for processing pretreated radar information；
The storage array, the radar information for processing the FPGA pretreatment modules and the DSP ARRAY PROCESSING
Stored；
The multimode load-on module, for different preprocessor to be loaded into FPGA pretreatment moulds according to different instruction
Block；
The power managed module, is managed for the power supply power consumption to system；
The state administration module, the main control unit for the status information of the system to be sent to radar system, and
Receive the feedback information of the main control unit.
Further, the DSP treatment array is made up of 4 processors；4 processors are divided into two groups in equal size,
Two sub- processing modules are constituted, each described subprocessing module includes a primary processor and a coprocessor；Two sons
The data interaction of full duplex is realized between processing module by SRIO and Gbe buses；Pass through between primary processor and coprocessor
Heyperlink and PCIe high-speed serial bus realize the data interaction of full duplex.
Further, the storage array is mainly made up of DDR3 and DDR2 SRAM storage arrays；Wherein, 4 are had
DDR2 SRAM are connected with FPGA pretreatment modules, data reading mode using double along triggering, caching for data transfer or
Storage pulse pressure matching factor and phase Code.
Further, the multimode load-on module includes control unit FPGA and memory cell Nor Flash, by control
Unit F PGA (S3) is used to that different preprocessor to be loaded into FPGA pretreatment modules according to different instruction, so as to realize thunder
Up to the pretreatment of information, the pretreatment includes pulse, SAR or ISAR imaging.
Further, the power managed module is used to be managed specially the power supply power consumption of system：The power consumption
Respectively be managed the power supply of the control section of system and process part by management module, wherein, control section is control unit
FPGA, process part is the FPGA pretreatment modules and DSP treatment arrays；Upper electricity is always maintained to control section；When
During holding state, by electricity under process part；When working properly, by electricity in process part.
Further, the state administration module shares control unit FPGA with the multimode load-on module, specially：Institute
State the status information of control unit FPGA systems described in Real-time Collection by way of LVTTL level signals, and by the state
Information package and feeds back to main control unit into the status command frame of predetermined format；Main control unit receives the status command frame, and
Whether the state according to processing system has exception to make corresponding feedback processing.
Further, when radar works on power, the multimode load-on module is according to different instruction by different pretreatments
Program is loaded into FPGA pretreatment modules；The signal condition that control unit FPGA is monitored to it in real time is acquired, and is sent to
The main control unit of radar system；FPGA pretreatment modules have by the different preprocessor of the instruction loading of multimode load-on module
Body includes：
During loading pulse processing routine, the radar sended over by GTX HSSI High-Speed Serial Interfaces reception collection plate is located in advance
Reason data, complete after pulse pressure and velocity compensation, are cached in plug-in SRAM by interception points, complete correlative accumulation treatment,
Result is sent to DSP by SRIO and processes array；
During loading imaging processing routine, the radar pretreatment that collection plate is sended over is received by GTX HSSI High-Speed Serial Interfaces
Data, complete after pulse pressure and correction of walking about, and are cached in plug-in SRAM by interception points, complete orientation treatment, will locate
Reason result is distributed to DSP and processes array by SRIO；
DSP treatment arrays complete the treatment of SAR/ISAR or monopulse radar detection information.
Further, the working method of multimode load-on module is：When program burn writing, DSP will by asynchronous serial port interface
Routine data is sent to control unit FPGA, and the data that control unit FPGA will be received are written in program Flash, so that complete
Into the program burn writing for the treatment of FPGA；When program is loaded, control unit FPGA is instructed by parsing loading procedure, from program
Corresponding program is read in Flash, data configuration is carried out by loading sequential, so as to realize the loading of program.
According to above-mentioned technical proposal, beneficial effects of the present invention are：
(1) system is made up of 1 treatment FPGA (V6)+1 control unit FPGA (S3)+4C6678 frameworks, wherein control is single
First FPGA (S3) is responsible for upper electricity, reset and clock configuration, the treatment FPGA journeys of 1 treatment FPGA (V6)+4C6678 and ancillary equipment
The function such as sequence loading and system mode collection；Treatment FPGA (V6) be responsible for distance by radar pulse pressure, velocity compensation, correction of walking about,
The radar such as correlative accumulation, projection Preprocessing Algorithm is realized；4C6678 constitute two-by-two DSP treatment submodule, by SRIO,
The high-speed serial bus such as Heyperlink, PCIe, Gbe realize treatment submodule between, the data interaction between main coprocessor, pass through
SRIO buses realize mass data transfers with treatment FPGA (V6), and director data is realized with treatment FPGA (V6) by EMIF buses
Interaction, is finally completed the final process result for obtaining radar information.The system is played using the hardware handles framework of FPGA+DSP
The features of FPGA and DSP, complete Complex Radar information processing algorithm real-time operation, are capable of achieving the maximum effect of dense information treatment
Take ratio.
(2) system solves the problems, such as the memory bottleneck of DSP and FPGA using DDR3 and high-speed SRAM technology.Every
The DDR3 memories of plug-in 4 16 bit wides of C6678, maximum storage capacity reaches 4GByte, and most fast storage speed reaches 1600MHz, can
For storing radar information processing intermediate variable.The plug-in 4 DDR2 SRAM high speed storing chips of FPGA, monolithic memory capacity reaches
288Mb, can be used to store pulse pressure matching factor, distance to information such as pulse pressure data.
(3) system is realized using multimode loading technique and is loading difference with the different time sections in once working on power
Processing routine, realizes the function of different disposal algorithm.The method can solve complicated algorithm time-sharing work, while realizing taking hardware
The excessive contradiction of resource, extends system use condition, lifting system disposal ability.
(4) by designing compact, high performance-price ratio Radar Signal Processing System, set so as to substantially reduce software, hardware
Meter difficulty, shortens the construction cycle, is mainly reflected in the following aspects：(1) treatment speed-up ratio and parallel efficiency, including number are improved
According to the efficiency for the treatment of, transmission and real time algorithm；(2) software and hardware design cost is reduced using modular method, is shortened
Design cycle；(3) optimize DLL and interface, so as to mitigate the live load of software designer, letter can be absorbed in
The consideration of number Processing Algorithm, improves exploitation and the maintenance levels of software.
Brief description of the drawings
Fig. 1 is Radar Signal Processing System block diagram；
Fig. 2 is treatment array composition；
Fig. 3 is storage array schematic diagram；
Fig. 4 is that multimode loads schematic diagram.
Specific embodiment
Specific embodiments of the present invention is described in detail below in conjunction with the accompanying drawings.
Fig. 1 is Radar Signal Processing System block diagram, and Fig. 2 is treatment array composition, and Fig. 3 is storage array schematic diagram, Fig. 4
For multimode loads schematic diagram.
System in the specific embodiment of the invention includes that DSP processes array, and FPGA pretreatment modules, storage array is more
Mould load-on module, the functional module such as power managed and state supervision.
A kind of Radar Signal Processing System, including：DSP processes array, and FPGA pretreatment modules, storage array, multimode add
Carry module, the functional module such as power managed and state supervision；Wherein,
The DSP treatment array is mainly used to complete such as SAR/ISAR imagings, pulse, SAR image matching and recognizes
Complex Radar information processing algorithm.Primary processor is from 8 newest core TMS320C6678 processors of TI companies, monokaryon highest master
Frequency reaches 1.25GHz, and monokaryon floating-point disposal ability is 20GFLOP/s (fixed-point processing ability is 40GMAC/s), is industry treatment energy
The most strong processor of power.Meanwhile, the processor has superpower data transfer and storage capacity, be not only integrated with SRIO,
The low speed bus such as the high-speed serial bus such as Hyperlink, PCIe, Gbe, also EMIF16, TSIP, UART, SPI, I2C, including
L1, L2 and L3 support cache technologies in interior abundant internal storage resources, and external storage interface supports that vast capacity DDR3 is deposited
Reservoir.
With reference to radar data treatment and transmission feature, DSP treatment arrays are made up of 4 TMS320C6678 processors, will be located
4 processors for managing array are divided into two groups, constitute two sub- processing modules and symmetrical treatment framework, and subprocessing module is divided again
It is primary processor and coprocessor, is easy to data parallel and collaboration to process.Subprocessing intermodule is realized by SRIO and Gbe buses
The data interaction of full duplex, the maximum data exchange rate is up to 13.5Gbps；Pass through between primary processor and coprocessor
Heyperlink and PCIe high-speed serial bus realize the data interaction of full duplex, and the maximum data exchange rate is reachable
17.5Gbps；The primary processor of two subprocessing modules is respectively by respective SRIO, EMIF16, TSIP, UART, SPI, I2C etc.
The data/address bus of high, normal, basic three kinds of speed carries out data interaction with FPGA, and the maximum data exchange rate is more than 12.5Gbps；Two sons
The coprocessor of processing module can also be by carrying out data interaction outside Gbe buses and system, and speed is up to 1Gbps.
The FPGA pretreatment modules be mainly used in completing greatly points floating-point pulse pressure, velocity compensation, correction of walking about, projection,
The radar Preprocessing Algorithm such as correlative accumulation.From the Virtex6-475T FPGA of Xilinx companies, possess abundant logic, multiply
Musical instruments used in a Buddhist or Taoist mass, clock and storage resource, I/O interface flexibles, and including 20x high speed GTX buses, be capable of achieving and between DSP or FPGA at a high speed
Bus interconnection.Wherein, 8x GTX and two sub- processing module interconnection, data exchange rate reach 25Gbps；Other 12x GTX are used
In inter-system data interaction, data exchange rate reaches 37.5Gbps.Using FPGA full parellels stream treatment and mass data
Interaction capabilities, realize the pretreatment and transfer of whole signal processing system data so that system data treatment and interface are more clever
Living, applicability is stronger.
The storage array is mainly made up of DDR3 and SRAM storage arrays.C6678 has 64 special EMIF DDR3 total
Line, single processor maximum capacity extends to 4GB, and highest access speed is up to 1600MHz, and storage total bandwidth is reachable
800Gbps, can be used for store radar data real time process intermediate data and variable, extend treatment array storage and
Disposal ability, it is ensured that the validity and real-time of data interaction.The plug-in 4 currently advanced ultrahigh speed static state DDR2 of FPGA
SRAM, monolithic bit wide is 36, storage depth 8M, and, up to 330MHz, data reading mode is using double along tactile for highest access speed
Hair, makes memory bandwidth be doubled, and can be used for the caching of data transfer or storage pulse pressure matching factor, phase Code etc., significantly
Improve the ability of FPGA pretreatments and the processing framework of optimization FPGA.
The multimode load-on module refers to complete processing system according to different instruction by a control unit FPGA (S3)
The loading of the different pretreatments programs such as pulse, SAR or ISAR imaging is realized in treatment FPGA (V6), is capable of achieving single board timesharing
Realize difference in functionality.Mainly it is made up of control unit FPGA (S3) and Large Copacity Nor Flash, is realized by remote loading technology
The program Solidification of processing system treatment FPGA (V6) or renewal, the loading of difference in functionality program is realized by instruction.Make specific
With under environment, can be saved by way of this kind of time-sharing multiplex system hardware cost and reduce system power dissipation.
The power managed refers to separately to set the power supply of the control section (S3) of system and process part (V6+4DSP)
Meter, using programmable power supply technology, by the control section (S3) of processing system by actual task requirement to process part (V6+
Power module 4DSP) carries out switch control, reduces stand-by power consumption and heating, lifting system working time, so as to reach property high
The purpose of the energy reliable and stable work of processing system ultra-long time.
The state supervision refers to that all status informations of processing system are passed through into LVTTL in real time by control unit FPGA (S3)
The mode of level signal is acquired, and all status informations are packaged into predetermined command frame, feeds back to main control unit.Master control
Unit reception state command frame, and timing query feedback result, and whether abnormal making accordingly is had according to the state of processing system
Treatment.By state regulation technique, the purpose of real-time monitoring each module working condition of Complex Electronic Systems Based is capable of achieving, it is ensured that system
Reliable and stable work.
Radar Signal Processing System is by high speed serial bus technology realities such as SRIO, GTX, Heyperlink, PCIe, Gbe
Mass data transfers between existing system and between processor with interact, realize instructing DBMS between DSP and FPGA by EMIF buses
Exchange；Mass data storage is realized by ultrahigh speed DDR3 and DDR2 technology；Hardware system is realized by multimode loading technique
Timesharing multifunctional multiplexing；By power managed and state be concurrently in charge of technology realize that processing system is long when, reliably working.Above technology
Successful Application so that the bus topolopy of the system is reasonable in design, parallel processing, chip chamber between data transfer mode and plate
And the technology such as parallel processing is organically merged in chip, the disposal ability and data throughput capabilities of system are performed to
Maximum.
Specific works mode is described as follows：
A kind of Radar Signal Processing System, including：DSP processes array, and FPGA pretreatment modules, storage array, multimode adds
Carry module, power managed module and state administration module；
When radar works on power, be loaded into for different preprocessor according to different instruction by the multimode load-on module
FPGA pretreatment modules；The signal condition that control unit FPGA is monitored to it in real time is acquired, and is sent to radar system
Main control unit；FPGA pretreatment modules are specifically included by the different preprocessor of the instruction loading of multimode load-on module：
During loading pulse processing routine, the radar sended over by GTX HSSI High-Speed Serial Interfaces reception collection plate is located in advance
Reason data, complete after pulse pressure and velocity compensation, are cached in plug-in SRAM by interception points, complete correlative accumulation treatment,
Result is sent to DSP by SRIO and processes array；
During loading imaging processing routine, the radar pretreatment that collection plate is sended over is received by GTX HSSI High-Speed Serial Interfaces
Data, complete after pulse pressure and correction of walking about, and are cached in plug-in SRAM by interception points, complete orientation treatment, will locate
Reason result is distributed to DSP and processes array by SRIO；
DSP treatment arrays complete the treatment of SAR/ISAR or monopulse radar detection information.
As shown in figure 1, signal processing system is mainly by 1 Xilinx high-performance FPGA Virtex6 315T as treatment
FPGA, 1 Xilinx low side FPGA Spartan3 are used as control unit FPGA, 4 TI companies high-performance processors
TMS320C6678 realizes high density calculation process as processor array.Being realized by GTX interfaces for treatment FPGA is high between plate
Speed interconnection.Treatment FPGA is realized and outside other cell interconnections by LVDS interface, for realizing communication between plates instruction transmission.Place
Reason is realized being interacted with the state of other boards with control unit FPGA by I/O port.
As shown in Fig. 2 realizing full connection using high-speed serial bus between treatment array and FPGA.FPGA and DSPA is (main
Processor 1) interconnection is realized by SRIO buses and between DSPB (primary processor 2), (association is processed for DSPC (coprocessor 1) and DSPD
Device 2) realize that chip chamber is interconnected by SRIO buses, DSPA and DSPD, DSPB and DSPC realize interconnecting by Heyperlink,
DSPA and DSPB, DSPC and DSPD realize interconnecting by PCIe, and other 3 road 4lane GTX buses of FPGA are outside by connector
Extension.
As shown in figure 3, DDR3 chip of the plug-in 4 4Gb maximum operating frequencies of each DSP for 1600MHz, and plug-in 1
The Nor Flash of 512Mb and 1 SPI program Flash of 128Mb, constitute the storage system of DSP, and DSP can be by distinct program
Different storage address sections are cured to, after upper electricity, the program of distinct program section can be loaded according to different instruction, realize different work(
Can, enhance the flexibility of system treatment.
As shown in figure 4, the working method of multimode load-on module is：When program burn writing, DSP will by asynchronous serial port interface
Routine data is sent to control unit FPGA, and the data that control unit FPGA will be received are written in program Flash, so that complete
Into the program burn writing for the treatment of FPGA；When program is loaded, control unit FPGA is instructed by parsing loading procedure, from program
Corresponding program is read in Flash, data configuration is carried out by loading sequential, so as to realize the loading of program.
Compared with prior art, the invention uses FPGA+DSP processing frameworks, play FPGA input/output interfaces flexibly and
The features such as parallel pipelining process treatment and DSP focus on ability by force and be easily programmed, makes system be more convenient to realize complicated algorithm work(
Can, and possess stronger processing capability in real time.Prevent by using high-speed transfer and storage, multi-mode loading, power managed, heat
The multinomial key technology such as shield and state supervision, solves existing processing system versatility, flexibility and extended capability deficiency etc. and lacks
Point, construct a high-performance power dissipation ratio, high integration, high density, high reliability and can be long when the signal transacting that works it is general
Hardware system, takes multinomial effective safeguard procedures so that stable system performance reliability.
The present invention separately designs control and processing function, and Module Division is carried out by function, and circuit design and function are divided
It is more reasonable.
Above-mentioned specific embodiment is only used for explaining and illustrate technical scheme, but can not constitute will to right
The restriction of the protection domain asked.It will be apparent to those skilled in the art that doing any letter on the basis of technical scheme
New technical scheme, will fall under the scope of the present invention obtained from single deformation or replacement.
Claims (8)
1. a kind of Radar Signal Processing System, it is characterised in that the system includes：FPGA pretreatment modules, DSP treatment battle arrays
Row, storage array, multimode load-on module, power managed module and state administration module；Wherein,
The FPGA pretreatment modules, for being pre-processed to radar information；
The DSP processes array, for processing pretreated radar information；
The storage array, is carried out for the radar information to the FPGA pretreatment modules and DSP treatment ARRAY PROCESSINGs
Storage；
The multimode load-on module, for different preprocessor to be loaded into FPGA pretreatment modules according to different instruction；
The power managed module, is managed for the power supply power consumption to system；
The state administration module, for the status information of the system to be sent to the main control unit of radar system, and receives
The feedback information of the main control unit.
2. the system as claimed in claim 1, it is characterised in that the DSP treatment array is made up of 4 processors；Described 4
Processor is divided into two groups in equal size, constitutes two sub- processing modules, and each described subprocessing module includes a primary processor
With a coprocessor；The data interaction of full duplex is realized between two sub- processing modules by SRIO and Gbe buses；Primary processor
The data interaction of full duplex is realized by Heyperlink and PCIe high-speed serial bus and between coprocessor.
3. the system as claimed in claim 1, it is characterised in that the storage array is main by DDR3 and DDR2SRAM storage battle arrays
Row composition；Wherein, have 4 DDR2SRAM to be connected with FPGA pretreatment modules, data reading mode, along triggering, is used using double
In the caching or storage pulse pressure matching factor and phase Code of data transfer.
4. the system as claimed in claim 1, it is characterised in that the multimode load-on module includes control unit FPGA and storage
Unit Nor Flash, are used to be loaded into different preprocessor according to different instruction by control unit FPGA (S3)
FPGA pretreatment modules, so as to realize the pretreatment of radar information, the pretreatment includes pulse, SAR or ISAR imaging.
5. the system as claimed in claim 1, it is characterised in that the power managed module is used to enter the power supply power consumption of system
Row management is specially：Respectively be managed the power supply of the control section of system and process part by the power managed module, its
In, control section is control unit FPGA, and process part is the FPGA pretreatment modules and DSP treatment arrays；To control
System part is always maintained at electricity；When holding state, by electricity under process part；When working properly, by electricity in process part.
6. the system as claimed in claim 1, it is characterised in that the state administration module is shared with the multimode load-on module
Control unit FPGA, specially：Described control unit FPGA systems described in Real-time Collection by way of LVTTL level signals
Status information, and the status information is packaged into the status command frame of predetermined format, and feed back to main control unit；Main control unit
The status command frame is received, and whether there is exception to make corresponding feedback processing according to the state of processing system.
7. the system as any one of claim 1-6, it is characterised in that when radar works on power, the multimode adds
Carry module and different preprocessor is loaded into by FPGA pretreatment modules according to different instruction；Control unit FPGA is in real time to it
The signal condition monitored is acquired, and is sent to the main control unit of radar system；FPGA pretreatment modules are loaded by multimode
The preprocessor that the instruction loading of module is different is specifically included：
During loading pulse processing routine, the radar pretreatment number that collection plate is sended over is received by GTX HSSI High-Speed Serial Interfaces
According to, complete after pulse pressure and velocity compensation, it is cached in plug-in SRAM by interception points, correlative accumulation treatment is completed, will locate
Reason result is sent to DSP and processes array by SRIO；
During loading imaging processing routine, the radar preprocessed data that collection plate is sended over is received by GTX HSSI High-Speed Serial Interfaces,
Complete after pulse pressure and correction of walking about, be cached in plug-in SRAM by interception points, orientation treatment is completed, by result
DSP is distributed to by SRIO and processes array；
DSP treatment arrays complete the treatment of SAR/ISAR or monopulse radar detection information.
8. the system as any one of claim 1-7, it is characterised in that the working method of multimode load-on module is：When
During program burn writing, routine data is sent to control unit FPGA by DSP by asynchronous serial port interface, and control unit FPGA will be received
To data be written in program Flash so that complete process FPGA program burn writing；When program is loaded, control unit
FPGA is instructed by parsing loading procedure, and corresponding program is read from program Flash, and data configuration is carried out by loading sequential, from
And realize the loading of program.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611169624.1A CN106886177B (en) | 2016-12-16 | 2016-12-16 | Radar signal processing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611169624.1A CN106886177B (en) | 2016-12-16 | 2016-12-16 | Radar signal processing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106886177A true CN106886177A (en) | 2017-06-23 |
| CN106886177B CN106886177B (en) | 2020-07-17 |
Family
ID=59176374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611169624.1A Active CN106886177B (en) | 2016-12-16 | 2016-12-16 | Radar signal processing system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106886177B (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108169746A (en) * | 2017-12-21 | 2018-06-15 | 南京理工大学 | Chirp Semi-active RADAR guidance header signal processing method |
| CN108563144A (en) * | 2018-03-30 | 2018-09-21 | 西安电子科技大学 | A kind of missile-borne radar signal processing semi-hardware type simulation test system |
| CN109444886A (en) * | 2018-12-30 | 2019-03-08 | 成都汇蓉国科微系统技术有限公司 | A kind of parallel computation processing method, system and the medium of Bistatic SAR real time imagery |
| CN109613491A (en) * | 2018-12-24 | 2019-04-12 | 上海威固信息技术股份有限公司 | A kind of high-speed signal acquisition storage and playback system based on FPGA |
| CN109633613A (en) * | 2018-11-20 | 2019-04-16 | 上海无线电设备研究所 | A kind of FPGA implementation method of hypersonic Platform Alliance pulse compression and the compensation of bullet speed |
| CN109753478A (en) * | 2018-12-30 | 2019-05-14 | 成都汇蓉国科微系统技术有限公司 | A kind of parallel data processing method based on FPGA, device |
| CN110687842A (en) * | 2019-10-14 | 2020-01-14 | 理工雷科电子(西安)有限公司 | Management platform health status monitoring system based on SRIO network |
| CN111538259A (en) * | 2020-03-31 | 2020-08-14 | 北京卫星制造厂有限公司 | Multi-processor platform cooperative control system and method for aerospace fuel cell power system |
| CN111580057A (en) * | 2019-02-19 | 2020-08-25 | 北京华航无线电测量研究所 | Moving target echo range migration correction method |
| CN112946580A (en) * | 2021-01-14 | 2021-06-11 | 无锡国芯微电子系统有限公司 | Multiprocessor cooperative radiation source frequency parameter estimation device and method |
| CN116132666A (en) * | 2023-04-13 | 2023-05-16 | 四川赛狄信息技术股份公司 | FPGA-based video image processing method and system |
| CN116660899A (en) * | 2023-08-01 | 2023-08-29 | 西安电子科技大学 | Near-field target ISAR imaging system and device based on FPGA+DSP |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5822615A (en) * | 1995-05-26 | 1998-10-13 | Mitsubishi Denki Kabushiki Kaisha | Control method for automatic gathering of status data for distributed type remote I/O control system at start-up |
| EP0918267A2 (en) * | 1993-10-29 | 1999-05-26 | Matsushita Electric Industrial Co., Ltd. | Method for transforming failure transitions of the finite-state machine into a succes transitions |
| CN102520396A (en) * | 2012-01-04 | 2012-06-27 | 西安电子科技大学 | Time-varying narrow-band interference suppression method based on complex empirical mode decomposition |
| CN102590811A (en) * | 2012-01-13 | 2012-07-18 | 西安电子科技大学 | Small FMCW-based (frequency modulated continuous wave) SAR (synthetic aperture radar) imaging system by using FPGA (field programmable gate array) |
| CN103116872A (en) * | 2013-01-25 | 2013-05-22 | 西安电子科技大学 | Synthetic aperture radar (SAR) image high-speed processing system and method based on parallel digital signal processors (DSPs) |
| CN103278806A (en) * | 2013-06-08 | 2013-09-04 | 北京理工大学 | Method for removing target detection Doppler dispersion of broadband signals based on sub-band processing |
| CN103793355A (en) * | 2014-01-08 | 2014-05-14 | 西安电子科技大学 | General signal processing board card based on multi-core DSP (digital signal processor) |
| CN103869292A (en) * | 2014-04-02 | 2014-06-18 | 清华大学 | General purpose radar imaging processing system based on embedded GPU |
| CN203858623U (en) * | 2014-04-29 | 2014-10-01 | 赫兹曼电力（广东）有限公司 | Simple FPGA dynamic configuration structure |
| CN104931938A (en) * | 2015-05-07 | 2015-09-23 | 清华大学 | Coherent agile frequency radar clutter inhibition method and system |
| CN105467378A (en) * | 2014-09-04 | 2016-04-06 | 苏州声光达水下探测仪器有限公司 | Multi-beam depth-sounding sonar signal processing board based on fixed/floating-point processor |
-
2016
- 2016-12-16 CN CN201611169624.1A patent/CN106886177B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0918267A2 (en) * | 1993-10-29 | 1999-05-26 | Matsushita Electric Industrial Co., Ltd. | Method for transforming failure transitions of the finite-state machine into a succes transitions |
| US5822615A (en) * | 1995-05-26 | 1998-10-13 | Mitsubishi Denki Kabushiki Kaisha | Control method for automatic gathering of status data for distributed type remote I/O control system at start-up |
| CN102520396A (en) * | 2012-01-04 | 2012-06-27 | 西安电子科技大学 | Time-varying narrow-band interference suppression method based on complex empirical mode decomposition |
| CN102590811A (en) * | 2012-01-13 | 2012-07-18 | 西安电子科技大学 | Small FMCW-based (frequency modulated continuous wave) SAR (synthetic aperture radar) imaging system by using FPGA (field programmable gate array) |
| CN103116872A (en) * | 2013-01-25 | 2013-05-22 | 西安电子科技大学 | Synthetic aperture radar (SAR) image high-speed processing system and method based on parallel digital signal processors (DSPs) |
| CN103278806A (en) * | 2013-06-08 | 2013-09-04 | 北京理工大学 | Method for removing target detection Doppler dispersion of broadband signals based on sub-band processing |
| CN103793355A (en) * | 2014-01-08 | 2014-05-14 | 西安电子科技大学 | General signal processing board card based on multi-core DSP (digital signal processor) |
| CN103869292A (en) * | 2014-04-02 | 2014-06-18 | 清华大学 | General purpose radar imaging processing system based on embedded GPU |
| CN203858623U (en) * | 2014-04-29 | 2014-10-01 | 赫兹曼电力（广东）有限公司 | Simple FPGA dynamic configuration structure |
| CN105467378A (en) * | 2014-09-04 | 2016-04-06 | 苏州声光达水下探测仪器有限公司 | Multi-beam depth-sounding sonar signal processing board based on fixed/floating-point processor |
| CN104931938A (en) * | 2015-05-07 | 2015-09-23 | 清华大学 | Coherent agile frequency radar clutter inhibition method and system |
Non-Patent Citations (1)
| Title |
|---|
| 原涛: "一种弹载SAR实时成像信号处理机设计", 《中国优秀硕士学位论文全文数据库（电子期刊）信息科技辑》 * |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108169746B (en) * | 2017-12-21 | 2021-09-21 | 南京理工大学 | Linear frequency modulation pulse semi-active radar seeker signal processing method |
| CN108169746A (en) * | 2017-12-21 | 2018-06-15 | 南京理工大学 | Chirp Semi-active RADAR guidance header signal processing method |
| CN108563144A (en) * | 2018-03-30 | 2018-09-21 | 西安电子科技大学 | A kind of missile-borne radar signal processing semi-hardware type simulation test system |
| CN109633613A (en) * | 2018-11-20 | 2019-04-16 | 上海无线电设备研究所 | A kind of FPGA implementation method of hypersonic Platform Alliance pulse compression and the compensation of bullet speed |
| CN109613491A (en) * | 2018-12-24 | 2019-04-12 | 上海威固信息技术股份有限公司 | A kind of high-speed signal acquisition storage and playback system based on FPGA |
| CN109613491B (en) * | 2018-12-24 | 2024-02-09 | 上海威固信息技术股份有限公司 | High-speed signal acquisition, storage and playback system based on FPGA |
| CN109444886A (en) * | 2018-12-30 | 2019-03-08 | 成都汇蓉国科微系统技术有限公司 | A kind of parallel computation processing method, system and the medium of Bistatic SAR real time imagery |
| CN109753478A (en) * | 2018-12-30 | 2019-05-14 | 成都汇蓉国科微系统技术有限公司 | A kind of parallel data processing method based on FPGA, device |
| CN109444886B (en) * | 2018-12-30 | 2020-06-26 | 成都汇蓉国科微系统技术有限公司 | Parallel computing processing method, system and medium for bistatic SAR real-time imaging |
| CN111580057A (en) * | 2019-02-19 | 2020-08-25 | 北京华航无线电测量研究所 | Moving target echo range migration correction method |
| CN110687842A (en) * | 2019-10-14 | 2020-01-14 | 理工雷科电子(西安)有限公司 | Management platform health status monitoring system based on SRIO network |
| CN111538259A (en) * | 2020-03-31 | 2020-08-14 | 北京卫星制造厂有限公司 | Multi-processor platform cooperative control system and method for aerospace fuel cell power system |
| CN112946580A (en) * | 2021-01-14 | 2021-06-11 | 无锡国芯微电子系统有限公司 | Multiprocessor cooperative radiation source frequency parameter estimation device and method |
| CN116132666A (en) * | 2023-04-13 | 2023-05-16 | 四川赛狄信息技术股份公司 | FPGA-based video image processing method and system |
| CN116132666B (en) * | 2023-04-13 | 2023-06-27 | 四川赛狄信息技术股份公司 | FPGA-based video image processing method and system |
| CN116660899A (en) * | 2023-08-01 | 2023-08-29 | 西安电子科技大学 | Near-field target ISAR imaging system and device based on FPGA+DSP |
| CN116660899B (en) * | 2023-08-01 | 2023-10-13 | 西安电子科技大学 | Near-field target ISAR imaging system and device based on FPGA+DSP |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106886177B (en) | 2020-07-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106886177A (en) | A kind of Radar Signal Processing System | |
| US8598932B2 (en) | Integer and half clock step division digital variable clock divider | |
| CN102929836B (en) | Special ASIC (Application Specific Integrated Circuit) chip system for spaceflight | |
| CN105045763A (en) | FPGA (Field Programmable Gata Array) and multi-core DSP (Digital Signal Processor) based PD (Pulse Doppler) radar signal processing system and parallel realization method therefor | |
| CN103744644B (en) | The four core processor systems built using four nuclear structures and method for interchanging data | |
| CN102073481A (en) | Multi-kernel DSP reconfigurable special integrated circuit system | |
| CN105279133A (en) | VPX parallel DSP signal processing board card based on SoC online reconstruction | |
| CN104657330A (en) | High-performance heterogeneous computing platform based on x86 architecture processor and FPGA (Field Programmable Gate Array) | |
| WO2020103058A1 (en) | Programmable operation and control chip, a design method, and device comprising same | |
| CN110289859A (en) | Parallel time based on multi-disc ADC replaces High Speed Sampling System | |
| CN101509805A (en) | Multipath paralleling data acquisition system based on on-site programmable gate array | |
| CN105045566A (en) | Embedded parallel computing system and parallel computing method adopting same | |
| CN103365749A (en) | Multi-core processor debugging system | |
| CN104615386A (en) | Off-core cache device | |
| CN104598404B (en) | Computing device extended method and device and expansible computing system | |
| CN100343778C (en) | Transferring data between differently clocked busses | |
| Wang et al. | MOCA: An inter/intra-chip optical network for memory | |
| CN114746853A (en) | Data transfer between memory and distributed computing array | |
| CN202049232U (en) | High-performance general signal processor based on standard bus platform | |
| CN115114224A (en) | Flight control computer hardware system of SOC + FPGA | |
| Mulder et al. | Feeding high-bandwidth streaming-based FPGA accelerators | |
| CN103678202A (en) | DMA (direct memory access) controller of multicore processor | |
| KR20210021565A (en) | Hardware-based virtual-physical address translation for programmable logic masters within a system on a chip | |
| Hu et al. | A Noc Centric Low Overhead Multi-chip Interconnection Technology | |
| CN213399574U (en) | Extensible storage FPGA board card based on configurable memory group |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |