CN115114224A

CN115114224A - Flight control computer hardware system of SOC + FPGA

Info

Publication number: CN115114224A
Application number: CN202210646278.0A
Authority: CN
Inventors: 汪华松; 宋国庆; 毛仲君; 刘进; 徐海航; 叶德章; 魏建峰; 郭帅; 陈佳乐
Original assignee: Institute of Aerospace Technology of China Aerodynamics Research and Development Center
Current assignee: Institute of Aerospace Technology of China Aerodynamics Research and Development Center
Priority date: 2022-06-09
Filing date: 2022-06-09
Publication date: 2022-09-27

Abstract

The invention discloses a flight control computer hardware system of SOC + FPGA, relating to the technical field of flight control computer hardware systems, and the key points of the technical scheme are as follows: the system comprises an SOC unit, an FPGA unit and an auxiliary circuit, wherein the auxiliary circuit comprises an interface unit, a storage unit and a debugging unit, an ARM and a DSP in the SOC unit communicate in a mode of interrupting and sharing a memory space, and the FPGA unit interacts with the SOC unit through an EMIF (external memory interface) bus. The SOC unit in the flight control computer hardware system is an ARM + DSP dual-core heterogeneous processor, the FPGA is rich in interface resources, and based on the modularized development of the programmable logic device, the system not only can meet the requirements of the flight control system on characteristics of strong real-time performance, high operation precision and high flexibility, but also can simplify software and hardware design, reduce system power consumption and improve system reliability.

Description

Flight control computer hardware system of SOC + FPGA

Technical Field

The invention relates to the technical field of flight control computer hardware systems, in particular to a flight control computer hardware system of SOC + FPGA.

Background

The flight control computer is a core control system for the aircraft to complete flight tasks and is responsible for sensor data acquisition, control rate calculation, flight task scheduling and management and the like. For flight control hardware system architecture, the architecture is not limited to a single processor, but multiple processors are increasingly adopted to cooperatively complete tasks. Due to the limitation of on-chip resources and operational capability, a large number of additional auxiliary circuits are required for a single processor, so that the flight control software and hardware system is high in complexity and insufficient in instantaneity and reliability. The multiprocessor is most commonly constructed by two or more of ARM, DSP and FPGA, and has two kinds of isomorphic multi-core and heterogeneous multi-core. The isomorphic multi-core processor is single in type, so that the requirements of a flight control system on high real-time performance, high operation precision and flexible interface are difficult to meet at the same time. The heterogeneous multi-core mainly comprises ARM + DSP, ARM + FPGA, DSP + FPGA and ARM + DSP + FPGA, ARM transaction management capability in an ARM + DSP framework is strong, DSP operation capability is strong, IO (input/output) resources of the ARM and DSP processors are less than those of the FPGA, and interfaces have no universality and are insufficient in flexibility and expandability; due to the lack of a powerful DSP operation unit in the ARM + FPGA architecture, the high-precision floating-point operation capability is insufficient, and the real-time calculation of a complex algorithm is difficult to complete; the DSP + FPGA architecture is lack of ARM multi-task real-time management capability, so that the characteristics of multiple tasks, high complexity and strong real-time performance of the flight control system cannot be met; the ARM + DSP + FPGA architecture is a relatively comprehensive architecture, various microprocessors are combined with one another to make up for deficiencies, and the effect of improving the performance of flight control software and hardware systems is remarkable, so that the ARM + DSP + FPGA architecture is one of current research and development trends.

Therefore, the invention aims to provide a flight control computer hardware system of SOC + FPGA, and aims to solve the problems of poor real-time performance, low operation precision and flexibility, low system reliability and high system power consumption of the conventional flight control system.

Disclosure of Invention

The invention aims to solve the problems and provides a flight control computer hardware system of SOC + FPGA, wherein an SOC unit (system level chip) in the flight control computer hardware system adopts an ARM + DSP dual-core heterogeneous processor, the FPGA is rich in interface resources, and a programmable logic device is developed based on modularization.

1. The technical purpose of the invention is realized by the following technical scheme: a flight control computer hardware system of SOC + FPGA comprises an SOC unit, an FPGA unit and an auxiliary circuit, wherein the auxiliary circuit comprises an interface unit, a storage unit and a debugging unit;

the SOC unit is a dual-core heterogeneous processor, the kernel of the SOC unit is an ARM kernel and a DSP kernel, the ARM kernel and the DSP kernel are communicated with each other through a DSP L2RAM and an interrupt wire of a shared memory, the ARM kernel and the DSP kernel can both access the shared memory, and after data in a memory space is read and written, the other side is notified in an interrupt mode, so that the data are processed in time;

the FPGA unit is used for interface distribution and data transmission, is logically programmed through FPGA hardware and is configured to form an interface unit by combining with an external interface protection chip; the FPGA unit transmits data with the SOC unit through an EMIF bus;

the interface unit is used for meeting the hanging connection of various devices;

the storage unit is used for storing programs and data, and comprises a NAND-FlashA, a NAND-FlashB, a NOR-FlashC and a synchronous dynamic random access memory SDRAM, wherein the NOR-FlashC interacts with the SOC unit through an SPI bus and is used for storing programs; the synchronous dynamic random access memory SDRAM interacts with the SOC unit through a DDR bus to provide a memory space for the SOC unit; the NAND-FlashA and the NAND-FlashB interact with the SOC unit through an EMIF bus to perform mutual backup storage of data;

the debugging unit is used for developing and debugging programs;

the SOC unit sends a control instruction to the FPGA unit through an EMIF bus, and the FPGA unit controls the corresponding interface unit to work so as to realize the control of external equipment; when data are input into the interface unit, the FPGA unit processes the data in advance, sends an interrupt request to the SOC unit after the processing is finished, and after the SOC unit receives the interrupt, reads corresponding data according to the interrupt type to realize the interaction between the flight control unit and the external equipment.

In the scheme, on one hand, the complexity and the coupling of the program can be reduced, the software reliability is enhanced, the advantages of all processors are fully exerted, the control part is processed by the ARM, the complex operation is carried out by the DSP, the control and the algorithm are separated and independent, the complexity and the coupling of the program can be effectively reduced, and the software reliability is improved. On the other hand, the CPU load can be reduced, and the real-time performance of the system can be enhanced; the ARM core carries out task scheduling and management based on a real-time operating system, the DSP core carries out algorithm real-time calculation, and the FPGA unit carries out preprocessing on data from the interface unit, so that reasonable sharing of CPU load is realized, and the real-time performance of the system can be effectively improved. Moreover, the system can simplify the hardware design and reduce the power consumption of the system; through the SOC unit architecture of ARM kernel + DSP kernel, can construct the minimum system of dual-core with less auxiliary circuit, simplified hardware design, utilize the FPGA unit to carry out logic circuit modularized design, can improve development efficiency, also be favorable to improving system integration, reduce the consumption. In addition, the system can improve the flexibility and the expandability of the interface; the FPGA unit completes tasks such as interface timing sequence, interface expansion and the like, modular thought development is adopted, each unit module is independent and communicates with a bus, the unit modules are not related to each other, other modules of the system cannot be influenced by modifying a certain module, and the flexibility and the expandability of the system can be enhanced.

The invention is further configured to: the interface unit comprises a plurality of CAN ports, SPI ports, RS232 ports, RS422/485 ports, DAC ports, ADC ports, PWM ports and GPIO ports.

By adopting the technical scheme, the interface types of the interface unit are rich, and the requirement for hanging various devices is met.

The invention is further configured to: the interface unit realizes physical isolation between the FPGA unit and the interface unit by combining an ESD protection interface chip with a protection circuit.

By adopting the technical scheme, the device can be prevented from being damaged due to the fact that abnormal injection enters through the interface unit.

The invention is further configured to: the protection circuit adopts a parallel voltage protection type device to combine with a series current protection type device and a parallel power protection device to realize three-level protection.

By adopting the technical scheme, the impact resistance of the interface can be improved, and the reliability of the interface is enhanced.

The invention is further configured to: the debugging unit is provided with an SOC program programming port, an SOC debugging port, an SOC network port, an FPGA program programming port and an FPGA debugging port.

By adopting the technical scheme, the debugging unit can conveniently develop and debug the program.

The invention not only is limited to an SOC architecture design method formed by integrating an ARM and a DSP in a chip, but also comprises an architecture design method for taking the ARM and the DSP as two separated processors.

The invention is not limited to the design method of SOC + FPGA architecture formed by ARM and DSP, and also comprises the design method of SOC + SPOC architecture formed by SOPC (system on programmable chip) constructed based on FPGA.

In conclusion, the invention has the following beneficial effects:

1. the system adopts the SOC combined with the FPGA, can fully integrate the advantages of various processors, not only can improve the real-time performance of the flight control system and the processing capacity of complex data and algorithms, but also can flexibly configure interfaces;

2. the system of the invention adopts an architecture of SOC combined with FPGA, ARM and DSP on an SOC unit have reliable inter-core communication mechanism, which is beneficial to improving software reliability, and sufficient protection measures are provided between a core device and an interface unit, thus enhancing the shock resistance of hardware and improving the reliability;

3. the system of the invention adopts an architecture combining SOC with FPGA, can construct a system on a programmable chip based on a soft core or a hard core processor in the FPGA to form an SOC + SOPC architecture, so that the flight control system can be used in occasions with higher complexity, and the expansion capability of the system is enhanced.

Drawings

Fig. 1 is a schematic diagram of a hardware system architecture of a flight control computer of SOC + FPGA in the embodiment of the present invention;

FIG. 2 is a schematic diagram of an FPGA unit design according to an embodiment of the present invention.

In the figure: 1. an SOC unit; 2. an FPGA unit; 3. an interface unit; 4. a storage unit; 5. a debugging unit; 6. an ARM core; 7. a DSP core; 8. a CAN port; 9. an SPI port; 10. an RS232 port; 11. RS422/RS285 port; 12. a DAC port; 13. an ADC port; 14. a PWM port; 15. a GPIO port; 16. NAND-FlashA; 17. NAND-FlashB; 18. NOR-FlashC; 19. synchronous dynamic random access memory SDRAM; 20. programming ports of the SOC program; 21. an SOC debugging port; 22. SOC network port; 23. programming a port of an FPGA program; 24. a PGA debugging port; 25. DSP L2 RAM; 26. an interrupt line; 27. an EMIF bus; 28. an SPI bus; 29. a DDR bus.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions of the present invention will be described in further detail below with reference to the embodiments of the present invention and the accompanying drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail with reference to examples.

The embodiment is as follows:

as shown in fig. 1 and 2, an SOC + FPGA flight control computer hardware system, as shown in fig. 1 and 2, includes an SOC unit 1, an FPGA unit 2, and an auxiliary circuit, where the auxiliary circuit includes an interface unit 3, a storage unit 4, and a debugging unit 5.

The SOC unit 1 is a dual-core heterogeneous processor, the core of the SOC unit 1 is an ARM core 6 and a DSP core 7, the ARM core 6 and the DSP core 7 are communicated with an interrupt line 26 through a DSP L2RAM25 of a shared memory, the ARM core 6 and the DSP core 7 can both access the shared memory, and after data in a memory space is read and written, the other side is notified in an interrupt mode, so that the data is processed in time.

The FPGA unit 2 is used for interface distribution and data transmission, and the FPGA unit 2 is configured to form an interface unit 3 through FPGA hardware logic programming and combining with an external interface protection chip. The FPGA unit 2 performs data transmission with the SOC unit 1 through the EMIF bus 27.

The interface unit 3 is used to meet the requirements of various equipment hitches.

The memory unit 4 is used for program and data storage, the memory unit 4 includes NAND-FlashA16, NAND-FlashB17, NOR-FlashC18 and synchronous dynamic random access memory SDRAM19, and the NOR-FlashC18 interacts with the SOC unit 1 through the SPI bus 28 for program storage. The SDRAM19 interacts with SOC unit 1 via DDR bus 29 to provide memory space for SOC unit 1. The NAND-FlashA16 and the NAND-FlashB17 interact with the SOC unit 1 through the EMIF bus 27 to perform mutual data backup and storage, prevent flight data loss and enhance hardware reliability.

The debugging unit 5 is used for program development debugging.

The SOC unit 1 sends a control instruction to the FPGA unit 2 through the EMIF bus 27, and controls the corresponding interface unit 3 to operate through the FPGA unit 2, thereby controlling the external device. When data are input into the interface unit 3, the FPGA unit 2 carries out preprocessing, sends an interrupt request to the SOC unit 1 after the data are input, and reads corresponding data according to the interrupt type after the SOC unit 1 receives the interrupt, so that interaction between flight control and external equipment is realized.

According to the scheme, on one hand, the complexity and the coupling of a program can be reduced, the software reliability is enhanced, the advantages of all processors are fully exerted, a control part is processed by an ARM (advanced RISC machine), complex operation is taken charge of by a DSP (digital signal processor), control and algorithm are separated and independent, the complexity and the coupling of the program can be effectively reduced, and the software reliability is improved. On the other hand, the CPU load can be reduced, and the real-time performance of the system can be enhanced; the ARM core 6 carries out task scheduling and management based on a real-time operating system, the DSP core 7 carries out algorithm real-time calculation, and the FPGA unit 2 carries out preprocessing on data from the interface unit 3, so that reasonable sharing of CPU load is realized, and the real-time performance of the system can be effectively improved. Moreover, the system can simplify the hardware design and reduce the power consumption of the system; through the SOC unit 1 framework of ARM inner core 6+ DSP inner core 7, can construct the dual-core minimum system with less auxiliary circuit, simplified hardware design, utilize FPGA unit 2 to carry out logic circuit modularized design, can improve development efficiency, also be favorable to improving system integration, reduce the consumption. In addition, the system can improve the flexibility and the expandability of the interface; the FPGA unit 2 completes tasks such as interface timing sequence, interface expansion and the like, modular thought development is adopted, each unit module is independent and communicates with a bus, the unit modules are not related to each other, and other modules of the system cannot be influenced by modifying a certain module, so that the flexibility and the expandability of the system can be enhanced.

In this embodiment, the interface unit 3 includes a plurality of channels of CAN ports 8, SPI ports 9, RS232 ports 10, RS422/485 ports, DAC ports 12, ADC ports 13, PWM ports 14, and GPIO ports 15, so that the interface types of the interface unit 3 are rich, and the interface unit is convenient for meeting the requirements of hanging various devices.

The interface unit 3 realizes physical isolation between the FPGA unit 2 and the interface unit 3 by combining an ESD protection interface chip with a protection circuit, and can prevent abnormal injection from entering through the interface unit 3 to damage devices.

The protection circuit adopts a parallel voltage protection type device to combine with a series current protection type device and a parallel power protection device to realize three-level protection, thereby improving the impact resistance of the interface and enhancing the reliability of the interface.

The debugging unit 5 comprises an SOC program programming port 20, an SOC debugging port 21, an SOC network port 22, an FPGA program programming port 23 and an FPGA debugging port 24, which is convenient for the debugging unit 5 to develop and debug the program.

The scheme of the invention is not limited to an SOC unit 1 architecture formed by engaging and integrating an ARM core 6 and a DSP in a chip, but also comprises a pseudo SOC unit 1 architecture formed by two separated processors, namely an ARM core 6 processor and a DSP core 7 processor.

In addition, the scheme of the invention is not limited to the SOC + FPGA architecture formed by the ARM core 6 and the DSP core 7, and also comprises an SOPC unit (system on a programmable chip) constructed based on the FPGA unit 2 to form the SOC + SPOC architecture.

In the above embodiment of the present invention, compared with a flight control hardware system with a conventional architecture, the flight control computer hardware system of the present invention has the following advantages:

(1) the control task and the complex algorithm are separately and independently developed, so that the complexity and the coupling of the program are reduced, and the portability and the reliability of the software are improved;

(2) the work of the CPU is reasonably distributed, the ARM is responsible for real-time control, the DSP is responsible for operation, and the FPGA performs data preprocessing, so that the burden of the CPU is reduced, and the real-time performance of the system is improved;

(3) based on SOC development formed by ARM and DSP, development of an interaction circuit between double cores is avoided, software and hardware design is simplified, hardware logic circuit development is carried out based on FPGA, various interface protection measures are designed, system integration level is improved, system power consumption is reduced, and hardware interface reliability is enhanced;

(4) the FPGA with rich interfaces and flexible configuration is used for modular interface design, various interface configuration programs can be written into the FPGA in advance, welding selection resistors are designed, different configurations of the interfaces are realized by welding selection resistors, and the functional diversity and the configuration flexibility of the interfaces are improved.

(5) The embedded software system can be connected with a large-capacity program and a large-capacity data storage chip in a hanging mode, and the embedded software system is convenient to transplant and store data in a long-term flight mode.

The working principle is as follows: the system of the invention adopts the structure of SOC combined with FPGA, fully integrates the advantages of various processors, not only improves the real-time performance of the flight control system, the processing capacity of complex data and algorithm, but also can flexibly configure the interface; the ARM and the DSP on the SOC unit 1 have a reliable inter-core communication mechanism, so that the software reliability is improved, sufficient protection measures are provided between a core device and the interface unit 3, the impact resistance of hardware can be enhanced, and the reliability is improved; the SOC unit 1 is combined with the FPGA unit 2, the system on the programmable chip can be constructed based on a soft core or hard core processor in the FPGA, and an SOC + SOPC framework is formed, so that the flight control system can be used in occasions with higher complexity, and the expansion capability of the system is enhanced.

The present embodiment is only for explaining the present invention, and it is not limited to the present invention, and those skilled in the art can make modifications of the present embodiment without inventive contribution as needed after reading the present specification, but all of them are protected by patent law within the scope of the claims of the present invention.

Claims

1. A flight control computer hardware system of SOC + FPGA is characterized in that: the system comprises an SOC unit (1), an FPGA unit (2) and an auxiliary circuit, wherein the auxiliary circuit comprises an interface unit (3), a storage unit (4) and a debugging unit (5);

the SOC unit (1) is a dual-core heterogeneous processor, the inner core of the SOC unit (1) is an ARM inner core (6) and a DSP inner core (7), the ARM inner core (6) and the DSP inner core (7) are communicated with an interrupt wire (26) through a DSP L2RAM (25) of a shared memory, the ARM inner core (6) and the DSP inner core (7) can both access the shared memory, and after data in a memory space is read and written, the other side is notified in an interrupt mode to realize timely processing of the data;

the FPGA unit (2) is used for interface distribution and data transmission, and the FPGA unit (2) is configured to form an interface unit (3) through FPGA hardware logic programming and combining with an external interface protection chip; the FPGA unit (2) is in data transmission with the SOC unit (1) through an EMIF bus (27);

the interface unit (3) is used for meeting the hanging connection of various devices;

the memory unit (4) is used for program and data storage, the memory unit (4) comprises a NAND-FlashA (16), a NAND-FlashB (17), a NOR-FlashC (18) and a synchronous dynamic random access memory SDRAM (19), the NOR-FlashC (18) interacts with the SOC unit (1) through an SPI bus (28) for program storage; the synchronous dynamic random access memory SDRAM (19) interacts with the SOC unit (1) through a DDR bus (29) to provide a memory space for the SOC unit (1); the NAND-FlashA (16) and the NAND-FlashB (17) interact with the SOC unit (1) through an EMIF bus (27) to perform mutual backup storage of data;

the debugging unit (5) is used for program development and debugging;

the SOC unit (1) sends a control instruction to the FPGA unit (2) through an EMIF bus (27), and the FPGA unit (2) controls the corresponding interface unit (3) to work so as to realize the control of external equipment; when data are input into the interface unit (3), the interface unit is preprocessed by the FPGA unit (2), an interrupt request is sent to the SOC unit (1) after the processing is finished, and after the SOC unit (1) receives the interrupt, corresponding data are read according to the interrupt type, so that interaction between the flight control and external equipment is realized.

2. The flight control computer hardware system of SOC + FPGA of claim 1, wherein: the interface unit (3) comprises a plurality of channels of CAN ports (8), SPI ports (9), RS232 ports (10), RS422/485 ports, DAC ports (12), ADC ports (13), PWM ports (14) and GPIO ports (15).

3. The flight control computer hardware system of SOC + FPGA of claim 1, wherein: the interface unit (3) realizes physical isolation between the FPGA unit (2) and the interface unit (3) by combining an ESD protection interface chip with a protection circuit.

4. The flight control computer hardware system of SOC + FPGA of claim 3, wherein: the protection circuit adopts a parallel voltage protection type device to combine with a series current protection type device and a parallel power protection device to realize three-level protection.

5. The flight control computer hardware system of SOC + FPGA of claim 1, wherein: the debugging unit (5) is provided with an SOC program programming port (20), an SOC debugging port (21), an SOC network port (22), an FPGA program programming port (23) and an FPGA debugging port (24).