CN115168114A - A Spaceborne Integrated Integrated Electronic System Based on COTS Devices - Google Patents

Abstract

The embodiment of the invention discloses a satellite-borne integrated electronic system based on a COTS device, which comprises: the system comprises a core processing board card, a communication control board card, a signal acquisition board card and an external function board card which are respectively connected with a back board in a bidirectional mode; the core processing board card is used for carrying out system data operation and sending a control instruction to the external function board card through the backboard; the communication control board card is used for realizing signal communication with an external load and an external function board card, transmitting communication data to the core processing board card through the backboard, and finishing output of an OC instruction according to a control instruction of the core processing board card; the signal acquisition board card is used for acquiring external load and analog quantity data of the external function board card and sending the data to the core processing board card through the backboard; the external function board card is used for receiving and executing a control instruction sent by the core processing board or sending a control signal to an external load through interface conversion; and the measurement data returned by the external load is transmitted back to the core processing board card.

Description

A Spaceborne Integrated Integrated Electronic System Based on COTS Devices

technical field

The invention relates to the field of electronic systems, in particular to a space-borne integrated integrated electronic system based on COTS devices.

Background technique

With the continuous development and innovation of aerospace technology, new space application modes such as satellite cluster operations and inter-satellite networking make the integration of aerospace electronic systems become the development direction of aerospace product applications. In order to meet the needs of future applications, the satellite onboard computer plans to use the commercial off-the-shelf (COTS) and relatively mature development tools in the industrial field and the high-reliability development experience of aerospace to combine the whole satellite affairs management, attitude and orbit control, telemetry and remote control, and digital baseband processing. , unlocker drive and digital power distribution management and other functions are integrated in the single board computer. This design idea and method can greatly improve product performance and integration, reduce product volume, power consumption, reduce development costs, and shorten development cycles, which has become a future development trend.

In view of the low-cost and high-reliability requirements of spaceborne satellites, this patent rationally sorts out information flow and system architecture design through an optimized architecture scheme, divides software and hardware functions in a balanced manner, and improves system implementation efficiency; through the reuse of control, calculation, and processing hardware Or integration, the level and partition design of software, reduce the scale of hardware implementation and the difficulty of software implementation. Carry out integrated, low-cost and high-reliability design of products through new technologies such as breakthroughs in integrated integrated electronic system architecture design, low-cost integrated electronic system COTS device application technology, and system architecture multi-level redundancy reliability design and evaluation technology; Achieve low cost, high reliability and high integration of constellation satellite electronic systems.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a space-borne integrated integrated electronic system based on COTS devices, which solves at least one of the defects of the prior art.

To this end, one aspect of the present invention provides a space-borne integrated electronic system based on COTS devices, comprising:

The core processing board, the communication control board, the signal acquisition board and the external function board which are bidirectionally connected to the backplane respectively,

in,

The core processing board is used to receive the measurement data returned by the external load and analyze the operation, store the system operation data, and send the effective operation result and control instruction to the external function board through the backplane;

The communication control board is used to realize signal communication between the core processing board and external loads and external function boards, send the received communication data to the core processing board through the backplane, and complete the core processing The output of the board OC command;

The signal acquisition board is used to collect the analog data of the external load and the external function board and send the data to the core processing board through the backplane;

The external function board is used for receiving and executing control instructions sent by the core processing board, or sending control signals to an external load through interface conversion; and returning the measurement data returned by the external load to the core processing board.

Optionally, the core processing board includes an arithmetic unit and a voting unit;

in,

The arithmetic unit is composed of N processors, where N≧3, and the processors are connected through a processor bus.

Optionally, the operation unit adopts a three-modular redundancy design, including,

The first hot-standby processor, the second hot-standby processor and the third hot-standby processor are configured to respectively receive the measurement data returned by the external load and perform arithmetic processing at the same time;

The computing unit further includes a first cold-standby processor and a second cold-standby processor, which are replaced when the hot-standby processor is faulty, so as to keep the three-machine hot-standby running state.

Optionally, the voting unit is composed of an anti-fuse FPGA chip,

Each processor of the arithmetic unit opens up 3 registers to store the three-machine processing data, respectively reads the three-machine processing data from the respective corresponding registers, conducts three-out-two voting, completes the first-level voting and broadcasts the voting results to all. The anti-fuse FPGA chip of the voting unit;

The anti-fuse FPGA chip performs secondary voting according to the voting result, and after the voting is unanimous, it is determined that the computing unit is on the flight and outputs a valid computing result.

Optionally, the operation unit utilizes the navigation second pulse of the external navigation module and the anti-fuse FPGA chip to perform time synchronization, so that the task cycles of the N processors are consistent.

Optionally, the operation unit utilizes the second pulse of the external navigation module and the anti-fuse FPGA chip to perform time synchronization, including:

The N processors use the external navigation module second pulse to perform 1s time synchronization, and after the processor receives the external navigation module second pulse, the second pulse terminal synchronizes the local time to complete the first-level synchronization;

The N processors use the 50ms time slice of the anti-fuse FPGA chip's own crystal oscillator to perform secondary synchronization.

Optionally, the external function board includes a measurement and control baseband board, a measurement and control radio frequency board, and a motor drive and magnetic assembly circuit board,

in,

The measurement and control baseband board and the measurement and control radio frequency board are used to complete the transmission and reception of measurement and control signals and data exchange between the integrated electronic system and the ground measurement and control station; when the satellite is within the measurement and control arc of the ground measurement and control station, it cooperates with the ground measurement and control station, Complete telemetry, remote control, distance measurement and speed measurement functions;

The motor drive and magnetic assembly circuit board is used to realize the drive control function of the SADA, the magnet bar drive control function and the too-sensitive photocurrent signal processing function.

Optionally, the external function board also includes,

Primary power distribution board, secondary power conversion and power distribution board;

The primary power distribution board card is used to receive the OC command output by the communication control board, control the power distribution switch on the primary power distribution board card to turn on and off, and realize the power-on and power-off control of the primary power output of each channel.

The secondary power conversion and power distribution board card is used to realize the voltage conversion from the primary power supply to the secondary power supply, and to receive the OC command output by the communication control board to control the on-off of the power distribution switch on the secondary power distribution board to realize Power-on and power-off control for each secondary power output.

Optionally, the backplane is connected to the core processing board, the communication control board, the signal acquisition board and the external function board through an SPI bus.

Optionally, the components of the integrated electronic system are all COTS devices.

The beneficial effects of the present invention are as follows:

The solution provided by the invention integrates the information processing part of the external load into the system, and the data processing is completed by the software and hardware of the integrated electronic system, which realizes the simplification of the hardware system, improves the integration degree of the integrated electronic system as a whole, and reduces the weight and volume. Reduce the power consumption of the whole machine.

Description of drawings

The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

FIG. 1 shows a block diagram of an integrated electronic system provided by an embodiment of the present invention.

FIG. 2 shows a schematic diagram of communication connection of each module of an integrated electronic system provided by an embodiment of the present invention.

FIG. 3 shows a schematic diagram of a three-machine arbitration voting mechanism of an integrated electronic system provided by an embodiment of the present invention.

FIG. 4 shows a schematic diagram of multiprocessor time synchronization provided by an embodiment of the present invention.

FIG. 5 shows a schematic diagram of a communication connection between an integrated electronic system and an external load provided by an embodiment of the present invention.

Detailed ways

In order to illustrate the present invention more clearly, the present invention will be further described below with reference to the embodiments and accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. Those skilled in the art should understand that the content specifically described below is illustrative rather than restrictive, and should not limit the protection scope of the present invention.

An embodiment of the present invention provides a space-borne integrated integrated electronic system based on COTS devices. The integrated electronic system is composed of eight printed circuit boards. The boards are a group and are connected to the backplane through connectors. The two groups of boards are connected to both sides of the backplane respectively to realize power supply and signal transmission on the backplane. The installation form is shown in Figure 1, including:

The core processing board, the communication control board, the signal acquisition board and the external function board which are bidirectionally connected to the backplane respectively,

in,

The core processing board is used to receive the measurement data returned by the external load and analyze the operation, store the system operation data, and send the valid operation result and the OC command to the external function board through the backplane;

The communication control board is used to realize signal communication between the core processing board and external loads and external function boards, send the received communication data to the core processing board through the backplane, and complete the core processing The output of the board OC command;

The signal acquisition board is used to collect the analog data of the external load and the external function board and send the data to the core processing board through the backplane;

The external function board is used for receiving and executing the OC instruction sent by the core processing board, or sending the OC instruction to the external load through interface conversion; and returning the measurement data returned by the external load to the core processing board.

This solution integrates the core processing board, communication control board, signal acquisition board and external function board to simplify the hardware system, improve the integration of the integrated electronic system as a whole, reduce the weight and volume, and reduce the Overall power consumption.

In a specific embodiment, the components of the integrated electronic system are all COTS devices.

It should be understood that low-cost and high-reliability electronic systems for low-orbit constellations use more commercially mature COTS devices to improve their work performance and reduce development costs. Facing the special space environment requirements in the aerospace field, it is necessary to meet the functional performance index requirements. On the basis of , it should also meet the requirements of environmental adaptability and on-orbit reliability. Because COTS devices generally do not use anti-irradiation technology and the internal cell library of the device does not adopt reinforcement design, they usually do not have anti-irradiation indicators, and the ability to resist total dose and single event effect is very weak. Failure will affect its normal operation. On-orbit missions run.

Therefore, it is very necessary to design and evaluate multi-level redundancy for low-cost COTS devices. The reliability requirements are met through the multi-level redundancy design at the device level, module level and whole machine level.

In a possible implementation manner, as shown in FIG. 2 , the core processing board includes an arithmetic unit and a voting unit;

in,

The arithmetic unit is composed of N processors, where N≧3, and the processors are connected through a processor bus.

The processor adopts a three-mode redundancy design, adopts a three-machine hot backup + two-machine cold backup architecture design, and selects a high-performance and low-cost ARM processor, specifically, including,

a first hot-standby processor, a second hot-standby processor, and a third hot-standby processor,

The processors respectively receive the measurement data and perform arithmetic processing at the same time;

It also includes that the first cold standby processor and the second cold standby processor are replaced when the hot standby processor fails, so as to maintain the running state of the three-machine hot standby.

In a specific embodiment, the voting unit is composed of an anti-fuse FPGA chip,

Each processor of the arithmetic unit opens up 3 registers to store the three-machine processing data, respectively reads the three-machine processing data from the respective corresponding registers, conducts three-out-two voting, completes the first-level voting and broadcasts the voting results to all. The anti-fuse FPGA chip of the voting unit;

The anti-fuse FPGA chip performs two-level voting according to the voting result. After the voting is unanimous, it is determined that the operation unit is on the flight and outputs a valid operation result. The valid operation result includes a control state, and outputs the control state to the communication control. The FPGA unit of the module is used to realize the control output of the external communication control module and the signal acquisition instruction module. Determine the flight status of the processor unit and switch the faulty computing unit in time through the power supply module, so as to ensure the normal operation of the core processing module.

In a possible implementation manner, as shown in FIG. 3 , which is a diagram of a three-machine arbitration and voting mechanism of the integrated electronic system, the anti-fuse FPGA chip includes a first voter 201 , a second voter 202 and a first voter 202 . Three voter 203, the operation unit includes a first ARM unit 101, a second ARM unit 102 and a third ARM unit 103, and the three ARM units compare the operation results of the local machine with the operation results of the other two machines through their respective registers And output the consistent result to the three voters; the three voters receive the comparison results of the three ARM units for a second vote, and determine which ARM unit is the flight based on the voting results, and the flight will conduct external Output control of signals or commands.

The three-mode redundant processor performs data exchange through the SPI bus to realize data sharing and comparison. The three-mode redundant ARM unit realizes data interaction through the interactive register, and the ARM unit realizes the three-mode redundancy of data interaction by writing the interactive register of the three machines and reading the data of its corresponding interactive register.

The interaction of the voting rights of the ARM processors in this embodiment can prevent the conflict of voting rights caused by the failure of one of the three ARM units.

In a specific embodiment, the processor uses the second pulse of the external navigation module and the anti-fuse FPGA to perform time synchronization, so that the task cycles of the N processors are consistent.

In a specific embodiment, the time synchronization performed by the processor using the navigation second pulse of the external navigation module and the anti-fuse FPGA includes:

The processor uses the external navigation module second pulse to perform 1s time synchronization, and after the processor receives the pulse, the second pulse terminal synchronizes the local time to complete the first-level synchronization;

Second-level synchronization is performed using the 50ms time slice of the anti-fuse FPGA's own crystal oscillator.

The following is an explanation of time synchronization by taking a three-mode redundant processor as an example: As shown in Figure 4, the three-mode redundant processor adopts a two-level synchronization design, and the first-level synchronization uses an external navigation for the three-mode redundant processor. The module second pulse performs 1s time synchronization. After the processor receives the pulse, the second pulse is interrupted to synchronize the local time, so that the start and end times of the three processor cycle tasks are consistent, and the task synchronization of the three-mode redundant processor is guaranteed; the secondary synchronization is 50ms time slice synchronization, the synchronization pulse is generated by the anti-fuse FPGA using its own crystal oscillator every 50ms, and the three processors recognize the pulse for time slice synchronization, that is, the external interrupt source is used as the trigger point for system synchronization. The two machines recognize each other's interrupt status and enter the interrupt service routine unanimously. The interrupt service routine mainly exchanges status and data, so that the time reference of the three processor modules is finally synchronized to ensure the data synchronization of the three-mode redundant processors.

In a specific embodiment, the communication control board selects FLASH-type FPGA to complete the interface processing function. This type of FPGA is not sensitive to single event effects, and a dual-machine cold-standby FPGA system is designed to realize the faulty FPGA through a watchdog circuit. reset and machine cutting operations. The memory uses MRAM, which is not sensitive to single-event effects, does not cause single-event locking, and is not prone to single-event flipping. NOR FLASH and NAND FLASH are used to store programs and data, and the program and data are stored in three-modular redundant storage, and the program and data are read and compared to ensure the correctness of the program and data. Each driver or acquisition chip in the driver layer, such as CAN chip, 422 chip, OC chip, AD chip, etc., adopts redundant backup design to ensure the high reliability of the interface.

In a specific embodiment, the external function board includes a measurement and control baseband board, a measurement and control radio frequency board, and a motor drive and magnetic assembly circuit board,

in,

The motor drive and magnetic assembly circuit board is used to realize the drive control function of SADA (solar wing drive mechanism, Solar Array Drive Assembly), the magnet bar drive control function and the too-sensitive photocurrent signal processing function;

The measurement and control baseband board and the measurement and control radio frequency board are used to complete the transmission and reception of measurement and control signals and data exchange between the integrated electronic system and the ground measurement and control station; when the satellite is within the measurement and control arc of the ground measurement and control station, it cooperates with the ground measurement and control station, Complete telemetry, remote control, distance measurement and speed measurement functions;

In a specific embodiment, the external function board further includes:

Primary power distribution board, secondary power conversion and power distribution board;

The primary power distribution board card is used to receive the OC command output by the communication control board, control the power distribution switch on the primary power distribution board card to turn on and off, and realize the power-on and power-off control of the primary power output of each channel.

The secondary power conversion and power distribution board card is used to realize the voltage conversion from the primary power supply to the secondary power supply, and to receive the OC command output by the communication control board to control the on-off of the power distribution switch on the secondary power distribution board to realize Power-on and power-off control for each secondary power output.

In a specific embodiment, the backplane is connected to the core processing board, the communication control board and the external function board through an SPI bus.

In a specific embodiment, as shown in FIG. 5 , each control board of the integrated electronic system is connected to an external load through an interface. Star sensitive probe 2, too sensitive probe A, too sensitive probe B, primary electrical equipment, secondary electrical equipment, S/X radio frequency antenna and GNSS antenna, etc. The external function board converts and receives the control instructions of the core processing board through the interface of the communication control board and sends it to the corresponding external load to control its operation, and passes the measurement data received by the external load through the communication control board. The interface is converted back to the core processing board.

It should be noted that, in the description of the present invention, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these entities or that there is any such actual relationship or sequence between operations. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Obviously, the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, rather than limiting the embodiments of the present invention. Changes or changes in other different forms cannot be exhausted here, and all obvious changes or changes derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims (10)

1. a space-borne integrated electronic system based on COTS device, is characterized in that, comprises: The core processing board, the communication control board, the signal acquisition board and the external function board which are bidirectionally connected to the backplane respectively, in, The core processing board is used to receive the measurement data returned by the external load and analyze the operation, store the system operation data, and send the effective operation result and control instruction to the external function board through the backplane; The communication control board is used to realize signal communication between the core processing board and external loads and external function boards, send the received communication data to the core processing board through the backplane, and complete the core processing The output of the board OC command; The signal acquisition board is used to collect the analog data of the external load and the external function board and send the data to the core processing board through the backplane; The external function board is used for receiving and executing control instructions sent by the core processing board, or sending control signals to an external load through interface conversion; and returning the measurement data returned by the external load to the core processing board. 2. The integrated electronic system according to claim 1, characterized in that, The core processing board includes an arithmetic unit and a voting unit; in, The arithmetic unit is composed of N processors, where N≧3, and the processors are connected through a processor bus. 3. The integrated electronic system according to claim 2, characterized in that, The arithmetic unit adopts a three-modular redundant design, including, The first hot-standby processor, the second hot-standby processor and the third hot-standby processor are configured to respectively receive the measurement data returned by the external load and perform arithmetic processing at the same time; The computing unit further includes a first cold-standby processor and a second cold-standby processor, which are replaced when the hot-standby processor is faulty, so as to keep the three-machine hot-standby running state. 4. The integrated electronic system according to claim 3, characterized in that, The voting unit is composed of an anti-fuse FPGA chip, Each processor of the arithmetic unit opens up 3 registers to store the three-machine processing data, respectively reads the three-machine processing data from the respective corresponding registers, conducts three-out-two voting, completes the first-level voting and broadcasts the voting results to all. The anti-fuse FPGA chip of the voting unit; The anti-fuse FPGA chip performs secondary voting according to the voting result, and after the voting is unanimous, it is determined that the computing unit is on the flight and outputs a valid computing result. 5. The integrated electronic system according to claim 3, characterized in that, The operation unit uses the navigation second pulse of the external navigation module and the anti-fuse FPGA chip to perform time synchronization, so that the task cycles of the N processors are consistent. 6. The integrated electronic system according to claim 5, characterized in that, The operation unit utilizes the second pulse of the external navigation module and the anti-fuse FPGA chip to perform time synchronization, including: The N processors use the external navigation module second pulse to perform 1s time synchronization, and after the processor receives the external navigation module second pulse, the second pulse terminal synchronizes the local time to complete the first-level synchronization; The N processors use the 50ms time slice of the anti-fuse FPGA chip's own crystal oscillator to perform secondary synchronization. 7. The integrated electronic system according to claim 1, wherein, The external function board includes a measurement and control baseband board, a measurement and control radio frequency board, and a motor drive and magnetic assembly circuit board, in, The measurement and control baseband board and the measurement and control radio frequency board are used to complete the transmission and reception of measurement and control signals and data exchange between the integrated electronic system and the ground measurement and control station; when the satellite is within the measurement and control arc of the ground measurement and control station, it cooperates with the ground measurement and control station, Complete telemetry, remote control, distance measurement and speed measurement functions; The motor drive and magnetic assembly circuit board is used to realize the drive control function of the SADA, the magnet bar drive control function and the too-sensitive photocurrent signal processing function. 8. The integrated electronic system according to claim 7, characterized in that, The external function board also includes, Primary power distribution board, secondary power conversion and power distribution board; The primary power distribution board card is used to receive the OC command output by the communication control board, control the on-off of the power distribution switch on the primary power distribution board card, and realize the power-on and power-off control of the primary power output of each channel; The secondary power conversion and power distribution board card is used to realize the voltage conversion from the primary power supply to the secondary power supply, and to receive the OC command output by the communication control board to control the on-off of the power distribution switch on the secondary power distribution board to realize Power-on and power-off control for each secondary power output. 9. The integrated electronic system according to claim 7, characterized in that, The backplane is connected with the core processing board, the communication control board, the signal acquisition board and the external function board through the SPI bus. 10. The integrated electronic system according to claim 7, wherein, The components of the integrated electronic system are all COTS devices.

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