CN115168114A - Satellite-borne integrated electronic system based on COTS device - Google Patents
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Abstract
The embodiment of the invention discloses a satellite-borne integrated electronic system based on a COTS device, which comprises: the system comprises a core processing board card, a communication control board card, a signal acquisition board card and an external function board card which are respectively connected with a back board in a bidirectional mode; the core processing board card is used for carrying out system data operation and sending a control instruction to the external function board card through the backboard; the communication control board card is used for realizing signal communication with an external load and an external function board card, transmitting communication data to the core processing board card through the backboard, and finishing output of an OC instruction according to a control instruction of the core processing board card; the signal acquisition board card is used for acquiring external load and analog quantity data of the external function board card and sending the data to the core processing board card through the backboard; the external function board card is used for receiving and executing a control instruction sent by the core processing board or sending a control signal to an external load through interface conversion; and the measurement data returned by the external load is transmitted back to the core processing board card.
Description
Technical Field
The invention relates to the field of electronic systems, in particular to a satellite-borne integrated comprehensive electronic system based on a COTS device.
Background
With the continuous development and innovation of aerospace technology, the aerospace electronic system is made to be integrated into the development direction of aerospace product application in brand new space application modes such as satellite cluster operation and inter-satellite networking. In order to meet the future application requirements, the satellite onboard computer is supposed to combine commercial current of goods (COTS) in the industrial field and relatively mature development tools with the aerospace high-reliability development experience, and the functions of whole satellite housekeeping, attitude and orbit control, remote measurement and control, data transmission baseband processing, unlocking device driving, digital power distribution management and the like are integrated on a single board computer to be realized. The design idea and the method can greatly improve the product performance and the integration level, reduce the product volume and the power consumption, reduce the development cost and shorten the development period, and become a future development trend.
Aiming at the requirements of low cost and high reliability of a satellite-borne satellite, the software and hardware functions are divided in a balanced manner through an optimized system structure scheme to reasonably comb information streams and design a system framework, and the system implementation efficiency is improved; the hardware realization scale and the software realization difficulty are reduced through multiplexing or integration of control, calculation and processing hardware and the software hierarchy and partition design. The integration, low-cost and high-reliability design of products is developed by breaking through new technologies such as an integrated electronic system architecture design, a low-cost integrated electronic system COTS device application technology, a system architecture multilevel redundancy reliability design and evaluation technology and the like by means of attack and customs; finally, the low cost, high reliability and high integration of the constellation satellite electronic system are realized.
Disclosure of Invention
The invention aims to provide a satellite-borne integrated electronic system based on a COTS device, which solves at least one of the defects of the prior art.
Therefore, the invention provides a satellite-borne integrated electronic system based on COTS devices, which comprises:
a core processing board card, a communication control board card, a signal acquisition board card and an external function board card which are respectively connected with the backboard in a bidirectional way,
wherein,
the core processing board card is used for receiving the measurement data returned by the external load, analyzing and operating the measurement data, storing system operation data, and sending effective operation results and control instructions to the external function board card through the backboard;
the communication control board card is used for realizing signal communication between the core processing board card and an external load and an external function board card, sending received communication data to the core processing board card through the backboard, and finishing the output of an OC instruction of the core processing board card;
the signal acquisition board card is used for acquiring external load and analog quantity data of the external function board card and sending the data to the core processing board card through the backboard;
the external function board card is used for receiving and executing a control instruction sent by the core processing board or sending a control signal to an external load through interface conversion; and transmitting the measurement data returned by the external load back to the core processing board card.
Optionally, the core processing board includes an arithmetic unit and a voting unit;
wherein,
the arithmetic unit consists of N processors, wherein N is more than or equal to 3, and the processors are connected through a processor bus.
Optionally, the arithmetic unit adopts a triple modular redundancy design, including,
the first hot standby processor, the second hot standby processor and the third hot standby processor are respectively arranged for receiving the measurement data returned by the external load and simultaneously performing operation processing;
the arithmetic unit also comprises a first cold standby processor and a second cold standby processor, and when the hot standby processor fails, the first cold standby processor and the second cold standby processor are replaced so as to keep the running state of the three machines in hot standby.
Optionally, the voting unit is composed of an antifuse FPGA chip,
each processor of the operation unit opens up 3 registers to store three-machine processing data, reads the three-machine processing data from the corresponding register respectively, carries out two-out-of-three voting, completes one-level voting and broadcasts the voting result to the antifuse FPGA chip of the voting unit;
and the anti-fuse FPGA chip carries out secondary voting according to the voting result, determines the operation unit to operate on the line after voting is consistent, and outputs an effective operation result.
Optionally, the operation unit performs time synchronization by using a navigation second pulse of an external navigation module and an antifuse FPGA chip to make task cycles of the N processors consistent.
Optionally, the time synchronization performed by the arithmetic unit using the pulse per second of the external navigation module and the antifuse FPGA chip includes:
the N processors utilize the second pulse of the external navigation module to carry out 1s time synchronization, and the processors carry out second pulse terminal synchronization local time after receiving the second pulse of the external navigation module to complete primary synchronization;
and the N processors carry out secondary synchronization by utilizing a 50ms time slice of the crystal oscillator of the antifuse FPGA chip.
Optionally, the external function board includes a measurement and control baseband board, a measurement and control radio frequency board, and a motor drive and magnetic component circuit board,
wherein,
the measurement and control baseband board card and the measurement and control radio frequency board card are used for completing measurement and control signal receiving and transmitting and data interaction between the integrated electronic system and the ground measurement and control station; when the satellite is in the measurement and control arc section of the ground measurement and control station, the satellite is matched with the ground measurement and control station to complete the functions of remote measurement, remote control, distance measurement and speed measurement;
the motor drive and magnetic component circuit board is used for realizing the SADA drive control function, the magnetic bar drive control function and the function of processing an ultra-sensitive photocurrent signal.
Optionally, the external functional board card further includes,
the power supply comprises a primary power distribution board card, a secondary power supply conversion and power distribution board card;
the primary power distribution board card is used for receiving OC instructions output by the communication control board, controlling the on-off of a power distribution switch on the primary power distribution board card and realizing the power on-off control of each path of primary power output.
The secondary power supply conversion and distribution board card is used for realizing voltage conversion from a primary power supply to a secondary power supply, receiving an OC instruction output by the communication control board, controlling the on-off of a distribution switch on the secondary distribution board card and realizing the on-off control of each secondary power supply output.
Optionally, the backplane is connected to the core processing board, the communication control board, the signal acquisition board and the external function board through an SPI bus.
Optionally, all the components of the integrated electronic system are COTS devices.
The invention has the following beneficial effects:
the scheme provided by the invention integrates the information processing part of the external load into the system, and the data processing is uniformly completed by software and hardware of the integrated electronic system, so that the simplification of the hardware system is realized, the integration level of the integrated electronic system is integrally improved, the weight and the volume are reduced, and the power consumption of the whole computer is reduced.
Drawings
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
Fig. 1 is a block diagram illustrating components of an integrated electronic system provided by an embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating communication connections among modules of an integrated electronic system according to an embodiment of the present invention.
Fig. 3 is a schematic diagram illustrating a three-machine arbitration voting mechanism of an integrated electronic system according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating multiprocessor time synchronization provided by an embodiment of the present invention.
Fig. 5 is a schematic diagram illustrating a communication connection between an integrated electronic system and an external load according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the present invention, the present invention will be further described with reference to the following examples and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
One embodiment of the present invention provides a satellite-borne integrated electronic system based on COTS devices, where the integrated electronic system is composed of eight printed circuit boards, the printed circuit boards are in a standard 6U size (160 mm × 233 mm), four board cards are in a group, and are connected to a backplane through connectors, the two board cards are respectively connected to two sides of the backplane, and implement power supply and signal transmission on the backplane, and the installation form is as shown in fig. 1, and includes:
a core processing board card, a communication control board card, a signal acquisition board card and an external function board card which are respectively connected with the backboard in a bidirectional way,
wherein,
the core processing board card is used for receiving the measurement data returned by the external load, analyzing and operating the measurement data, storing system operation data, and sending an effective operation result and an OC instruction to the external function board card through the backboard;
the communication control board card is used for realizing signal communication between the core processing board card and an external load and an external function board card, sending received communication data to the core processing board card through the backboard, and finishing the output of an OC instruction of the core processing board card;
the signal acquisition board card is used for acquiring external loads and analog quantity data of the external function board card and sending the data to the core processing board card through the backboard;
the external function board card is used for receiving and executing the OC instruction sent by the core processing board or sending the OC instruction to an external load through interface conversion; and transmitting the measurement data returned by the external load back to the core processing board card.
According to the scheme, the core processing board card, the communication control board card, the signal acquisition board card and the external function board card are integrated together, so that a hardware system is simplified, the integration level of a comprehensive electronic system is integrally improved, the weight and the volume are reduced, and the power consumption of the whole system is reduced.
In a specific embodiment, the components of the integrated electronic system are COTS devices.
It should be understood that the low-cost and high-reliability electronic system facing the low-orbit constellation adopts more commercially mature COTS devices to improve the working performance and reduce the development cost, and the requirements of environmental adaptability and on-orbit reliability should be met on the basis of meeting the requirements of functional performance indexes in the special space environment requirement of the aerospace field. Because the COTS device does not generally adopt an anti-radiation process, and a cell library in the device does not adopt a reinforcement design, the COTS device generally has no anti-radiation index, has weak capability of resisting total dose and single event effect, and can influence the normal on-orbit task operation when a fault occurs.
Therefore, it is very necessary to design and evaluate the multi-level redundancy for low-cost COTS devices. The requirement of reliability is met through the multi-level redundancy design of a device level, a module level and a complete machine level.
In a possible implementation manner, as shown in fig. 2, the core processing board includes an arithmetic unit and a voting unit;
wherein,
the arithmetic unit consists of N processors, wherein N is more than or equal to 3, and the processors are connected through a processor bus.
The processor adopts a triple modular redundancy design, adopts a three-machine hot standby and two-machine cold standby architecture design, selects an ARM processor with high performance and low cost, and concretely comprises,
a first hot standby processor, a second hot standby processor and a third hot standby processor,
the processor respectively receives the measurement data and simultaneously performs operation processing;
the system also comprises a first cold standby processor and a second cold standby processor, wherein when the hot standby processor fails, the first cold standby processor and the second cold standby processor are replaced so as to keep the running state of the three-machine hot standby.
In a specific embodiment, the voting unit consists of an antifuse FPGA chip,
each processor of the operation unit opens up 3 registers to store three-machine processing data, reads the three-machine processing data from the corresponding register respectively, carries out two-out-of-three voting, completes one-level voting and broadcasts the voting result to the antifuse FPGA chip of the voting unit;
the anti-fuse FPGA chip carries out secondary voting according to the voting result, determines that the operation unit works as an office machine and outputs an effective operation result after voting is consistent, the effective operation result comprises a control state, the control state is output to the FPGA unit of the communication control module so as to realize control output of the external communication control module and the signal acquisition instruction module, the secondary voting is to vote the data comparison results of the three processor units again through the anti-fuse FPGA voter so as to determine the working state of the processor unit and timely switch the failed operation unit through the power supply module, and therefore normal operation of the core processing module is guaranteed.
In a possible implementation manner, as shown in fig. 3, the diagram of the three-machine arbitration voting mechanism of the integrated electronic system is shown, the antifuse FPGA chip includes a first voter 201, a second voter 202, and a third voter 203, the operation unit includes a first ARM unit 101, a second ARM unit 102, and a third ARM unit 103, and the three ARM units compare the operation result of the local machine with the operation results of the other two machines through respective registers and output the result of whether the operation result is consistent to the three voters; and the three voters receive the comparison results of the three ARM units to carry out secondary voting, determine which ARM unit is the current airliner according to the voting results, and control the output of external signals or instructions by the current airliner.
The triple modular redundancy processor carries out data interaction through the SPI bus to realize data sharing and comparison. The triple modular redundancy ARM unit realizes data interaction through the interaction register, and the ARM unit realizes triple modular redundancy of data interaction through writing the interaction register of the triple machine and reading the data of the interaction register corresponding to the ARM unit.
In this embodiment, the voting right interaction of the ARM processor can prevent the voting right conflict problem caused by a failure in one of the three ARM units.
In a specific embodiment, the processors are time synchronized by using a pulse per second of an external navigation module and an antifuse FPGA to make task cycles of the N processors consistent.
In a specific embodiment, the time synchronization of the processor with the navigation second pulse of the external navigation module and the antifuse FPGA comprises:
the processor uses an external navigation module pulse per second to carry out 1s time synchronization, and after receiving the pulse, the processor carries out pulse per second terminal synchronization on local time to complete primary synchronization;
and performing secondary synchronization by using a 50ms time slice of the crystal oscillator of the antifuse FPGA.
The following explanation of time synchronization is given by taking a triple modular redundant processor as an example: as shown in fig. 4, the triple modular redundancy processor adopts a two-stage synchronization design, wherein the first-stage synchronization is that the triple modular redundancy processor uses an external navigation module second pulse to perform 1s time synchronization, and the processor performs second pulse interruption after receiving the pulse to synchronize local time, so that the starting time and the ending time of the periodic tasks of the three processors are consistent, and the task synchronization of the triple modular redundancy processor is ensured; the second-level synchronization is 50ms time slice synchronization, synchronous pulses are generated every 50ms by an anti-fuse FPGA by using a crystal oscillator of the anti-fuse FPGA, the three processors identify the pulses to carry out the time slice synchronization, namely, an external interrupt source is used as a trigger point of the system synchronization, and after the external interrupt arrives, the three processors mutually identify the interrupt states of the other two processors and enter an interrupt service program in a consistent mode. The interrupt service program mainly exchanges state and data, so that the time references of the three processor modules are finally synchronized, and the data synchronization of the triple-modular redundancy processor is ensured.
In a specific embodiment, the communication control board selects a FLASH type FPGA to complete an interface processing function, the FPGA is insensitive to a single event effect, a dual-computer cold standby FPGA system is designed, and reset and switching-off operation of a fault FPGA is realized through a watchdog circuit. The memory is made of MRAM, and is insensitive to single event effect, and does not produce single event locking and single event upset easily. NOR FLASH and NAND FLASH are selected for storing programs and data, and the correctness of the programs and the data is ensured by performing triple-out-of-two comparison during program and data reading through triple-modular redundancy storage of the programs and the data. And each driving or collecting chip of the driving layer, such as a CAN chip, a 422 chip, an OC chip, an AD chip and the like, adopts a redundancy backup design, so that the high reliability of the interface is ensured.
In a specific embodiment, the external function board cards comprise a measurement and control baseband board card, a measurement and control radio frequency board card and a motor drive and magnetic component circuit board,
wherein,
the motor driving and magnetic component circuit board is used for realizing a driving control function of an SADA (Solar Array Drive Assembly), a magnetic rod driving control function and an insensitive photocurrent signal processing function;
the measurement and control baseband board card and the measurement and control radio frequency board card are used for completing measurement and control signal receiving and sending and data interaction between the integrated electronic system and the ground measurement and control station; when the satellite is in the measurement and control arc section of the ground measurement and control station, the satellite is matched with the ground measurement and control station to complete the functions of remote measurement, remote control, distance measurement and speed measurement;
in a specific embodiment, the external functional board further includes,
the power supply comprises a primary power distribution board card, a secondary power supply conversion and power distribution board card;
the primary power distribution board card is used for receiving an OC instruction output by the communication control board, controlling the on-off of a power distribution switch on the primary power distribution board card and realizing the power-on and power-off control of each path of primary power output.
The secondary power supply conversion and distribution board card is used for realizing voltage conversion from a primary power supply to a secondary power supply, receiving an OC instruction output by the communication control board, controlling the on-off of a distribution switch on the secondary distribution board card and realizing the on-off control of each secondary power supply output.
In a specific embodiment, the backplane is connected to the core processing board, the communication control board, and the external function board via an SPI bus.
In a specific embodiment, as shown in fig. 5, each control board of the integrated electronic system is connected to an external load through an interface, where the external load includes, for example: the system comprises a magnetometer, a magnetic torquer, a satellite sensitive probe 1, a satellite sensitive probe 2, an satellite sensitive probe A, an satellite sensitive probe B, primary electric equipment, secondary electric equipment, an S/X radio frequency antenna, a GNSS antenna and the like. The external function board card receives a control instruction of the core processing board card through interface conversion of the communication control board and sends the control instruction to a corresponding external load to control the operation of the external function board card, and measurement data received by the external load is converted and returned to the core processing board card through the interface of the communication control board.
It should be noted that, in the description of the present invention, relational terms such as first and second, and the like are used only for distinguishing one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between the entities or operations. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations and modifications can be made on the basis of the above description, and all embodiments cannot be exhaustive, and all obvious variations and modifications belonging to the technical scheme of the present invention are within the protection scope of the present invention.
Claims (10)
1. A satellite-borne integrated electronic system based on COTS devices is characterized by comprising:
a core processing board card, a communication control board card, a signal acquisition board card and an external function board card which are respectively connected with the backboard in a bidirectional way,
wherein,
the core processing board card is used for receiving the measurement data returned by the external load, analyzing and operating the measurement data, storing system operation data, and sending effective operation results and control instructions to the external function board card through the backboard;
the communication control board card is used for realizing signal communication between the core processing board card and an external load and an external function board card, sending received communication data to the core processing board card through the backboard, and finishing the output of an OC instruction of the core processing board card;
the signal acquisition board card is used for acquiring external loads and analog quantity data of the external function board card and sending the data to the core processing board card through the backboard;
the external function board card is used for receiving and executing a control instruction sent by the core processing board or sending a control signal to an external load through interface conversion; and transmitting the measurement data returned by the external load back to the core processing board card.
2. Integrated electronic system according to claim 1,
the core processing board card comprises an arithmetic unit and a voting unit;
wherein,
the arithmetic unit consists of N processors, wherein N is more than or equal to 3, and the processors are connected through a processor bus.
3. Integrated electronic system according to claim 2,
the arithmetic unit adopts a triple modular redundancy design and comprises,
the first hot standby processor, the second hot standby processor and the third hot standby processor are respectively arranged for receiving the measurement data returned by the external load and simultaneously carrying out operation processing;
the arithmetic unit also comprises a first cold standby processor and a second cold standby processor, and when the hot standby processor fails, the first cold standby processor and the second cold standby processor are replaced to keep the running state of the three machines in hot standby.
4. Integrated electronic system according to claim 3,
the voting unit is composed of an antifuse FPGA chip,
each processor of the operation unit opens up 3 registers to store three-machine processing data, reads the three-machine processing data from the corresponding register respectively, carries out two-out-of-three voting, completes one-level voting and broadcasts the voting result to the antifuse FPGA chip of the voting unit;
and the anti-fuse FPGA chip carries out secondary voting according to the voting result, determines the operation unit to be on the spot and outputs an effective operation result after the voting is consistent.
5. Integrated electronic system according to claim 3,
and the arithmetic unit utilizes the navigation second pulse of the external navigation module and the antifuse FPGA chip to perform time synchronization so as to enable the task cycles of the N processors to be consistent.
6. Integrated electronic system according to claim 5,
the operation unit utilizes the pulse per second of the external navigation module and the anti-fuse FPGA chip to carry out time synchronization and comprises the following steps:
the N processors utilize the second pulse of the external navigation module to carry out 1s time synchronization, and the processors carry out second pulse terminal synchronization local time after receiving the second pulse of the external navigation module to complete primary synchronization;
and the N processors perform secondary synchronization by using a 50ms time slice of the crystal oscillator of the anti-fuse FPGA chip.
7. Integrated electronic system according to claim 1,
the external function board card comprises a measurement and control baseband board card, a measurement and control radio frequency board card and a motor drive and magnetic component circuit board,
wherein,
the measurement and control baseband board card and the measurement and control radio frequency board card are used for completing measurement and control signal receiving and transmitting and data interaction between the integrated electronic system and the ground measurement and control station; when the satellite is in the measurement and control arc section of the ground measurement and control station, the satellite is matched with the ground measurement and control station to complete the functions of remote measurement, remote control, distance measurement and speed measurement;
the motor drive and magnetic component circuit board is used for realizing the SADA drive control function, the magnetic bar drive control function and the function of processing an ultra-sensitive photocurrent signal.
8. Integrated electronic system according to claim 7,
the external function board card also comprises a card body,
a primary power distribution board card, a secondary power supply transformation and distribution board card;
the primary power distribution board card is used for receiving an OC instruction output by the communication control board, controlling the on-off of a power distribution switch on the primary power distribution board card and realizing the power on-off control of each path of primary power output;
the secondary power supply conversion and distribution board card is used for realizing voltage conversion from a primary power supply to a secondary power supply, receiving an OC instruction output by the communication control board, controlling the on-off of a distribution switch on the secondary distribution board card and realizing the on-off control of each secondary power supply output.
9. Integrated electronic system according to claim 7,
the backboard is connected with the core processing board card, the communication control board card, the signal acquisition board card and the external function board card through an SPI bus.
10. Integrated electronic system according to claim 7,
the components of the integrated electronic system are COTS devices.
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- 2022-05-31 CN CN202210608845.3A patent/CN115168114A/en active Pending
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| CN115372044A (en) * | 2022-10-25 | 2022-11-22 | 中国航空工业集团公司金城南京机电液压工程研究中心 | Detection control device integrated in electromechanical product and use method thereof |
| CN115766503A (en) * | 2022-11-14 | 2023-03-07 | 天津航空机电有限公司 | Method for detecting board card configuration of secondary power distribution system and verifying communication link |
| CN116599563A (en) * | 2023-05-12 | 2023-08-15 | 航天时代飞鹏有限公司 | Aviation multimode communication all-in-one |
| CN117439277A (en) * | 2023-12-21 | 2024-01-23 | 天津航空机电有限公司 | Communication network structure and communication method of secondary power distribution system |
| CN117439277B (en) * | 2023-12-21 | 2024-04-09 | 天津航空机电有限公司 | Communication network structure and communication method of secondary power distribution system |
| CN118092873A (en) * | 2024-04-19 | 2024-05-28 | 贵州航天控制技术有限公司 | Three-self inertial navigation software architecture design method based on multi-core processor |
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