CN116660899B - Near-field target ISAR imaging system and device based on FPGA+DSP - Google Patents
Near-field target ISAR imaging system and device based on FPGA+DSP Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/9004—SAR image acquisition techniques
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/904—SAR modes
- G01S13/9052—Spotlight mode
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/904—SAR modes
- G01S13/9064—Inverse SAR [ISAR]
Abstract
The application provides a near-field target ISAR imaging system and equipment based on FPGA+DSP, which receives echo data and corresponding parameter information in each pulse through an FPGA chip; calculating a time domain compensation coefficient and a frequency domain compensation coefficient of echo data, and compensating the echo data according to the time domain compensation coefficient and the frequency domain compensation coefficient to obtain a data compensation result; and circularly and alternately receiving data compensation results in one period through two pieces of multi-core DSP chips, and performing self-focusing processing on the data compensation results in each period in a multi-core synchronous parallelization processing mode to obtain imaging waveform data, and finally imaging. The application fully utilizes the advantages of FPGA parallel processing data and the advantages of complex floating point operation and multi-core parallel processing of the multi-core DSP, so that the processing task allocation of the imaging algorithm is optimal as much as possible. The application can reduce the imaging operation amount and improve the imaging efficiency.
Description
Technical Field
The application belongs to the technical field of radar imaging processing, and particularly relates to a near-field target ISAR imaging system and device based on FPGA+DSP.
Background
Radar target imaging is an important process for radar target detection, and in conventional ground radar ISAR imaging, is mainly implemented by range profile envelope alignment and self-focusing. For high-speed moving objects, conventional imaging schemes may cause an increase in the Doppler bandwidth of the object. In practical process application, because the action distance is far, even if a high-speed target is imaged, the system repetition frequency is generally below kilohertz, and the real-time requirement can be generally met.
Under the condition that the speed of a high-speed platform and the speed of a moving target are high, the target is required to be hit accurately through two-dimensional imaging, and the platform needs to respond in time within a very short time, so that higher requirements are put forward on the instantaneity of an imaging system. However, the existing ISAR imaging technology has long time consumption in the parts of envelope alignment and self-focusing processing, is not enough to meet the high real-time requirement of sub-millisecond level in engineering application, and has a large lifting space, and the acceleration algorithm processing design needs to be further optimized by thinking.
Disclosure of Invention
In order to solve the problems in the prior art, the application provides a near-field target ISAR imaging system and equipment based on FPGA+DSP, and the technical scheme of the application is as follows:
in a first aspect, the present application provides a near field target ISAR imaging system based on fpga+dsp, comprising: one FPGA chip and two multi-core DSP chips;
the FPGA chip receives echo data in each pulse sent by the upper computer and parameter information corresponding to the echo data; calculating a time domain compensation coefficient and a frequency domain compensation coefficient of echo data according to the parameter information, and compensating the echo data according to the time domain compensation coefficient and the frequency domain compensation coefficient to obtain a time-frequency domain data compensation result; sending the data compensation result to two multi-core DSP chips; wherein there are multiple pulses within each cycle;
the method comprises the steps that two pieces of multi-core DSP chips circularly and alternately receive a data compensation result in one period, and perform self-focusing processing on the data compensation result in each period in a multi-core synchronous parallelization processing mode to obtain imaging waveform data; and sending the imaging waveform data back to the upper computer so that the upper computer can perform imaging.
In a second aspect, the application provides near-field target ISAR imaging equipment based on FPGA+DSP, which is provided with a near-field target ISAR imaging system based on FPGA+DSP.
The application has at least one of the following advantages:
firstly, the application fully utilizes the advantages of parallel data processing of the FPGA, complex floating point operation of the multi-core DSP and multi-core parallel processing, so that the task allocation of the imaging algorithm is optimal as much as possible.
Secondly, the time-frequency domain compensation coefficient is calculated by utilizing the FPGA chip in advance by two pulses, so that the time of the FPGA for carrying out floating point number operation on the time-frequency domain compensation coefficient is greatly shortened. In addition, according to the characteristic of uncorrelation of compensation coefficients of each point in time-frequency domain compensation, the process of calculating the compensation coefficients is further processed in parallel and IP is packaged, and the advantage of FPGA parallel processing is utilized to the greatest extent.
Thirdly, the application uses two multi-core DSP chips to carry out ping-pong pipeline operation, which can greatly improve the data processing efficiency and reduce the target imaging rate by about half. And the data compensation results with large data quantity are shared by seven cores in the DSP chip for parallel processing, so that the advantage of multi-core parallel processing is greatly exerted. In addition, in the self-focusing process of the data compensation result of each checking part, the process of comparing and screening with the threshold value is arranged before sorting, so that part of special display points can be screened out in advance, the data scale input by a sorting algorithm is reduced, the operation amount is reduced, the efficiency is improved, and the time consumption is reduced.
The present application will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a near field target ISAR imaging system based on FPGA+DSP;
FIG. 2 is a schematic diagram of a parallelized design flow of a field programmable gate array FPGA algorithm;
fig. 3 is a schematic diagram of an algorithm design flow of a multi-core DSP digital signal processor.
Detailed Description
The present application will be described in further detail with reference to specific examples, but embodiments of the present application are not limited thereto.
Because the radar imaging algorithm has complex signal processing and needs to carry out a large number of floating point operations, the radar signal processing system is required to have higher performance in terms of data storage capacity and real-time processing capacity.
Referring to fig. 1 to 3, the present application provides a near field target ISAR imaging system based on fpga+dsp, including: one FPGA chip and two multi-core DSP chips;
the FPGA chip receives echo data in each pulse sent by the upper computer and parameter information corresponding to the echo data; calculating a time domain compensation coefficient and a frequency domain compensation coefficient of echo data according to the parameter information, and compensating the echo data according to the time domain compensation coefficient and the frequency domain compensation coefficient to obtain a time-frequency domain data compensation result; sending the data compensation result to two multi-core DSP chips; wherein there are multiple pulses within each cycle;
the method comprises the steps that two pieces of multi-core DSP chips circularly and alternately receive a data compensation result in one period, and perform self-focusing processing on the data compensation result in each period in a multi-core synchronous parallelization processing mode to obtain imaging waveform data; and sending the imaging waveform data back to the upper computer so that the upper computer can perform imaging.
In a specific embodiment, the FPGA chip receives echo data and corresponding parameter information sent from the upper computer through the RS422 serial port, performs downsampling processing on the echo data by adopting a direct extraction method, and caches a downsampling result corresponding to each pulse into its own asynchronous FIFO.
Noteworthy are: the radar echo is generated by simulating a high-speed moving object according to a near-field low-speed moving object, and parameter information is different under different changing scenes. The parameter information mainly relates to the number of distance points N, the number of pulses M, the sampling rate Fs, the pulse repetition frequency PRF, etc. According to the application, several groups of representative scene parameters are simulated in advance to carry out echo data generation and imaging processing, firstly, the upper computer sends information such as simulated echo data and parameters in different scenes to the FPGA through the RS422 serial port, the FPGA receives the parameters and AD receives the echo data, and the AD receives the echo data and then carries out downsampling processing by adopting a direct extraction method, and the echo data is buffered into the asynchronous FIFO.
In a specific embodiment, calculating the time domain compensation coefficient and the frequency domain compensation coefficient of the echo data based on the parameter information comprises: the chip of the FPGA is provided with a plurality of channels,
calculating a frequency domain compensation coefficient of echo data according to the parameter information;
when a pulse downsampling result is entered into the asynchronous FIFO, a time domain compensation coefficient of echo data in the pulse is calculated according to the parameter information, and the time domain compensation coefficient and the frequency domain compensation coefficient are stored into the RAM.
Noteworthy are: after the FPGA chip receives the parameter information, the time domain compensation coefficient and the frequency domain compensation coefficient of the echo signal can be calculated according to the received parameter information, and the time domain compensation coefficient and the frequency domain compensation coefficient are different. Wherein the time-domain compensation coefficient is related to the fast time sequence and the slow time sequence of the echo data, and each point of the echo corresponds to one compensation coefficient, i.e. each pulse corresponds to one time-domain compensation coefficient. The calculated time domain compensation coefficients are stored in the FIFO each time for simultaneous reading thereafter, the time domain compensation coefficients being calculated M times in total in one burst period CPI. The frequency domain compensation coefficient is only related to the waveform fast time sequence, the frequency domain compensation coefficient in one CPI is only calculated once, and the frequency domain compensation coefficient calculation result is repeatedly read in the RAM. The calculation of the time-frequency domain compensation coefficient of the application involves multiplication and division of a large number of floating point numbers, can develop corresponding IP cores by using Vivado HLS software, adopts C++ compiling, has simple algorithm, high operation precision, easy understanding, easy modification and strong portability.
In a specific embodiment of the present application, the compensating the echo data according to the time domain compensation coefficient and the frequency domain compensation coefficient to obtain the data compensation result of the time domain includes:
reading the time domain compensation coefficient of the current pulse from the RAM;
carrying out complex multiplication on the time domain compensation coefficient of the current pulse and the downsampling result of the current pulse to carry out time domain compensation on the downsampling result, and carrying out FFT (fast Fourier transform) calculation on the time domain compensated result to obtain a time domain compensation result;
according to the waveform data length of the echo data, the FPGA chip in this embodiment performs 0-compensating or 0-non-compensating operation on the downsampling result, and performs FFT calculation on the 0-compensating or 0-non-compensating execution result to obtain a time-domain compensation result.
Reading frequency domain compensation coefficients from the RAM;
and carrying out complex multiplication on the frequency domain compensation coefficient and the time domain compensation result to obtain a time-frequency domain data compensation result.
Noteworthy are: when echo data in each pulse arrives and the FIFO is enough for one PRT (Pulse Repetition Time, pulse repetition period), the time domain compensation coefficient corresponding to each pulse is subjected to time domain compensation with the echo data, then FFT calculation is performed on the result after the time domain compensation by an FFT module, and the calculation time of the FFT module is mainly determined by hardware. The difference of the parameter settings of the waveforms can cause the difference of the echo distance direction point number, and when the length of one waveform data does not meet the power of 2 to the power of n, the 0 supplementing operation is carried out before the FFT operation is carried out. The application can be realized by utilizing an FFT core provided by an FPGA chip manufacturer, and the FFT core supplements the waveform point number to the power of n of 2 by configuring the FFT core into a point number programmable mode and adding a group of time sequence logic circuits for judging the point number.
After the FFT calculation is finished, synchronously reading the frequency domain compensation coefficient which is calculated in advance, and performing complex multiplication operation again to realize frequency domain compensation. And reading the frequency domain compensation coefficient stored in the RAM by using the FFT core output enable, pulling up the RAM read enable in time sequence, generating data of a corresponding address after two beats, synchronizing the time domain compensation result to carry out two beats of time delay, and synchronously entering the read RAM data and the obtained time domain compensation result into a complex multiplication module to carry out frequency domain compensation calculation.
In the above process, the time consumed by the algorithm processing of the FPGA chip should include one time of frequency domain compensation coefficient calculation, M times of time domain complex multiplication, M times of FFT calculation, and one time of frequency domain complex multiplication calculation, where the time consumed by the single time-frequency domain compensation coefficient calculation is longer, even longer than the sum of the remaining processing time, and the time domain compensation coefficient is calculated M times in total, and the processing time is greatly prolonged by successively calculating the time domain compensation coefficient corresponding to each pulse one by one and then performing complex multiplication. The parallel processing thinking is introduced to perform the optimization design, and the parallel design of the FPGA processing part of the present application is described in further detail with reference to fig. 2.
After the radar parameters of the upper computer reach the FPGA, the calculation of the frequency domain compensation coefficient which is only once and the time domain compensation coefficients corresponding to the first two pulses is finished in parallel, then echo data is read, and in the calculation of the later compensation coefficients, the calculation of the frequency domain compensation coefficients is not needed to be considered, and only the parallel calculation of the time domain compensation coefficients of the two pulses is carried out. The time-frequency domain compensation and FFT parallel processing of the first two pulses are overlapped on the basis, and the parallelization processing is exerted to the maximum. In the rest algorithm part, the compensation is to complete time domain complex multiplication while reading signal data, the time-frequency domain complex multiplication consumes little redundant time, the time is mainly concentrated in the FFT calculation part, the time of pulse repetition period is enough to complete complex multiplication and FFT calculation, and finally, the complex multiplication is carried out while the complex multiplication is carried out when the frequency domain is compensated, the data after the complex multiplication is transmitted to SRIO, the redundant time consumption is not carried out, and the parallel processing operation is continuously carried out by repeating the same.
Referring to FIG. 3, in a specific embodiment of the present application, the two multi-core DSP chips are 8-core DSP chips;
the 0 th core is responsible for receiving a data compensation result in one period and carrying the data compensation result to SL 2; and pulling down the flag bit of the semaphore by acquiring the semaphores of the 1 st core to the 7 th core, wherein the flag bit of the semaphore being low indicates that the core is in an occupied state.
Noteworthy are: the method comprises the steps that SRIO communication between a 0 th core in a DSP chip and an FPGA is established, firstly, the 0 th core carries out configuration and initialization of a core clock, DDR3 speed, reference clock frequency, a CACHE CACHE, DMA and SRIO, then waits for the FPGA chip to send data, the arrived data are placed on a shared memory DDR3 address, after the data are sent, an interrupt instruction is transmitted through a DoorBell, the 0 th core triggers the interrupt to enter an interrupt service function SRIO_DoorBell_isr, DMA data moving compensation results are carried out on SL2, and the signal quantity of each core is obtained. And starting DMA (direct memory access ) corresponding to one doorbell signal transmission, then moving the data shift compensation result in one signal length PRT to SL2, and pulling down the flag bit of the signal quantity by acquiring the signal quantity of each core to finish data receiving between the FPGA and the DSP.
In the process, when DMA is used, RAM parameter setting of the direct memory access controller is reconfigured, parallel transmission of the EDMA is realized by adopting a plurality of channel controllers and a transmission controller, the size of a data block of single burst transmission of the EDMA (Enhanced Direct Memory Access ) is increased, FIFO channels of the EDMA are fully utilized, and the maximization of data throughput between two memory mapped slave terminals on a device is realized. Meanwhile, the FPGA control is enabled to send the processed data to the corresponding DSPs through the SRIO high-speed interface, the double DSP chips (DSP 1 and DSP 2) circularly receive the data to carry out big Ping-Pong operation of two adjacent CPIs, the two DSP chips are loaded with the same operation program to carry out data processing, each piece of DSP processes echo data in one CPI to form a frame of image, ping-Pong operation is alternately formed, and the actual time consumption of the DSPs in the design is the time consumed in the DSPs with longer time consumption in the DSP1 and the DSP 2.
In a specific embodiment of the present application, each of the 1 st core to the 7 th core determines a data address according to its own core number and a length of a data compensation result in an occupied state, reads a required portion of the data compensation result from SL2 according to the data address, performs self-focusing processing on the required portion, and then buffers the data address into a buffer space. After the 1 st core to the 7 th core finish the self-focusing processing in one period, the 0 th core sends a release command to the 1 st core to the 7 th core, so that the 1 st core to the 7 th core pull up the flag bit of the signal quantity of the 1 st core, wherein the flag bit of the signal quantity is high, which indicates that the core is in an idle state. The 1 st core judges whether all cores are in an idle state, if so, the data output zone bit is pulled up; reading the self-focusing processing result of each core from the cache space and performing FFT operation when the 0 th core detects that the data output flag bit is pulled up; and outputting the FFT operation result of the self-focusing processing result to the upper computer in parallel so as to enable the upper computer to image.
Noteworthy are: the 8 cores firstly judge the semaphore, and when the 0 th core judges that the semaphore is acquired, the semaphore is released to wait for the arrival of the next data. The 1 st core to the 7 th core perform self-focusing algorithm processing after obtaining the signal quantity, and the self-focusing algorithm processing comprises energy ratio sequencing, finding the special display point and synthesizing the special display point. For the design of 7-core synchronous parallel processing, the application firstly judges the inter-core synchronization, divides the data compensation result into 7 parts according to the dividing of the distance point number into 7 parts in the algorithm processing process of each step, respectively distributes the 7 parts for parallel processing of the cores, and places the carried data compensation result on the SL2 shared memory by the 0 th core, wherein each core is visible. The allocation is performed by data hop address mapping by each core that acquires the core number. If the data compensation result cannot be integrated, the rest redundant data is delivered to the 1 core to be continuously processed, 7 cores simultaneously process the respective divided partial data compensation result, and the judgment of inter-core synchronization is carried out before and after each parallel processing, so that all processes of the self-focusing algorithm are completed according to the same parallel processing method. The hardware implementation advances the threshold comparison process in finding the special display points to the process of calculating the energy ratio, searches the data smaller than the threshold according to the energy ratio calculated in the first step and records the value and ID of the data before sorting, then rapidly sorts the screened data, screens out part of the special display points in advance, and reduces the data scale input by a sorting algorithm.
In the processing process of the multi-core DSP, the whole implementation design logic drives the 8 cores to maintain correct time sequence and operation flow by means of signal quantity and data output zone bits.
Referring to fig. 3, the design of the DSP multi-core timing control flow of the present application is further described in detail. The first is a data output flag bit signal which is in a pull-down state when initialized, and is controlled to be pulled up by the 1 st core, and the pull-up time is that the flag bit is pulled up by the 1 st core after the 7 th core synchronization algorithm is completely finished. When the 0 th core judges that the interrupt signal quantity is obtained and released, the state of waiting for the data output zone bit signal to be pulled up is kept, once the data output zone bit signal is pulled up, when the 0 th core pulls down the zone bit and then enters a TCP (transmission control protocol) network port for transmission, and the self-focusing processing result is completely returned to the upper computer through the network port. The second is a semaphore, the module of hardware semaphore being accessible to all cores on the DSP, each core having access to the respective semaphore. The manner in which the DSP core obtains the semaphore is achieved by reading the value of the corresponding semaphore register sem_correct, and if the semaphore is in an idle state, the return value of the register is 1, whereas the return value is 0. Initially, the semaphore is in an idle state, when the csl_ semAcquireDirect (Num) acquires the semaphore, the semaphore is in an occupied state, and when the csl_ semReleaseSeamphare (Num) releases the semaphore, the semaphore returns to the idle state. Csl_semfree (Num) can be used to determine whether the semaphore numbered Num is in an idle state. After the 0 th core pulls down the last data output zone bit, the transmission algorithm is needed to be carried out by acquiring the returned semaphore as an entrance returned by the network port, and then the semaphore is released after the task is ended. And the semaphore and the data output zone bit are restored to the initialized state, the operation of the complete DSP chip is finished, and the next SRIO receives data.
There is multi-core parallel processing and inter-core synchronous processing. The synchronization data among cores is realized by judging the states of corresponding semaphores of the cores. And 7 cores acquire the semaphore with the number corresponding to the core, then judging whether 7 cores acquire the corresponding semaphore, if not, executing the loop all the time by the program, waiting for all the cores to acquire the semaphore until each core acquires the semaphore, continuing the jump-out loop to run downwards by the program, and releasing the corresponding semaphore after each core processes the corresponding partial algorithm module. And judging whether each core releases the corresponding semaphore, if so, continuing to run the next algorithm module by the program, otherwise, continuing to run the loop by the program until each core releases the semaphore, and continuing to run the program by jumping out of the loop until each core releases the semaphore. The following algorithm module is then executed. Therefore, through the judgment of the reciprocating acquisition and release signal quantity, the data synchronization operation among multiple cores is realized, and the accuracy of parallel processing is ensured.
And finally, carrying out 7-kernel synchronization in azimuth and high-efficiency FFT operation on the data subjected to self-focusing processing of the DSP chip, and completing sub-millisecond signal data processing to obtain imaging waveform data. And packaging the processing result, and returning the processing result to the upper computer for imaging through the gigabit Ethernet port.
The application provides near-field target ISAR imaging equipment based on FPGA+DSP, which is provided with a near-field target ISAR imaging system based on FPGA+DSP.
The application adopts various innovative methods in the aspects of system, software algorithm and hardware realization, utilizes a signal processing board card formed by a piece of FPGA chip and two pieces of eight-core DSP chips in a heterogeneous way to perform sub-millisecond optimization processing design on the high-speed near-field target ISAR imaging system, and the signal processing platform has strong floating point operation capability and flexibility, reduces the complexity of hardware design and has high resource utilization rate. The FPGA time-frequency domain compensation module and the DSP self-focusing parallel processing are designed, meanwhile, the distribution of the FPGA and the DSP algorithm can be optimized, the advantages of the FPGA high-efficiency parallel processing data, the DSP complex floating point number operation and the multi-core parallel data processing are fully exerted, the parallelism is maximized, the parallel processing exists between the FPGA and the DSP, the FPGA and the DSP and between the DSP and the multi-core, the two DSPs can perform ping-pong operation, the DSP operation time is reduced by half integrally, and the defect of slow operation time of the DSP of the complex algorithm is overcome. Under the condition of no loss of imaging quality, the processing time of the algorithm can reach the sub-millisecond level finally.
Referring to the time consumption of the imaging system shown in the table 1, the application is realized by carrying out algorithm optimization acceleration processing design of the two-dimensional high-resolution imaging system by using the radar echo generated by simulating the high-speed motion by the near-field low-speed motion, so that the algorithm processing time can finally reach the requirement of sub-millisecond level, and the requirement of higher real-time performance under a plurality of application scenes is greatly met while high-precision imaging is ensured. From Table 1, it can be seen that the time consumption of the present application is greatly reduced.
Table 1 Algorithm time-consuming table
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Although the application is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality.
The foregoing is a further detailed description of the application in connection with the preferred embodiments, and it is not intended that the application be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the application, and these should be considered to be within the scope of the application.
Claims (8)
1. Near field target ISAR imaging system based on FPGA+DSP, characterized by comprising: one FPGA chip and two multi-core DSP chips;
the FPGA chip receives echo data in each pulse sent by the upper computer and parameter information corresponding to the echo data; calculating a time domain compensation coefficient and a frequency domain compensation coefficient of the echo data according to the parameter information, and compensating the echo data according to the time domain compensation coefficient and the frequency domain compensation coefficient to obtain a time-frequency domain data compensation result; sending the data compensation result to the two multi-core DSP chips; wherein there are multiple pulses within each cycle;
the two multi-core DSP chips circularly and alternately receive the data compensation result in one period, and perform self-focusing processing on the data compensation result in each period in a multi-core synchronous parallelization processing mode to obtain imaging waveform data; sending the imaging waveform data back to the upper computer so as to enable the upper computer to image;
the calculating the time domain compensation coefficient and the frequency domain compensation coefficient of the echo data according to the parameter information comprises: the chip of the FPGA is provided with a plurality of data channels,
calculating a frequency domain compensation coefficient of the echo data according to the parameter information;
when a down-sampling result of a pulse is entered into the asynchronous FIFO, calculating a time domain compensation coefficient of echo data in the pulse according to the parameter information, and storing the time domain compensation coefficient and the frequency domain compensation coefficient into the RAM;
the FPGA chip receives echo data and corresponding parameter information sent by an upper computer through an RS422 serial port, performs downsampling processing on the echo data by adopting a direct extraction method, and caches a downsampling result corresponding to each pulse into an asynchronous FIFO of the FPGA chip.
2. The near field target ISAR imaging system based on fpga+dsp according to claim 1, wherein the compensating the echo data according to the time domain compensation coefficient and the frequency domain compensation coefficient to obtain a time-frequency domain data compensation result includes:
reading a time domain compensation coefficient of a current pulse from the RAM;
carrying out complex multiplication on the time domain compensation coefficient of the current pulse and the downsampling result of the current pulse to carry out time domain compensation on the downsampling result, and carrying out FFT (fast Fourier transform) calculation to obtain a time domain compensation result;
reading the frequency domain compensation coefficients from the RAM;
and carrying out complex multiplication on the frequency domain compensation coefficient and the time domain compensation result to obtain a time-frequency domain data compensation result.
3. The near field target ISAR imaging system based on fpga+dsp according to claim 2, wherein the FPGA chip performs 0-compensating or 0-not-compensating operation on the downsampling result according to the waveform data length of the echo data, and performs FFT calculation on the 0-compensating or 0-not-compensating execution result to obtain a time-domain compensation result.
4. The near field target ISAR imaging system based on fpga+dsp according to claim 3, wherein the two multi-core DSP chips are 8-core DSP chips;
the 0 th core is responsible for receiving the data compensation result in the period and carrying the data compensation result to SL 2; pulling down the flag bit of the semaphore by acquiring the semaphores of the 1 st core to the 7 th core;
wherein a low flag bit of the semaphore indicates that the core is in an occupied state.
5. The near field target ISAR imaging system based on fpga+dsp according to claim 4, wherein each of the 1 st core to the 7 th core determines a data address according to its own core serial number and a length of a data compensation result in an occupied state, reads a required part of the data compensation result from SL2 according to the data address, performs self-focusing processing on the required part, and then buffers the data address in a buffer space.
6. The fpga+dsp based near field target ISAR imaging system according to claim 5, wherein after the 1 st core to the 7 th core each complete the self-focusing process in one cycle, the 0 th core will send a release command to the 1 st core to the 7 th core, causing the 1 st core to the 7 th core to pull up a flag bit of its own semaphore;
wherein a high flag bit of the semaphore indicates that the core is in an idle state.
7. The near field target ISAR imaging system based on fpga+dsp according to claim 6, wherein the 1 st core judges whether all cores are in an idle state, and if so, pulls up a data output flag bit; reading the self-focusing processing result of each core from the cache space and performing FFT operation when the 0 th core detects that the data output flag bit is pulled up; and outputting FFT operation results to the upper computer in parallel so as to enable the upper computer to image.
8. A near field target ISAR imaging device based on fpga+dsp, characterized in that a near field target ISAR imaging system based on fpga+dsp as claimed in any one of claims 1 to 7 is provided.
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