CN108228262A - A kind of quick loading methods of TigerSharc DSP - Google Patents

Abstract

The invention belongs to embedded computer fields, are related to a kind of quick loading methods of TigerSharc DSP.This method uses FPGA as transmission intermediary, utilize the LINK interface high speed data transfer advantages of TigerSharc DSP, the program data stored in FLASH is read by DSP local bus by FPGA, inside FPGA data buffer storage is carried out by FIFO, data are transmitted to the LINK interfaces of DSP according to LINK interface transmission protocols simultaneously, are loaded so as to fulfill DSP programs.Advantage is to take full advantage of the processing feature of the flexible interface features of FPGA and parallelization Hardware, builds the loading environment based on LINK interfaces, on the basis of system hardware condition is not changed, can improve the loading velocity of DSP, shortens and starts the time.

Description

A kind of quick loading methods of TigerSharc DSP

Technical field：

The invention belongs to embedded computer fields, are related to a kind of quick loading methods of TigerSharc DSP.

Background technology：

Image trace processing system usually requires that there is system shorter program loading to start the time, to ensure after the power is turned on Enough quick tracking targets.TigerSharc DSP are extensive due to the l ink communication interfaces of the higher speed of service and high-speed Applied to the high-speed digital signals process field such as image procossing.

The loading of TigerSharc DSP programs, which starts, supports main boot and from two kinds of bootmodes of guiding, in most of applications Middle generally use main boot pattern, in this mode, TigerSharc use the address of DSP local bus, number as masters According to, read-write etc. signals loading code from EPROM or FLASH, this guidance mode limited by bus access sequential, program It is slow that loading starts speed, it is impossible to meet the requirement of image trace processing system.In the slave mode, TigerSharc is as quilt Dynamic side does not export control signal to outside, only starts several DMA and performs the loading core received by first DMA, loading speed Degree is fast.From load mode commonly used in multicomputer system, by primary processor or external host by LINK interfaces into stroke Sequence loads, and loading velocity is very fast, but external host is needed to have LINK interfaces.

FPGA extensively should at present due to having a variety of advantages such as flexible interface features, configurable access speed For in image processing system.The loading environment based on LINK interfaces is built using FPGA, it can be in the base for not changing hardware condition On plinth, loading velocity is improved, shortens and starts the time.

Invention content：

The purpose of the present invention is：

The present invention is the quick loading problem in order to solve DSP programs in image trace processing system.

The technical scheme is that：

Herein using FPGA as transmission intermediary, the high speed data transfer using the LINK interfaces of TigerSharc DSP is excellent Gesture devises a kind of quick loading methods of TigerSharc DSP, is read in FLASH and stored by DSP local bus by FPGA Program data, carry out data buffer storage by FIFO inside FPGA, while according to LINK interface transmission protocols to the LINK of DSP Interface transmits data, loads, is as follows so as to fulfill DSP programs：

A) DSP loadings and bus power control：The BMS pin status of TigerSharc DSP is set to ' 1 ' in FPGA, is matched It is from loading mode to put DSP.Controlled in FPGA by the HBR pin status to DSP, realize bus permission acquisition and Release.HBR pin status is set to ' 0 ', DSP release local bus before completing and weighs control to external equipment by DSP loadings；When After the completion of FPGA reads FLASH data, the HBR pin status of DSP is set to ' 1 ', gives back the DSP local bus rights to use to DSP；

B) FLASH reads control：The reset signal of FLASH, piece are selected in FPGA enable signal, output enable, write it is enabled Signal is controlled.The reset signal of FLASH is set to available state during DSP resets, and DSP is set to invalid after resetting； The piece of FLASH selects enable signal and output the enable signal CE and OE after DSP resets to be set to available state, when FLASH data Invalid state is set to after the completion of reading；FLASH write signals put invalid state；

C) FIFO writes control：It is 16 that depth is opened up inside FPGA, and the fifo buffer that width is 8 is to the FLASH of reading Data use 2 times of LINK interface clocks into row buffering, FIFO read-write clocks；FIFO writes control and is divided into 4 states, and when reset is State S0；After reset enter S1 states, FIFO write signals are set to available state in S1 states, judge FIFO whether expired and Whether FLASH data have run through, when FIFO is less than and FLASH data do not run through and continue to stay in S1 states, when FIFO has completely been redirected To S2 states, S3 states are jumped to when FLASH data have been run through；FIFO write signals are set to invalid state in S2 states, are judged FIFO expires state and FLASH data modes, and S1 states are jumped to when FIFO is less than and FLASH data are not run through, are otherwise stayed in S2 states；FIFO write signals are set to invalid state in S3 states, and eventually stop at S3 states, state machine terminates；

D) FIFO reads control：FIFO reads control and is divided into 2 states, reset or when FIFO empty or LINK mouthful do not allow transmission at In S4 states, FIFO read signals are set to invalid state in S4 states, when reset end and FIFO is not empty and LINK mouthfuls allow to send When jump to S5 states；FIFO read signals are set to available state in S5 states, if FIFO empty or LINK mouthfuls do not allow to send, are jumped S4 states are gone to, otherwise continue to stay in S5 states；

E) LINK interfaces send control：In FPGA according to LINK interfaces transmission timing generate LxCLKIN, LxCLKOUT, LxDAT, LxDIR signal.LxCLKOUT signals are the reference clock of LINK transmission datas；LxCLKIN signals connect for DSP ends LINK The answer signal of receiving end mouth, height expression can receive data, and low expression cannot receive data, pass through the prison to the signal in FPGA Survey judges whether DSP ends LINK interfaces allow transmission data；LxDAT signals are data to be sent, totally 8 position datawire, from Fifo buffer is read；LxDIR signal representation signal transmission directions are set to ' 1 ' in FPGA, and expression FPGA is sender；

F) step a), b), c), d) and, e) to be realized in FPGA, each step is parallel to be performed.

Present invention has the advantage that：

It is connect using the high speed LINK for building the mode of hardware logic electric circuit by program data and being sent to TigerSharc DSP Mouth takes full advantage of the processing feature of FPGA parallelization Hardwares, substantially reduces the load time of image trace processing system, Guarantee is provided quickly to track and then striking target.

Description of the drawings：

Fig. 1 is the quick loaded circuit schematic diagram of TigerSharc DSP programs；

Fig. 2 writes state of a control figure for FIFO；

Fig. 3 reads state of a control figure for FIFO.

Specific embodiment:

A kind of quick loading methods of TigerSharc DSP of the present invention are in certain image trace processing system Successful implementation, wherein DSP use ADSP company's T igerSharc series A DSP-TS101 chips, and FPGA uses Xi l inx companies XC2V3000 chips, FlASH uses the SM29LV160 chips of Shenzhen Guo Wei companies, stores the program data of 1.96Mbytes, LINK interface-clock-frequencies are configured to LINK interfaces default frequency (250/8) MHz in program.

The program data stored in FLASH is read by DSP local bus by FPGA, is carried out inside FPGA by FIFO Data buffer storage, while data are transmitted to the LINK interfaces of DSP according to LINK interface transmission protocols, it is final to realize adding for DSP programs It carries, is as follows：

A) the BMS pin status of TigerSharc DSP is set to ' 1 ' in FPGA, configuration DSP is from loading mode. HBR pin status is set to ' 0 ', DSP release local bus before completing and weighs control to external equipment by DSP loadings；When FPGA is read After the completion of taking FLASH data, the HBR pin status of DSP is set to ' 1 ', gives back the DSP local bus rights to use to DSP；

B) select the reset signal of FLASH, piece that enable signal, output be enabled, write enable signal controls in FPGA. The reset signal of FLASH is set to available state during DSP resets, and DSP is set to invalid after resetting；The piece choosing of FLASH is enabled Signal and output the enable signal CE and OE after DSP resets are set to available state, and nothing is set to after the completion of FLASH digital independents Imitate state；FLASH write signals put invalid state；FLASH reads the LINK interface clocks that clock is 2 times of program data, i.e. (250/4) MHz；

C) it is 16 that depth is opened up inside FPGA, and the fifo buffer that width is 8 delays the FLASH data of reading Punching, FIFO read-write clocks use 2 times of LINK interface clocks, i.e. (250/4) MHz；

D) FIFO writes control and is divided into 4 states, and when reset is state S0；Enter S1 states after reset, in S1 states FIFO write signals are set to available state, judge whether FIFO has expired and whether FLASH data have run through, when FIFO is less than and FLASH data, which are not run through, to be continued to stay in S1 states, when FIFO completely jumps to S2 states, is jumped to when FLASH data have been run through S3 states；FIFO write signals are set to invalid state in S2 states, judge that FIFO expires state and FLASH data modes, when FIFO not Full and FLASH data jump to S1 states when not running through, otherwise stay in S2 states；FIFO write signals are set in vain in S3 states State, and S3 states are eventually stopped at, state machine terminates；

E) FIFO readings control is divided into 2 states, reset or FIFO empty or LINK mouthfuls and does not allow to be in S4 states during transmission, FIFO read signals are set to invalid state by S4 states, and S5 shapes are jumped to when reset terminates and FIFO is not empty and LINK mouthfuls allow and send State；FIFO read signals are set to available state in S5 states, if FIFO empty or LINK mouthfuls do not allow to send, jump to S4 states, Otherwise continue to stay in S5 states；

F) the LINK interface transmission timings in ADSP-TS101 handbooks, in FPGA generate LxCLKIN, LxCLKOUT, LxDAT, LxDIR signal.LxCLKOUT signals are the reference clock of LINK transmission datas, i.e., match in FLASH programs LINK interface-clock-frequencies (250/8) MHz put；Answer signal of the LxCLKIN signals for DSP ends LINK receiving ports, high table Data can be received by showing, low expression cannot receive data, by judging that the monitoring of the signal DSP ends LINK interfaces are in FPGA No permission transmission data；LxDAT signals are data to be sent, totally 8 position datawire, are read from fifo buffer；LxDIR signals Representation signal transmission direction is set to ' 1 ' in FPGA, and expression FPGA is sender；

Above step performs parallel in FPGA, and the program data of loading 1.96Mbytes sizes is taken altogether as 86ms.Make Used time can improve the clock frequency of LINK interfaces in a program, further shorten the program load time.

Claims (1)

1. a kind of quick loading methods of TigerSharc DSP, it is characterized in that, FLASH is read by DSP local bus by FPGA The program data of middle storage carries out data buffer storage, while according to LINK interface transmission protocols to DSP inside FPGA by FIFO LINK interfaces transmission data, so as to fulfill DSP programs load, be as follows：

A) DSP loadings and bus power control：The BMS pin status of TigerSharc DSP is set to ' 1 ' in FPGA, configuration DSP is from loading mode；It is controlled, realize the acquisition of bus permission and released by the HBR pin status to DSP in FPGA It puts；HBR pin status is set to ' 0 ', DSP release local bus before completing and weighs control to external equipment by DSP loadings；Work as FPGA After the completion of reading FLASH data, the HBR pin status of DSP is set to ' 1 ', gives back the DSP local bus rights to use to DSP；

B) FLASH reads control：Enable signal, output is selected the reset signal of FLASH, piece to enable in FPGA, write enable signal It is controlled；The reset signal of FLASH is set to available state during DSP resets, and DSP is set to invalid after resetting；FLASH's Piece selects enable signal and output the enable signal CE and OE after DSP resets to be set to available state, when FLASH digital independents are completed Postposition is invalid state；FLASH write signals put invalid state；

C) FIFO writes control：It is 16 that depth is opened up inside FPGA, and the fifo buffer that width is 8 is to the FLASH data of reading Into row buffering, FIFO read-write clocks use 2 times of LINK interface clocks；FIFO writes control and is divided into 4 states, and when reset is state S0；After reset enter S1 states, FIFO write signals are set to available state in S1 states, judge FIFO whether expired and Whether FLASH data have run through, when FIFO is less than and FLASH data do not run through and continue to stay in S1 states, when FIFO has completely been redirected To S2 states, S3 states are jumped to when FLASH data have been run through；FIFO write signals are set to invalid state in S2 states, are judged FIFO expires state and FLASH data modes, and S1 states are jumped to when FIFO is less than and FLASH data are not run through, are otherwise stayed in S2 states；FIFO write signals are set to invalid state in S3 states, and eventually stop at S3 states, state machine terminates；

D) FIFO reads control：FIFO reading controls are divided into 2 states, reset or FIFO empty or LINK mouthfuls and do not allow to be in S4 during transmission FIFO read signals are set to invalid state by state in S4 states, are jumped when reset terminates and FIFO is not empty and LINK mouthfuls allow and send Go to S5 states；FIFO read signals are set to available state in S5 states, if FIFO empty or LINK mouthfuls do not allow to send, are jumped to Otherwise S4 states continue to stay in S5 states；

E) LINK interfaces send control：In FPGA according to LINK interfaces transmission timing generate LxCLKIN, LxCLKOUT, LxDAT, LxDIR signal；LxCLKOUT signals are the reference clock of LINK transmission datas；LxCLKIN signals connect for DSP ends LINK The answer signal of receiving end mouth, height expression can receive data, and low expression cannot receive data, pass through the prison to the signal in FPGA Survey judges whether DSP ends LINK interfaces allow transmission data；LxDAT signals are data to be sent, totally 8 position datawire, from Fifo buffer is read；LxDIR signal representation signal transmission directions are set to ' 1 ' in FPGA, and expression FPGA is sender；

F) step a), b), c), d) and, e) to be realized in FPGA, each step is parallel to be performed.