CN108228262B - Tiger Sharc DSP rapid loading method - Google Patents
Tiger Sharc DSP rapid loading method Download PDFInfo
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- CN108228262B CN108228262B CN201611139686.8A CN201611139686A CN108228262B CN 108228262 B CN108228262 B CN 108228262B CN 201611139686 A CN201611139686 A CN 201611139686A CN 108228262 B CN108228262 B CN 108228262B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
Abstract
The invention belongs to the field of embedded computers, and relates to a Tiger Sharc DSP rapid loading method. The method uses the FPGA as a transmission medium, utilizes the advantage of high-speed data transmission of the LINK interface of the Tiger Sharc DSP, reads program data stored in the FLASH through a DSP local bus by the FPGA, performs data caching in the FPGA through FIFO, and transmits data to the LINK interface of the DSP according to a LINK interface transmission protocol, thereby realizing DSP program loading. The method has the advantages that flexible interface characteristics of the FPGA and the processing characteristics of parallelization hardware are fully utilized, a loading environment based on the LINK interface is constructed, the loading speed of the DSP can be improved on the basis of not changing the hardware condition of the system, and the starting time is shortened.
Description
The technical field is as follows:
the invention belongs to the field of embedded computers, and relates to a Tiger Sharc DSP rapid loading method.
Background art:
image tracking processing systems generally require a system with a short program load start-up time to ensure that the target can be tracked quickly after power-up. The tiger share DSP is widely applied to the field of high-speed digital signal processing such as image processing due to a high operation speed and a high-speed i nk communication interface.
The Tiger Sharc DSP program loading starting supports two boot modes of main boot and auxiliary boot, the main boot mode is usually adopted in most applications, under the mode, Tiger Sharc is used as an active side, signals such as address, data, read-write and the like of a DSP local bus are used for loading codes from an EPROM or a FLASH, the boot mode is limited by bus access time sequence, the program loading starting speed is slow, and the use requirement of an image tracking processing system cannot be met. In the slave mode, TigerSharc is used as a passive side, a control signal is not output to the outside, only a plurality of DMA is started, and the loading core received by the first DMA is executed, so that the loading speed is high. The slave loading mode is generally used in a multiprocessor system, and a main processor or an external host loads a program through a LINK interface, so that the loading speed is high, but the external host needs to have the LINK interface.
FPGAs are widely used in image processing systems due to their advantages, such as flexible interface characteristics, configurable access speed, etc. The loading environment based on the LINK interface is constructed by using the FPGA, so that the loading speed can be increased and the starting time can be shortened on the basis of not changing the hardware condition.
The invention content is as follows:
the purpose of the invention is:
the invention aims to solve the problem of quick loading of DSP programs in an image tracking processing system.
The technical scheme of the invention is as follows:
the method for quickly loading the Tiger Sharc DSP comprises the following steps that an FPGA is used as a transmission medium, the advantage of high-speed data transmission of a LINK interface of the Tiger Sharc DSP is utilized, the FPGA reads program data stored in FLASH through a DSP local bus, data caching is carried out inside the FPGA through FIFO, and meanwhile data are transmitted to the LINK interface of the DSP according to a LINK interface transmission protocol, so that DSP program loading is realized, and the method comprises the following specific steps:
a) DSP loading and bus right control: setting the BMS pin state of the Tiger Sharc DSP to be '1' in the FPGA, and configuring the DSP to be in a slave loading mode. And the acquisition and release of the bus authority are realized by controlling the state of the HBR pin of the DSP in the FPGA. Setting the state of an HBR pin to be '0' before the DSP finishes loading, and releasing the local bus right control right to the external equipment by the DSP; after the FPGA finishes reading FLASH data, setting the HBR pin state of the DSP to be '1', and returning the DSP local bus use right to the DSP;
b) FLASH reading control: and controlling a reset signal, a chip selection enabling signal, an output enabling signal and a write enabling signal of the FLASH in the FPGA. The reset signal of the FLASH is set to be in an active state during the DSP reset period, and is set to be in an inactive state after the DSP reset is finished; the chip selection enabling signal and the output enabling signal of the FLASH are set to be in an active state after the DSP is reset, and are set to be in an inactive state after the FLASH data is read; the FLASH writing signal is set to be in an invalid state;
c) FIFO write control: opening an FIFO buffer area with the depth of 16 and the width of 8 in the FPGA to buffer the read-in FLASH data, wherein the FIFO read-write clock adopts a LINK interface clock of 2 times; the FIFO write control is divided into 4 states, and the state is S0 when the FIFO write control is reset; after the reset is finished, the state of S1 is entered, the FIFO writing signal is set to be the effective state in the state of S1, whether the FIFO is full and the FLASH data is read completely is judged, when the FIFO is not full and the FLASH data is not read completely, the state of S1 is continued, when the FIFO is full, the state of S2 is skipped, and when the FLASH data is read completely, the state of S3 is skipped; setting the FIFO writing signal to be in an invalid state in the S2 state, judging the FIFO full state and the FLASH data state, jumping to the S1 state when the FIFO is not full and the FLASH data is not read, and otherwise, remaining in the S2 state; the FIFO write signal is set to be in an invalid state in the state of S3, and finally stops in the state of S3, and the state machine is ended;
d) FIFO read control: the FIFO reading control is divided into 2 states, the state is S4 when the FIFO is empty or the LINK port is not allowed to transmit, the FIFO reading signal is set to be invalid in the state of S4, and the state jumps to the state of S5 when the reset is finished and the FIFO is not empty and the LINK port is allowed to transmit; setting the FIFO read signal to be in an effective state in the S5 state, jumping to the S4 state if the FIFO is empty or the LINK port is not allowed to transmit, and keeping in the S5 state if the FIFO is not empty or the LINK port is not allowed to transmit;
e) and (3) LINK interface sending control: LxCLKIN, LxCLKOUT, LxDAT, LxDIIR signals are generated in the FPGA according to a LINK interface transmission timing sequence. The LxCLKOUT signal is a reference clock for LINK to send data; the LxCLKIN signal is a response signal of a LINK receiving port of the DSP end, high indicates that data can be received, low indicates that data cannot be received, and the FPGA judges whether the LINK interface of the DSP end is allowed to send data or not by monitoring the signal; the LxDAT signal is data to be transmitted, and is read out from the FIFO buffer area by 8 bit data lines; the LxDIR signal represents the signal transmission direction, is set to be '1' in the FPGA, and represents that the FPGA is a sender;
f) the steps a), b), c), d) and e) are all realized in the FPGA, and all the steps are executed in parallel.
The invention has the advantages that:
the program data are sent to the high-speed LINK interface of the Tiger Sharc DSP by using a mode of building a hardware logic circuit, the processing characteristics of parallelization hardware of the FPGA are fully utilized, the loading time of the image tracking processing system is greatly shortened, and a guarantee is provided for quickly tracking and then hitting a target.
Description of the drawings:
FIG. 1 is a schematic diagram of a Tiger Sharc DSP program fast loading circuit;
FIG. 2 is a state diagram of FIFO write control;
FIG. 3 is a state diagram of FIFO read control.
The specific implementation mode is as follows:
the Tiger Sharc DSP fast loading method is successfully implemented in a certain image tracking processing system, wherein an ADSP company Tiger Sharc series ADSP-TS101 chip is used by a DSP, an XC2V3000 chip of an Xi l inx company is used by an FPGA, an SM29LV160 chip of a Shenzhen national micro company is used by a FLASH, 1.96Mbytes of program data are stored, and the LINK interface clock frequency is configured to be the LINK interface default frequency (250/8) MHz in the program.
The method comprises the following steps that program data stored in the FLASH are read by the FPGA through a DSP local bus, data caching is carried out inside the FPGA through FIFO, meanwhile, data are transmitted to a LINK interface of the DSP according to a LINK interface transmission protocol, and finally, loading of a DSP program is realized, and the method specifically comprises the following steps:
a) setting the BMS pin state of the Tiger Sharc DSP to be '1' in the FPGA, and configuring the DSP to be in a slave loading mode. Setting the state of an HBR pin to be '0' before the DSP finishes loading, and releasing the local bus right control right to the external equipment by the DSP; after the FPGA finishes reading FLASH data, setting the HBR pin state of the DSP to be '1', and returning the DSP local bus use right to the DSP;
b) and controlling a reset signal, a chip selection enabling signal, an output enabling signal and a write enabling signal of the FLASH in the FPGA. The reset signal of the FLASH is set to be in an active state during the DSP reset period, and is set to be in an inactive state after the DSP reset is finished; the chip selection enabling signal and the output enabling signal of the FLASH are set to be in an active state after the DSP is reset, and are set to be in an inactive state after the FLASH data is read; the FLASH writing signal is set to be in an invalid state; the FLASH read clock is a LINK interface clock which is 2 times of program data, namely (250/4) MHz;
c) opening an FIFO buffer area with the depth of 16 and the width of 8 in the FPGA to buffer the read-in FLASH data, wherein the FIFO read-write clock adopts 2 times of LINK interface clock, namely (250/4) MHz;
d) the FIFO write control is divided into 4 states, and the state is S0 when the FIFO write control is reset; after the reset is finished, the state of S1 is entered, the FIFO writing signal is set to be the effective state in the state of S1, whether the FIFO is full and the FLASH data is read completely is judged, when the FIFO is not full and the FLASH data is not read completely, the state of S1 is continued, when the FIFO is full, the state of S2 is skipped, and when the FLASH data is read completely, the state of S3 is skipped; setting the FIFO writing signal to be in an invalid state in the S2 state, judging the FIFO full state and the FLASH data state, jumping to the S1 state when the FIFO is not full and the FLASH data is not read, and otherwise, remaining in the S2 state; the FIFO write signal is set to be in an invalid state in the state of S3, and finally stops in the state of S3, and the state machine is ended;
e) the FIFO reading control is divided into 2 states, the state is S4 when the FIFO is empty or the LINK port is not allowed to transmit, the FIFO reading signal is set to be invalid in the state of S4, and the state jumps to the state of S5 when the reset is finished and the FIFO is not empty and the LINK port is allowed to transmit; setting the FIFO read signal to be in an effective state in the S5 state, jumping to the S4 state if the FIFO is empty or the LINK port is not allowed to transmit, and keeping in the S5 state if the FIFO is not empty or the LINK port is not allowed to transmit;
f) according to the LINK interface transmission time sequence in the ADSP-TS101 manual, LxCLKIN, LxCLKOUT, LxDAT and LxDIR signals are generated in the FPGA. The LxCLKOUT signal is a reference clock for LINK to send data, namely the clock frequency (250/8) MHz of a LINK interface configured in a FLASH program; the LxCLKIN signal is a response signal of a LINK receiving port of the DSP end, high indicates that data can be received, low indicates that data cannot be received, and the FPGA judges whether the LINK interface of the DSP end is allowed to send data or not by monitoring the signal; the LxDAT signal is data to be transmitted, and is read out from the FIFO buffer area by 8 bit data lines; the LxDIR signal represents the signal transmission direction, is set to be '1' in the FPGA, and represents that the FPGA is a sender;
the steps are executed in parallel in the FPGA, and the time for loading the program data with the size of 1.96Mbytes is 86 ms. When the system is used, the clock frequency of a LINK interface can be improved in a program, and the program loading time is further shortened.
Claims (1)
1. A Tiger Sharc DSP fast loading method is characterized in that an FPGA reads program data stored in a FLASH through a DSP local bus, data caching is carried out inside the FPGA through FIFO, and data are transmitted to a LINK interface of the DSP according to a LINK interface transmission protocol, so that DSP program loading is realized, and the method specifically comprises the following steps:
a) DSP loading and bus right control: setting the BMS pin state of the Tiger Sharc DSP to be '1' in the FPGA, and configuring the DSP as a slave loading mode; the acquisition and release of bus authority are realized by controlling the state of an HBR pin of the DSP in the FPGA; setting the state of an HBR pin to be '0' before the DSP finishes loading, and releasing the local bus right control right to the external equipment by the DSP; after the FPGA finishes reading FLASH data, setting the HBR pin state of the DSP to be '1', and returning the DSP local bus use right to the DSP;
b) FLASH reading control: controlling a reset signal, a chip selection enabling signal, an output enabling signal and a write enabling signal of the FLASH in the FPGA; the reset signal of the FLASH is set to be in an active state during the DSP reset period, and is set to be in an inactive state after the DSP reset is finished; the chip selection enabling signal and the output enabling signal of the FLASH are set to be in an active state after the DSP is reset, and are set to be in an inactive state after the FLASH data is read; the FLASH writing signal is set to be in an invalid state; the FLASH reading clock is a LINK interface clock which is 2 times;
c) FIFO write control: opening an FIFO buffer area with the depth of 16 and the width of 8 in the FPGA to buffer the read-in FLASH data, wherein the FIFO read-write clock adopts a LINK interface clock of 2 times; the FIFO write control is divided into 4 states, and the state is S0 when the FIFO write control is reset; after the reset is finished, the state of S1 is entered, the FIFO writing signal is set to be the effective state in the state of S1, whether the FIFO is full and the FLASH data is read completely is judged, when the FIFO is not full and the FLASH data is not read completely, the state of S1 is continued, when the FIFO is full, the state of S2 is skipped, and when the FLASH data is read completely, the state of S3 is skipped; setting the FIFO writing signal to be in an invalid state in the S2 state, judging the FIFO full state and the FLASH data state, jumping to the S1 state when the FIFO is not full and the FLASH data is not read, and otherwise, remaining in the S2 state; the FIFO write signal is set to be in an invalid state in the state of S3, and finally stops in the state of S3, and the state machine is ended;
d) FIFO read control: the FIFO reading control is divided into 2 states, the state is S4 when the FIFO is empty or the LINK port is not allowed to transmit, the FIFO reading signal is set to be invalid in the state of S4, and the state jumps to the state of S5 when the reset is finished and the FIFO is not empty and the LINK port is allowed to transmit; setting the FIFO read signal to be in an effective state in the S5 state, jumping to the S4 state if the FIFO is empty or the LINK port is not allowed to transmit, and keeping in the S5 state if the FIFO is not empty or the LINK port is not allowed to transmit;
e) and (3) LINK interface sending control: generating LxCLKIN, LxCLKOUT, LxDAT and LxDIR signals in the FPGA according to a LINK interface sending time sequence; the LxCLKOUT signal is a reference clock for LINK to send data; the LxCLKIN signal is a response signal of a LINK receiving port of the DSP end, high indicates that data can be received, low indicates that data cannot be received, and the FPGA judges whether the LINK interface of the DSP end is allowed to send data or not by monitoring the signal; the LxDAT signal is data to be transmitted, and is read out from the FIFO buffer area by 8 bit data lines; the LxDIR signal represents the signal transmission direction, is set to be '1' in the FPGA, and represents that the FPGA is a sender;
f) the steps a), b), c), d) and e) are all realized in the FPGA, and all the steps are executed in parallel.
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