JP6070600B2 - Microcomputer - Google Patents

Description

  The present invention relates to a microcomputer that includes a CPU capable of executing a test mode by switching an operation mode from the outside and stopping an operation being executed when a break request signal is input.

  A microcomputer (hereinafter referred to as a microcomputer) has a so-called on-chip debugging (hereinafter referred to as OCD) function, and is configured to be able to execute a test mode by switching the operation mode from the outside. is there. When executing the test mode, an OCD break function is required to connect the microcomputer to a debugger such as a personal computer so that communication is possible, and when the debugger issues a break request signal, the CPU stops the operation being executed. It becomes.

  In addition, since the microcomputer is constantly required to be low in cost and downsized, there is a circumstance that it is desired to minimize the number of inspection terminals that are unnecessary when operating in the normal mode as a product. For example, the technique disclosed in Patent Document 1 includes a test counter 31 in a semiconductor integrated circuit, counts a period during which the test signal T0 is asserted as a clock signal, and uses the test mode decoder 33 to calculate a final count value C0. By decoding, various test modes can be set. Further, the reset signal generation circuit 32 counts the length of the reset signal applied to the reset terminal of the microcomputer. When the count value is less than a predetermined value, the normal (user logic circuit 20) is reset, and when the count value is equal to or greater than the predetermined value. Resets the test counter 31.

JP 2005-274357 A

  However, Patent Document 1 does not assume that debugging is performed with a semiconductor integrated circuit connected to a debugger. When a specific test mode is set, a test is performed autonomously according to the mode. It has become. Therefore, it is not assumed that a break request issued by the debugger is accepted. Assuming that a break request is given by using a configuration that changes the type of signal to be applied according to the length of the reset signal, the CPU accepts the break supply when starting the microcomputer, and the start stops. End up.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a microcomputer capable of realizing operation mode switching, external communication, and break request signal input with as few terminals as possible. There is to do.

  According to the microcomputer of the first aspect, the microcomputer is used for switching the operation mode from the outside, and is used for communication between the outside and the CPU in the test mode for testing the circuit operation. A mode switching / communication terminal is provided. In addition, a normal operation mode is set in the initial state, and a test mode register is provided in which a test mode is set when a test mode write command is input by communication performed via a mode switching / communication terminal.

The counter is connected to the mode switching / communication terminal and continues counting while the level of the terminal is maintained active. The first comparator determines that the counter value of the counter is the time required for the communication. A break request signal is output to the CPU if it is greater than or equal to the first threshold set longer than the first threshold and less than the second threshold set greater than the first threshold . The second comparator, the counter value becomes equal to or larger than the second threshold value, outputs a signal for setting the normal operation mode to disable the test mode. If comprised in this way, switching of an operation mode, communication with the exterior, and the input of a break request signal can be performed using one mode switching / communication terminal.

The functional block diagram which is 1st Embodiment and shows about the part which concerns on the structure of a microcomputer (A) is a debug communication, (b) is an OCD break request, and (c) is a timing chart showing a signal form corresponding to mode management. Timing chart showing counter register operation when mode / communication terminal is fixed at low level Diagram showing the processing sequence between the debugger and the microcomputer when debugging the microcomputer with the debugger FIG. 1 equivalent view showing the second embodiment

(First embodiment)
As shown in FIG. 1, in a microcomputer 1, a CPU 2, a ROM 3, a RAM 4, peripheral circuits 5 </ b> A and 5 </ b> B are connected to each other via an address bus 6 and a data bus 7. A bus control switching circuit 8 is inserted in the address bus 6 and the data bus 7, and a mode / communication circuit 9 is connected via the bus control switching circuit 8. The mode / communication circuit 9 is connected via a bidirectional I / O circuit 10 to a mode / communication terminal 11 (mode switching / communication terminal) that is an external terminal of the microcomputer 1.

  The mode / communication terminal 11 is used to switch and set the operation mode of the microcomputer 1 from the outside. When the test mode is set as the operation mode, for example, a debugger (not shown) such as a personal computer is connected. And used for serial communication with the CPU 2. The mode / communication circuit 9 is a circuit for realizing the OCD function of the microcomputer 1 through the above communication.

  The bidirectional I / O circuit 10 is connected to a communication interface (I / F) unit 12 of the mode / communication circuit 9. The communication I / F unit 12 performs signal reception and transmission with the bidirectional I / O circuit 10 by 1-wire (serial) communication. The signal received by the communication I / F unit 12 Is decoded by the reception decoder 13 and an OCD command is issued. In addition, when command response data output from the CPU 2 is input, the transmission frame generation unit 14 of the communication I / F unit 12 generates a transmission frame including the data and transmits the transmission frame to the bidirectional I / O circuit 10.

  The OCD command is input to the OCD command I / F unit 15 where an address and data corresponding to the command are generated and output to the bus control switching circuit 8. The OCD command I / F unit 15 outputs a signal for selecting the bus control state of the bus control switching circuit 8 in accordance with the input OCD command. The bus control switching circuit 8 disconnects the mode / communication circuit 9 when the microcomputer 1 is set to the normal mode (normal operation mode), and the CPU 2 performs the ROM 3 and RAM 4 via the address bus 6 and the data bus 7 as usual. The peripheral circuit 5 is controlled to be accessible.

  On the other hand, when the microcomputer 1 is set to the test mode, the bus control switching circuit 8 performs control so that the CPU 2 can receive the command issued via the OCD command I / F unit 15. For example, the command is stored in an OCD command buffer provided in the peripheral circuit 5A, and the CPU 2 accesses the peripheral circuit 5A and acquires the OCD command. In addition, an OCD command buffer may be provided inside the bus control switching circuit 8.

  In the test mode, the data transmitted by the CPU 2 to the external debugger in response to the given OCD command is transmitted from the communication I / F unit 12 via the bus control switching circuit 8 and the OCD command I / F unit 15. Input to the generation unit 14. This enables bidirectional communication between the external debugger and the CPU 2 of the microcomputer 1.

  The OCD command is also input to the test mode register 16. The test mode register 16 outputs the normal mode setting signal in the reset initial state, and outputs the test mode setting signal when the test mode setting is instructed by the OCD command. These mode setting signals are output to the peripheral circuits 5A and 5B, for example, via the test mode invalidating unit 17.

  The output terminal of the bidirectional I / O circuit 10 is also connected to the input terminal of the counter register 18, and the counter register 18 counts a period during which the output terminal is in an active (for example, low) level. The value is output to the first comparator 19 and the second comparator 20. Although not shown, each circuit of the mode / communication circuit 9 operates in clock synchronization with a common internal clock signal. The test mode register 16 and the counter register 18 are supplied with a reset signal (of the microcomputer 1).

  The first comparator 19 detects a break request when the count value of the counter register 18 becomes equal to or greater than the threshold value Y, and outputs the OCD break request to the CPU 2 via the OCD break invalidation unit 21. The second comparator 20 detects a normal mode setting request when the count value of the counter register 18 is equal to or greater than the threshold value Z, and outputs a test mode invalidation signal to the test mode invalidation unit 17. The normal mode setting signal output from the mode invalidation unit 17 is also input to the OCD command I / F unit 15 and the OCD break invalidation unit 21. When the test mode invalidation signal is output while the test mode register 16 is outputting the test mode setting signal, the test mode setting signal is invalidated and the normal mode setting signal is validated.

  Here, as shown in FIG. 2, the signal control via the mode / communication terminal 11 has three patterns. In the debug communication of (a), when switching from the high level to the low level, it becomes a start bit (Start Of Flame), and subsequently, a plurality of data bits are indicated by a binary level change of high / low. Finally, a high-level end bit (End Of Flame) is arranged, and that is one frame of communication. The communication frame length is set to be less than the count value X of the counter register 18.

  The OCD break request in (b) is set so that the low level period is not less than the count value Y (> X, first threshold) and less than Z. The mode management (normal mode setting) in (c) is set so that the low level period is equal to or greater than the count value Z (second threshold). The OCD break request is valid only when the microcomputer 1 is operating in the test mode.

  That is, the external debugger can give different meanings to the signal applied to the microcomputer 1 by controlling the signal applied to the mode / communication terminal 11 as described above. As a specific numerical example, the time required for debug communication in (a) is about several μs, the time for enabling the OCD break request in (b) is about several tens of μs, and the time for enabling normal mode setting in (c). Is about several thousand μs.

  The mode / communication terminal 11 is fixed at a low level to set the normal mode when the microcomputer 1 is used as a product in the field. At this time, the timing at which the counter register 19 starts the count operation is from the time when the reset of the microcomputer 1 is released (see FIG. 3).

  Next, the operation of this embodiment will be described. As shown in FIG. 4, when debugging the microcomputer 1, the debugger is started externally and evaluation of the microcomputer 1 is started (D1). First, debug communication is performed via the mode / communication terminal 11 to issue a write command (test mode setting) to the test mode register 16 (D2). Then, the microcomputer 1 side receives the received command, writes to the test mode register 16, and sets the test mode (M1).

  Subsequently, the debugger issues a control command for the CPU bus (address bus 6 and data bus 7) through debug communication, and further issues a command for causing the CPU 2 to execute a software reset (D3). Then, the microcomputer 1 receives the received command, executes software reset, initializes the CPU 2, and restarts execution of software (M2).

  Thereafter, the debugger issues a control command for the CPU bus and issues a command for evaluation (D4), as in step D3. Then, the microcomputer 1 reads out circuit information of the circuit connected to the CPU bus, the peripheral circuit 5 and the RAM 4 according to the received command, and transmits the read information as “command response data” to the outside (debugger). (M3). “Circuit information” is, for example, a flag or data stored in the RAM 4.

  Then, after repeatedly executing steps D3 → M3 according to the contents of the evaluation, when the debugger issues an OCD break request (D5), the CPU 2 of the microcomputer 1 accepts the OCD break request and communicates at that time. If it is being executed, the communication being transferred is stopped (M4). Then, debugging and evaluation of the microcomputer 1 are finished (D6).

  As described above, according to the present embodiment, the microcomputer 1 is used for switching the operation mode from the outside, and the outside and the CPU 2 communicate with each other in the test mode for testing the circuit operation. The mode / communication terminal 11 used in the above is provided. In addition, a normal mode is set in an initial state, and a test mode register 15 is provided which sets a test mode when a test mode write command is input by communication performed via the mode / communication terminal 11.

The counter register 18 is connected to the mode / communication terminal 11 and continues the counting operation while the level of the terminal is kept active. The first comparator 19 indicates that the counter value of the counter register 18 A break request signal is output to the CPU 2 if it is greater than or equal to the first threshold Y set longer than the time required for communication and less than the second threshold Z set larger than the first threshold Y. Further, when the counter value is equal to or greater than the second threshold value Z, the second comparator 20 outputs a signal for invalidating the test mode and setting the normal mode. With this configuration, it is possible to switch the operation mode, communicate with the outside, and input a break request signal using one mode / communication terminal 11. Therefore, the microcomputer 1 can be configured in a small size.

(Second Embodiment)
Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different parts will be described. As shown in FIG. 5, the microcomputer 31 of the second embodiment deletes the test mode invalidation unit 17 in the microcomputer 1 of the first embodiment, and uses the test mode register to output the normal mode detection signal output from the second comparator 20. 32. Then, the test mode register 32 is reset when a normal mode detection signal is given, and stops outputting the test mode setting signal and outputs a normal mode detection signal if the test mode setting signal is being output.

  As described above, according to the second embodiment, since the second comparator 20 outputs a signal for resetting the test mode register 32 and invalidates the test mode, the same effect as the first embodiment can be obtained. .

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
The configuration and type of peripheral circuits connected to the address bus 6 and the data bus 7 are arbitrary.
The software executed by the CPU 2 in step M2 may be a test program prepared separately from the application program.

  In the drawings, 1 is a microcomputer, 2 is a CPU, 9 is a mode / communication circuit, 11 is a mode / communication terminal (mode switching / communication terminal), 16 is a test mode register, 18 is a counter register, and 19 is a first comparison. 20 represents a second comparator.

Claims (2)

When the break request signal is input, the CPU (2) that stops the operation being executed;
A mode switching / communication terminal (11) used for switching the operation mode from the outside and used for communication between the CPU and the outside in a test mode for testing the circuit operation ,
A counter (18) connected to the mode switching / communication terminal and continuing the counting operation while the level of the terminal is maintained active;
A normal operation mode is set in the initial state, and a test mode register (16, 32) that sets a test mode when a test mode write command is input by communication performed via the mode switching / communication terminal. )When,
Count value of the counter is, at the least the first threshold value is set longer than the time required for communication, the you output a break request signal if and second less than a threshold value is set larger than the first threshold value A first comparator (19);
Count value of the counter becomes equal to or larger than before Symbol second threshold, further comprising a second comparator for outputting a signal for setting the normal operation mode to disable the test mode (20) A featured microcomputer.   The microcomputer according to claim 1, wherein the second comparator (20) outputs a signal for resetting the test mode register (32) to invalidate the test mode.

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