JP2008033657A - Memory control device, information processor and memory control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control device, capable of efficiently executing enable write processing without key specification processing for calculating a key from writing data. <P>SOLUTION: A memory controller 12 executes processing for transmitting a write mask command for designating a key showing a specific first value (e.g., ffh) to a memory device 13 and processing for transmitting writing data to the memory device 13 after substituting the value of each invalid byte part contained in the writing data by ffh. The memory controller 12 then executes processing for transmitting a write mask command for designating a key showing a specific second value (e.g., 01h) to the memory device 13 and processing for substituting the value of each other byte part except valid byte parts the value of which is ffh in the writing data by 01h and transmitting the resulting writing data to the memory device 13. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory control device for executing a write mask writing process, an information processing device including the memory control device, and a memory control method.

  Conventionally, when a memory is controlled via a bus without a byte enable definition, for example, an enable write for rewriting only a specific byte portion is executed by the following method.

(1) Read-modify-write Read-modify-write is a method that once reads all data of the processing bit width from the memory device, rewrites the value of only the byte part to be written, and then writes again. In this method, it is necessary to read data once. When the data bus is half-duplex, a turnaround time for switching the direction is required, and the access time is increased.

(2) Write mask The write mask is a method for executing enable write using a write mask command including a key called a write mask key. The write circuit in the memory device has a comparator for each byte, and the key value is compared with the value of each byte part in the write data, and writing of the byte part that matches the key value is prohibited. Is done. Enable write can be executed more efficiently than when read-modify-write is used. Non-Patent Document 1 discloses a memory that supports the above-described write mask.
“512Mbit XDRTMDRAM (C-die) 4M x 16 (/ 8/4/2) bit x 8s Bank”, [online], [searched July 21, 2006], Internet <URL: http: // WWW. samsung.com/Products/Semiconductor/XDR_RDRAM/XDRDRAM/Component/512Mbit/K4Y50044UC/ds_k4y50xx4uc_rev03.pdf>

  However, when executing the enable write using the write mask described above, the controller side uses the value of the key from the write data in order to use a value that does not match any valid byte part in the write data as the key. It is necessary to perform a key specifying process of calculating.

  For example, when the key is composed of 8 bits, there are 256 patterns that can be represented by the key. Therefore, in the key specifying process, the write data of each valid byte part is decoded and each write data of the valid byte part is decoded. It is necessary to check the pattern and detect a pattern that is not used in any valid byte part from 256 patterns. Therefore, there arises a problem that a circuit in the controller is enlarged for the key specifying process.

  The present invention has been made in consideration of the above circumstances, and a memory control device and information processing capable of efficiently executing enable write processing without performing key specification processing of calculating a key from write data An object is to provide an apparatus and a memory control method.

  In order to solve the above-described problem, the present invention writes a byte portion that matches the key value by comparing the value of the key specified by the write mask command with the value of each byte portion in the write data. A memory control apparatus for controlling a memory device having a write mask function for prohibiting the write device, comprising: processing for transmitting a write mask command designating a key having a specific first value to the memory device; and write data A first write mask write cycle including: processing of transmitting the write data to the memory device after replacing a value of an invalid byte portion that should be prohibited from being written in the plurality of byte portions with the specific first value. A means for executing and a write mask command designating a key having a specific second value to said memory device. And a value of each byte part other than a valid byte part that is a valid byte part to be written and has the specific first value among a plurality of byte parts constituting the write data. Means for executing a second write mask write cycle including a process of transmitting the write data to the memory device after the replacement with the specific second value.

  According to the present invention, it is possible to efficiently execute the enable write process without performing the key specifying process of calculating the key from the write data.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration example of an information processing apparatus using a memory control apparatus according to an embodiment of the present invention. This information processing apparatus is realized as an embedded system incorporated in various computers such as personal computers, workstations, and server computers, or electronic devices such as AV equipment, and includes a processor 11, a memory controller 12, and a memory device. 13 and other various I / O devices (not shown).

  The processor 11 is a central processing unit (CPU) that controls the operation of the information processing apparatus, and executes various data processing using the memory device 13 that functions as a main memory. The memory controller 12 is a memory control device according to the present embodiment, controls the memory device 13 in response to a request from the processor 11, and performs read access for reading data from the memory device 13 and data to the memory device 13. A write access for writing is executed.

  The memory controller 12 is connected to the memory device 13 via a bus such as a serial bus in which no byte enable signal line is defined. In FIG. 1, the memory controller 12 and the memory device 13 are connected via a command transmission bus called an RQ bus and a data transmission / reception bus called a DQ bus. It is shown. Each of the RQ bus and the DQ bus is a serial bus. Each of the RQ bus and the DQ bus is composed of a plurality of sets, for example, 16 differential signal line pairs.

  The memory device 13 is a memory device that supports the write mask command, and compares the key value specified by the write mask command with the value of each byte part in the write data to match the key value. It has a write mask function that prohibits the writing of parts.

  When executing an enable write for rewriting only a specific byte part, the memory controller 12 is configured to continuously execute two write mask write cycles using two consecutive write mask commands. ing. In this case, in each write mask write cycle, a key indicating a predetermined specific value is used instead of a key calculated from write data. In the following, it is assumed that the write data is composed of, for example, 32-byte block data and the key is composed of, for example, 8 bits.

  In the first write mask write cycle, the memory controller 12 transmits a write mask command designating a key indicating a specific first value (for example, ffh) to the memory device 13 via the RQ bus, and 32 After replacing the value of each invalid byte part included in the write data composed of bytes with a specific first value (for example, ffh), the 32-byte write data is transferred to the memory device 13 via the DQ bus by burst transfer. The process to send is executed. In the memory device 13, writing of each byte part having a value of ffh is prohibited, and only writing of a byte part having another value is executed. The write position of each byte part is specified by an address included in the write mask command.

  In the first write mask write cycle, not only the invalid byte part but also the valid byte part having a specific first value is masked. For this reason, the second write mask write cycle is executed in order to execute the writing of the effective byte portion having the specific first value.

  In the second write mask write cycle, the memory controller 12 stores a write mask command for designating a key indicating a specific second value (for example, 01h) different from the first value, via the RQ bus. Among the 32 bytes constituting the processing to be transmitted to the device 13 and the write data, the value of each byte part other than the valid byte part having a specific first value is set to a specific first value (for example, 01h). And the process of transmitting the 32-byte write data to the memory device 13 via the DQ bus by burst transfer. By this second write mask write cycle, it is possible to execute writing of the valid byte part having the specific first value masked in the first write mask write cycle.

  As described above, in this embodiment, since a key indicating a predetermined specific value is used instead of a key calculated from write data, a mask write command is performed without performing a key specifying process that causes an increase in circuit scale. Enable write using can be executed.

  The second write mask write cycle only needs to be executed when there is a valid byte portion having a specific first value in the write data, and there is a valid byte portion having a specific first value. If not, the execution of the second write mask write cycle can be omitted.

  FIG. 2 shows another configuration example of the information processing apparatus using the memory control apparatus according to the present embodiment.

  In FIG. 2, the memory controller 12 is built in the processor 11 as a memory interface, and controls access to the memory device 13 in response to a request from the core in the processor 11. The other points are the same as in FIG.

  FIG. 3 shows a configuration example of a write circuit unit provided in the memory device 13.

  In order to execute the above-described write mask function, the memory device 13 is provided with a comparison circuit 21 and an AND gate circuit 22 for each memory cell group for one byte.

  Each comparison circuit 21 compares the 8-bit key value with the corresponding 8-bit data in the byte part. Only when there is a mismatch, a write enable signal is sent to the corresponding memory cell group. As a result, writing of the byte part including the data matching the key value is prohibited, and only writing of the non-matching byte part is executed.

  FIG. 4 is a timing chart of the enable write process of this embodiment.

  First, the memory controller 12 issues a first write mask command (Write Mask). This write mask command (Write Mask) includes, for example, an 8-bit key having a value of ffh. This write mask command is a command for instructing writing other than the byte portion that matches the key value included in the write mask command. The write mask command also includes address data that designates the write position of the write data.

  Thereafter, the memory controller 12 transmits 32-byte write data (WData). In the 32-byte write data, the value of the invalid byte portion that should be prohibited from being written is replaced with ffh. In the memory device 13, each byte part in the 32-byte write data is compared with ffh, and only the byte part having a value other than ffh is written.

  Thereafter, the memory controller 12 issues a second write mask command (Write Mask). The write mask command (Write Mask) includes, for example, an 8-bit key having a value of 01h. Then, the memory controller 12 transmits 32-byte write data (WData). In this 32-byte write data, the value of each byte part other than the valid byte part having a value of ffh is replaced with 01h. In the memory device 13, each byte part in the 32-byte write data is compared with ffh, and the byte part having a value other than 01h, that is, the ffh byte part is written.

  When the second write mask write cycle, that is, the second write mask command (Write Mask) is issued and the subsequent write data is transmitted, it is detected that the valid byte portion having the value of ffh exists in the write data. Only executed. If there is no valid byte portion having a value of ffh in the write data, the second write mask write cycle is not executed. Even if there is no valid byte part having a value of ffh in the write data, for example, the second write mask write cycle is executed using the write data in which all the byte parts are replaced with 01h. It is also possible.

  FIG. 5 shows an example of key values and write data used in the first write mask write cycle.

  The write data (WData) is composed of 32-byte block data from the first byte part B1 to the 32nd byte part B32. Assume that the byte part B10 is an invalid byte part that should be prohibited from being written and the other byte parts are valid byte parts that should be written.

  Validity / invalidity of each byte part of the write data is designated by the processor 11. The value (8-bit data) of the byte part B10, which is an invalid byte part, is replaced with ffh by the memory controller 12.

  If the value of the valid byte part B2 is ffh, not only writing of the invalid byte part B10 is masked but also writing of the valid byte part B2 is masked.

  FIG. 6 shows an example of key values and write data used in the second write mask write cycle. The values of the byte parts B1, B3 to B32 other than the valid byte part B2 whose value is ffh are replaced with 01h by the memory controller 12. Therefore, only writing of the valid byte part B2 is executed, and writing of the other byte parts B1, B3 to B32 is masked.

  Next, an example of a functional configuration of the memory controller 12 will be described with reference to FIG.

  In FIG. 7, write data from the processor 11 is represented as UWDAT, and write data transmitted from the memory controller 12 to the memory device 13 is represented as WDATA.

  The memory controller 12 includes a first cycle execution unit 21, a second cycle execution unit 22, and a determination unit 23.

  The first cycle execution unit 21 executes the first write mask write cycle (first write mask write cycle) using the write mask command including the key indicating the fixed value ffh. In this case, the value of each invalid byte part included in the write data UWDAT is replaced with ffh, and the write data UWDAT after this replacement is transmitted to the memory device 13 as the write data WDATA.

  The determination unit 23 determines whether or not there is a valid byte part having a value of ffh in the write data UWDAT. When it is determined that the valid byte part of ffh is present in the write data UWDAT, the second cycle execution part 22 uses the write mask command including the key indicating the fixed value 01h, and the second write mask described above. A write cycle (second write mask write cycle) is executed. In this case, the value of each byte part other than the valid byte part having the value ffh included in the write data UWDAT is replaced with 01h, and the write data UWDAT after this replacement is transmitted to the memory device 13 as the write data WDATA.

  Next, the difference between the enable write process of the present embodiment and the conventional enable write process will be described with reference to the timing charts of FIGS.

  FIG. 8 shows a timing chart of the read modify write. As described above, in read-modify-write, it is necessary to rewrite a part of the read data after executing the read cycle, and then execute the write cycle, and further, a waiting time for turnaround is required. Therefore, as shown in FIG. 8, it takes a long time to complete the enable write process.

  FIG. 9 shows a timing chart of a conventional light mask. In the conventional write mask, the enable write process can always be completed with only one write cycle, so the enable write process can be executed more efficiently than the read-modify-write, but the key is calculated from the write data. It is necessary to provide a circuit for the key specifying process, which causes a significant increase in the circuit scale of the memory controller.

  On the other hand, in the present embodiment, the enable write process can be executed at a speed higher than that of the read-modify-write, and unlike the conventional write mask, the key specifying process is unnecessary, resulting in an increase in circuit scale. Instead, the enable write process using the write mask command can be executed.

  Next, an example of a specific circuit configuration provided in the memory controller 12 will be described with reference to FIG.

  The memory controller 12 includes a write data # 1 output circuit 31, a write data # 1 output circuit 32, a selector (SEL) 33, a 32-bit NAND gate 34, and the like in order to execute enable write processing.

  The write data # 1 output circuit 31 is a circuit for outputting write data to be output in the first write mask write cycle. Based on the byte enable signal BE [31: 0] from the processor 11, 32-byte write data is output. The invalid byte part in UDATA [255: 0] is detected, and the value of the invalid byte part is replaced with ffh.

  The write data # 2 output circuit 32 is a circuit that outputs write data to be output in the second write mask write cycle. In the write data # 2 output circuit 32, as shown in the figure, a selector (SEL) 41 and a 9-bit NAND gate 42 are provided for each byte portion of write data.

  Each 9-bit NAND gate 42 outputs an output signal of logic “0” when the corresponding byte part is valid (BE = 1) and the value of the corresponding byte part is ffh, and otherwise. Outputs an output signal of logic “1”. Each selector (SEL) 41 selects 01h when the output signal of the corresponding 9-bit NAND gate 42 is logic “0”, and the output signal of the corresponding 9-bit NAND gate 42 is logic “1”. In this case, the data of the corresponding byte part in the write data UWDATA [255: 0] is selected.

  The selector (SEL) 33 selects the write data obtained by the write data # 1 output circuit 31 as the write data WDATA [255: 0] in the first write mask write cycle according to the timing signal SecWrite, and selects the memory device 13. In the second write mask write cycle, the write data MWDATA [255: 0] obtained by the write data # 2 output circuit 32 is selected as the write data WDATA [255: 0] and transmitted to the memory device 13. To do.

  In the 32-bit NAND gate 34, when the output signal from any one of the 32 9-bit NAND gates 42 is "0", that is, the effective byte portion of ffh is 1 in the write data WDATA [255: 0]. If more than one are included, a logic “1” signal (WriteFFhneed) indicating that the execution of the second write mask write cycle is necessary is output. When all the output signals of the 32 9-bit NAND gates 42 are “1”, the WriteFFhneed signal is logic “0”, and the execution of the second write mask write cycle is omitted.

  Next, the procedure of the write control process executed by the memory controller 12 will be described with reference to the flowchart of FIG.

  This write control process is executed when an enable write is necessary, for example, when the memory controller 12 receives write data including an invalid byte portion from the processor 11. Whether or not the write data includes an invalid byte portion can be determined by a byte enable signal BE [31: 0] from the processor 11.

  First, the memory controller 12 transmits a write mask command including ffh as a key to the memory device 13 via the RQ bus (step S101), and an invalid byte portion in the 32 bytes constituting the write data from the processor 11 Is replaced with ffh, and the write data subjected to the replacement is transmitted to the memory device 13 via the DQ bus (step S102).

  Next, the memory controller 12 determines whether or not the write data from the processor 11 includes a valid byte part having a value of ffh (step S103).

  If the write data includes a valid byte part having a value of ffh (NO in step S103), the memory controller 12 performs a write mask including O1h as a key in order to write the valid byte part of ffh. The command is transmitted to the memory device 13 via the RQ bus (step S104), and the value of each byte part other than the valid byte part of ffh is replaced with 01h in the 32 bytes constituting the write data from the processor 11. The write data subjected to the replacement is transmitted to the memory device 13 via the DQ bus (step S105).

  On the other hand, if the write data does not include a valid byte part having a value of ffh (NO in step S103), the execution of steps S104 and S105 is omitted, and the write control process for the enable write ends at this point. To do.

  As described above, according to the present embodiment, the enable write is executed using two consecutive write mask write cycles. Therefore, in each write mask write cycle, not the value calculated from the write data, A specific value determined in advance can be used as a key, and the circuit scale can be greatly reduced as compared with a conventional write mask method that requires a key specifying process.

  Further, since a function for omitting the execution of the second write mask write cycle is provided, there is no byte portion having the same value as the key used in the first write mask write cycle in the write data. In this case, the enable write process can be completed with only one write mask write cycle.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine a component suitably in different embodiment.

1 is a block diagram illustrating a configuration example of an information processing apparatus according to an embodiment of the present invention. The block diagram which shows the other structural example of the information processing apparatus of the embodiment. FIG. 3 is a circuit diagram showing an example of a write circuit in a memory device used in the information processing apparatus of the embodiment. 6 is a timing chart showing enable write processing executed by a memory control device provided in the information processing apparatus of the embodiment. The figure for demonstrating the 1st write cycle performed by the memory control apparatus provided in the information processing apparatus of the embodiment. The figure for demonstrating the 2nd write cycle performed by the memory control apparatus provided in the information processing apparatus of the embodiment. FIG. 3 is an exemplary block diagram for explaining a functional configuration of a memory control device provided in the information processing apparatus of the embodiment. The timing chart which shows a normal read modify write process. The timing chart which shows a normal mask write process. FIG. 3 is a circuit diagram showing a configuration example of a memory control device provided in the information processing apparatus of the embodiment. 6 is an exemplary flowchart illustrating the procedure of a write control process which is executed by the memory control device provided in the information processing apparatus of the embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Processor, 12 ... Memory controller, 13 ... Memory device, 21 ... 1st cycle execution part, 22 ... 2nd cycle execution part, 23 ... Determination part, 31 ... Write data # 1 output circuit, 32 ... Write data # 2 Output circuit 33... Selector, 34... 32 bit NAND gate.

Claims (10)

Controls a memory device that has a write mask function that prohibits writing of the byte part that matches the key value by comparing the value of the key specified by the write mask command with the value of the individual byte part in the write data. A memory control device,
A process of transmitting a write mask command designating a key having a specific first value to the memory device, and a value of an invalid byte portion that should be prohibited from being written among a plurality of byte portions constituting write data. Means for executing a first write mask write cycle comprising: processing for transmitting the write data to the memory device after replacing with a first value;
A process of transmitting a write mask command designating a key having a specific second value to the memory device, and a valid byte part to be written among a plurality of byte parts constituting the write data, and A process of transmitting the write data to the memory device after replacing the value of each byte part other than the valid byte part having a specific first value with the specific second value. A memory control device comprising: means for executing a mask write cycle.   It is determined whether or not there is an effective byte portion having the specific first value in the write data, and when there is no effective byte portion having the specific first value, the second write mask write 2. The memory control device according to claim 1, further comprising means for omitting execution of a cycle.   2. The memory control device according to claim 1, wherein the memory control device is connected to the memory device via a bus in which a byte enable signal line is not defined. Controls a memory device that has a write mask function that prohibits writing of the byte part that matches the key value by comparing the value of the key specified by the write mask command with the value of the individual byte part in the write data. A memory control device,
A process of transmitting a write mask command designating a key having a specific first value to the memory device, and a value of an invalid byte portion that should be prohibited from being written among a plurality of byte portions constituting write data. Means for executing a first write mask write cycle comprising: processing to transmit the write data to the memory device after replacing with a first value;
Means for determining whether or not there is a valid byte part having the specific first value in the write data;
A process of transmitting a write mask command designating a key having a specific second value to the memory device when a valid byte portion having the specific first value exists, and included in the write data, A second write mask write including: processing to transmit the write data to the memory device after replacing each byte portion other than the valid byte portion having the specific first value with the specific second value A memory control device comprising: means for executing a cycle. A processor;
A memory device having a write mask function that prohibits writing of the byte portion that matches the key value by comparing the value of the key specified by the write mask command with the value of the individual byte portion in the write data;
Memory control means for controlling the memory device in response to a request from the processor, comprising processing for transmitting a write mask command designating a key having a specific first value to the memory device, and write data A first write mask write cycle including: a process of transmitting the write data to the memory device after replacing a value of an invalid byte part that should be prohibited from writing in the plurality of byte parts with the specific first value , A process of transmitting a write mask command designating a key having a specific second value to the memory device, and a valid byte to be written in a plurality of bytes constituting the write data And the value of each byte part other than the valid byte part having the specific first value is the specific second value. The information processing apparatus characterized by comprising a memory control means including means for executing a second write mask write cycle including a process of transmitting the write data after replacing the value in the memory device.   It is determined whether or not there is an effective byte portion having the specific first value in the write data, and when there is no effective byte portion having the specific first value, the second write mask write 6. The information processing apparatus according to claim 5, further comprising means for omitting execution of a cycle. A processor;
A memory device having a write mask function that prohibits writing of the byte portion that matches the key value by comparing the value of the key specified by the write mask command with the value of the individual byte portion in the write data;
Memory control means for controlling the memory device in response to a request from the processor, comprising processing for transmitting a write mask command designating a key having a specific first value to the memory device, and write data A first write mask write cycle including: a process of transmitting the write data to the memory device after replacing a value of an invalid byte part that should be prohibited from writing in the plurality of byte parts with the specific first value A means for determining whether or not there is a valid byte part having the specific first value in the write data, and a valid byte part having the specific first value exists. A process of transmitting a write mask command designating a key having a specific second value to the memory device, and including in the write data And a process of transmitting the write data to the memory device after replacing each byte portion other than the valid byte portion having the specific first value with the specific second value. An information processing apparatus comprising: memory control means including means for executing a write mask write cycle. Controls a memory device that has a write mask function that prohibits writing of the byte part that matches the key value by comparing the value of the key specified by the write mask command with the value of the individual byte part in the write data A memory control method,
A process of transmitting a write mask command designating a key having a specific first value to the memory device, and a value of an invalid byte portion that should be prohibited from being written among a plurality of byte portions constituting write data. Performing a first write mask write cycle including processing to transmit the write data to the memory device after replacing with a first value;
A process of transmitting a write mask command designating a key having a specific second value to the memory device, and a valid byte part to be written among a plurality of byte parts constituting the write data, and A process of transmitting the write data to the memory device after replacing the value of each byte part other than the valid byte part having a specific first value with the specific second value. And a step of executing a mask write cycle.   It is determined whether or not there is an effective byte portion having the specific first value in the write data, and when there is no effective byte portion having the specific first value, the second write mask write The memory control method according to claim 8, further comprising a step of omitting execution of the cycle. Controls a memory device that has a write mask function that prohibits writing of the byte part that matches the key value by comparing the value of the key specified by the write mask command with the value of the individual byte part in the write data A memory control method,
A process of transmitting a write mask command designating a key having a specific first value to the memory device, and a value of an invalid byte portion that should be prohibited from being written among a plurality of byte portions constituting write data. Performing a first write mask write cycle including processing to transmit the write data to the memory device after replacing with a first value;
Determining whether there is a valid byte part having the specific first value in the write data;
A process of transmitting a write mask command designating a key having a specific second value to the memory device when a valid byte portion having the specific first value exists, and included in the write data, A second write mask write including: processing to transmit the write data to the memory device after replacing each byte portion other than the valid byte portion having the specific first value with the specific second value And a step of executing a cycle.

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