TWI581103B - Method and system for implementing bus operations with precise timing - Google Patents
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Description
本發明係關於嵌入式系統的領域,且更具體而言係關於在一種嵌入式系統內的匯流排操作(暫存器與記憶體的讀取與寫入)。 The present invention relates to the field of embedded systems and, more particularly, to bus operations (storage and memory read and write) within an embedded system.
在一嵌入式控制系統中,複數個要求指令可授權某些動作發生以回應於事件。某些要求指令係即時的;也就是說,回應必須發生於初始事件後的定義明確之時間。 In an embedded control system, a plurality of request instructions may authorize certain actions to occur in response to an event. Some requirements are immediate; that is, the response must occur at a well-defined time after the initial event.
另一常見的功能係為嵌入式控制器支援,其係透過通訊與一或多個裝置交換資訊。協定通常以脈衝邊緣的方式被明確界定,且允許少量的干擾。許多通訊協定,例如飛利浦的I2C,其係直接支援硬體。然而,當設計該硬體時,一種嵌入式控制器可能被要求來支援未預料到的一協定。一種用於解決此問題的方法被稱為「位元脈衝」,其中該控制器直接切換用於每個傳送位元或位元組的接腳。 Another common feature is embedded controller support, which exchanges information with one or more devices via communication. Agreements are usually well defined in the form of pulse edges and allow for small amounts of interference. Many communication protocols, such as Philips' I2C, directly support hardware. However, when designing the hardware, an embedded controller may be required to support an unanticipated agreement. One method for solving this problem is called "bit pulse" where the controller directly switches the pins for each transfer bit or byte.
對於處理那些沒有在設計設備時已知的事件之傳統解決方案係採用一種嵌入式控制器(或一種處理器)。該處理器,採用一個程式(裝置韌體的部分),能檢查輸入且決定如何回應於一改變的刺激輸入或事件。此方法非常靈活,尤其是如果用於該嵌入式控制器的韌體能被修正時。然而,存在一定數量的限制,如下所述。 A conventional solution (or a processor) is used for traditional solutions that deal with events that are not known at the time of designing the device. The processor, using a program (part of the device firmware), can check the input and decide how to respond to a changed stimulus input or event. This method is very flexible, especially if the firmware for the embedded controller can be modified. However, there are a number of limitations, as described below.
通常,處理器在輸入與輸出訊號上具有執行多樣且複 雜的操作之能力,但是這些能力依據成本而獲得。如果該回應必須要及時的話,該處理器將很可能要求一個中斷,該中斷係指示其所關注的一個事件。這些中斷能消耗相當多的時間,且因此該處理器回應也可能會發生。另外處理中斷能要求許多處理器循環,其係意指該處理器不能工作在其他功能上,同時回應於事件。另一個限制係為使用一處理器來執行一簡單回應會要求相當多的電力,除了指令與資料記憶器以外,同時該處理器可要求上千個閘極,來處理要求該反映的指示。 Usually, the processor has multiple implementations on the input and output signals. The ability to perform operations, but these capabilities are based on cost. If the response must be timely, the processor will most likely request an interrupt indicating an event of interest to it. These interrupts can consume a significant amount of time, and therefore the processor response can also occur. In addition, processing interrupts can require many processor cycles, which means that the processor cannot operate on other functions while responding to events. Another limitation is that using a processor to perform a simple response would require considerable power, in addition to the instruction and data memory, while the processor can require thousands of gates to process the indications that require the reflection.
進一步,使用「位元脈衝」來實施一通訊協定可能會由於許多原因而令人不滿意。該處理器可能還沒快到能以所要求的比率來切換位元,或在同時執行其他所要求的任務時,可能缺乏充分的能力來進行。因為在該處理器的負載可能隨時間變化,如果不是不可能,對於韌體用來維持該通訊協定的位元與位元組之間的精準時間關係是很困難的,因此使得該實施不符合協定的要求。 Further, using a "bit pulse" to implement a protocol may be unsatisfactory for a number of reasons. The processor may not be fast enough to switch bits at the required rate, or may lack sufficient capabilities to perform other required tasks at the same time. Because the load on the processor may change over time, if not impossible, it is difficult for the firmware to maintain a precise time relationship between the bit and the byte of the protocol, thus making the implementation non-compliant The requirements of the agreement.
本發明描述一種用於實施匯流排操作以精確計時的系統。該系統包含一觸發描述符暫存器,其係用於描述一匯流排操作。該觸發描述符暫存器包括一匯流排定義欄,其進一步包含用於提供資料資訊與位址資訊給匯流排操作的資料欄與位址欄。該觸發描述符暫存器也包括一事件選擇欄,其係選擇用於匯流排操作的一觸發。一處理器係具有 配置該觸發描述符暫存器的能力。 The present invention describes a system for implementing busbar operations for accurate timing. The system includes a trigger descriptor register that is used to describe a bus operation. The trigger descriptor register includes a bus definition column, which further includes a data column and an address bar for providing data information and address information to the bus operation. The trigger descriptor register also includes an event selection field that selects a trigger for the bus operation. a processor system has The ability to configure this trigger descriptor register.
本發明的另一具體實施例係一種用於實施匯流排操作以精確計時的方法。該方法涉及提供包含一匯流排定義欄的一觸發描述符暫存器,該匯流排定義欄係進一步包括資料欄與位址欄。該觸發描述符暫存器也包括用於選擇給匯流排操作的一事件選擇欄。該方法根據該事件選擇欄來選擇用於該匯流排操作的一觸發。然後該方法根據該位址欄與資料欄執行該匯流排操作。 Another embodiment of the present invention is a method for implementing busbar operations for accurate timing. The method involves providing a trigger descriptor register including a bus definition column, the bus definition column further including a data column and an address bar. The trigger descriptor register also includes an event selection bar for selecting operations for the bus. The method selects a trigger for the bus operation based on the event selection field. The method then performs the bus operation based on the address bar and the data column.
以下詳細的描述係配合參考的圖式。示例性具體實施例被描述來說明本發明之標的物,而不是限制標的物的範圍,標的物係藉由所附加的申請專利範圍所定義。 The following detailed description is in conjunction with the drawings. The exemplified embodiments are described to illustrate the subject matter of the invention, and are not intended to limit the scope of the subject matter, which is defined by the scope of the appended claims.
硬體通常是為一組特定的功能所設計。因此,硬體不靈活且在沒有物理改變時通常不能被擴充至其他功能。即使當建設該硬體時,這些協定沒有被預料到,所揭示的方法與系統能夠以硬體協助協定的實施。所描述的示例性系統提供一組觸發,其係能根據一事件執行讀取與寫入,來排除處理器的干擾。在此,因為該中斷藉由硬體的幫助,所以能減少執行的不確定性,亦減少執行時間。本發明的某些具體實施例係特別適合用於幫助中斷,其係涉及少量的工作或終止,例如觸發幾個寫入操作。進一步,本發明的具體實施例允許事件的排序,例如首先允許一訊號發 生,然後在一定義的時間後執行一功能。 Hardware is usually designed for a specific set of functions. Therefore, hardware is inflexible and cannot usually be extended to other functions without physical changes. Even when the hardware was built, these agreements were not anticipated, and the disclosed methods and systems were able to assist the implementation of the agreement with hardware. The described exemplary system provides a set of triggers that are capable of performing read and write based on an event to eliminate interference from the processor. Here, since the interruption is assisted by hardware, the execution uncertainty can be reduced and the execution time can be reduced. Certain embodiments of the present invention are particularly well-suited for assisting in interrupts, which involve a small amount of work or termination, such as triggering several write operations. Further, embodiments of the present invention allow for the ordering of events, such as first allowing a signal to be sent Raw, then perform a function after a defined time.
第1圖說明一種用於實施匯流排操作以精確計時的系統100。該系統100具有透過一內部系統匯流排102來實施一匯流排處理(讀取或寫入)的能力,例如一先進高性能匯流排(AHB,Advanced High-performance Bus)。這些處理的每一者可藉由一中斷訊號來觸發,該中斷訊號藉由一適合的來源來提供,例如計時器。即使一嵌入式控制器或處理器忽略該中斷,該中斷本身為了能遮蔽,該觸發的匯流排操作將仍會發生。該匯流排操作也可藉由軟體寫入來觸發,其將在以下更詳述地解釋。 Figure 1 illustrates a system 100 for implementing busbar operations for accurate timing. The system 100 has the ability to perform a bus processing (read or write) through an internal system bus 102, such as an Advanced High-performance Bus (AHB). Each of these processes can be triggered by an interrupt signal provided by a suitable source, such as a timer. Even if an embedded controller or processor ignores the interrupt, the interrupt itself will still occur in order to be obscured. This bus operation can also be triggered by software writing, which will be explained in more detail below.
該系統100包括一主介面104(例如一AHB主介面)及一組觸發描述符暫存器105,其係定義為匯流排操作。該AHB主介面也可提供排序。每一個觸發描述符暫存器105包括一位址欄106與一資料欄108。一事件選擇欄112指出一或多個中斷訊號,其係能觸發該匯流排操作。幾個中斷訊號可藉由OR-ing或AND-ing該中斷來邏輯地結合。此外,一延遲時間欄110可被提供來指示一段時間的長度。 The system 100 includes a primary interface 104 (e.g., an AHB primary interface) and a set of trigger descriptor registers 105, which are defined as bus operations. The AHB main interface also provides sorting. Each trigger descriptor register 105 includes a bit field 106 and a data field 108. An event selection field 112 indicates one or more interrupt signals that can trigger the bus operation. Several interrupt signals can be logically combined by OR-ing or AND-ing the interrupt. Additionally, a delay time column 110 can be provided to indicate the length of a period of time.
進一步,一觸發描述符暫存器105可包括複數個欄,其係指示一匯流排操作讀取或寫入、位元組的數量被讀取或寫入或I/O是否被啟動。此外,一條件欄可包括指示該嵌入式控制器是否在休眠狀態、在低電力狀態或一外部匯流排是否被啟動。根據該條件欄,一觸發可被啟動。 Further, a trigger descriptor register 105 can include a plurality of columns indicating whether a bus operation reads or writes, the number of bytes is read or written, or whether I/O is initiated. Additionally, a condition bar can include an indication of whether the embedded controller is in a sleep state, in a low power state, or whether an external bus is activated. According to the condition bar, a trigger can be activated.
該事件選擇欄112作動成用於一多工器114的一選擇 器。該裝置接受輸入訊號,例如中斷訊號116,例如比較計時器訊號、其他計時器訊號或一通用輸入與輸出(GPIO,General Purpose Input/Ouput)中斷。該事件選擇欄112由用於該匯流排操作的中斷訊號116選擇一訊號(觸發)。在一實施中,該觸發能由任何一個觸發來產生。舉例來說,在該觸發描述符暫存器105的事件選擇欄112可為與所有可能的觸發對應之一位元向量,而並非只有編碼一個觸發的一短位元欄。此結構可具有連接邏輯的優點,在此結構中,不論是對一外部輸入回應或由另一事件延遲之後任一者,誰先發生則顯示出一個輸出。 The event selection field 112 is actuated as a selection for a multiplexer 114. Device. The device accepts input signals, such as interrupt signals 116, such as comparison timer signals, other timer signals, or a General Purpose Input/Ouput (GPIO) interrupt. The event selection field 112 selects a signal (trigger) from the interrupt signal 116 for the bus operation. In an implementation, the trigger can be generated by any one of the triggers. For example, the event selection field 112 at the trigger descriptor register 105 can be a bit vector corresponding to all possible triggers, rather than just a short bit field that encodes a trigger. This structure may have the advantage of connection logic in which an output is displayed, either for an external input response or by another event delay, whichever occurs first.
用於提供所要求的一段時間與排序,該延遲時間欄110提供一個選擇至外部計時器,例如比較計時器。該一段延遲負載至一計數器,該計數器作動成用於排序的一計時器。此延遲時間能比儲存於一外部計時器的近似延遲更短,因為該訊號不需安排該中斷邏輯的程序。此結構有利於在該匯流排操作期間精確計時。第1圖證明該延遲時間欄110如何能初始化一減少計數器,該減少計數器舉例來說係能根據在延遲時間欄110所指示的時間倒數至零。在倒數之後,該匯流排操作根據負載至該減少計數器的中斷訊號116來觸發。在第1圖,該觸發描述符暫存器105包括一時脈欄120,其係作為用於多工器122的一選擇器,以允時間單位的選擇,通常稱為毫秒或微秒。一減少計數器118利用所選擇的時間單位。熟悉此技術領域的通常知識者應了解到,雖然在此描述了一減少計數器,但任何類型的 計數器可被使用來執行一段時間的倒數。 Used to provide the required period of time and ordering, the delay time column 110 provides a selection to an external timer, such as a comparison timer. The period of delay is loaded to a counter that acts as a timer for sequencing. This delay time can be shorter than the approximate delay stored in an external timer because the signal does not need to schedule the interrupt logic. This configuration facilitates accurate timing during the bus operation. Figure 1 demonstrates how the delay time column 110 can initialize a decrease counter, which can, for example, count down to zero according to the time indicated in the delay time column 110. After the countdown, the bus operation is triggered based on the interrupt signal 116 loaded to the down counter. In FIG. 1, the trigger descriptor register 105 includes a clock column 120 as a selector for the multiplexer 122 to allow selection of time units, commonly referred to as milliseconds or microseconds. A decrease counter 118 utilizes the selected time unit. Those of ordinary skill in the art will appreciate that although a reduction counter is described herein, any type of A counter can be used to perform a reciprocal of a period of time.
一優先編碼器126可包括根據提供至每個匯流排操作的標示號碼來排序匯流排操作。另外,優先次序資訊可與每個匯流排操作有關。然而,熟悉此技術領域的通常知識者將了解到,根據幾個已知的技術,優先次序或許被提供至在一排序的匯流排操作。 A priority encoder 126 can include sorting bus operations based on the identification number provided to each bus operation. In addition, priority information can be associated with each bus operation. However, those of ordinary skill in the art will appreciate that prioritization may be provided to a ranked bus operation in accordance with several known techniques.
第1圖顯示該優先編碼器126的輸出作為用於兩個多工器的選擇器-一位址多工器128與一資料多工器130。以此方法,該系統選擇用於執行該匯流排操作之適當的位址資訊與資料。該位址與資料資訊係提供至該主介面104,然後執行該內部系統匯流排102上的匯流排操作。 The first diagram shows the output of the priority encoder 126 as a selector for the two multiplexers - an address multiplexer 128 and a data multiplexer 130. In this way, the system selects appropriate address information and materials for performing the bus operation. The address and data information is provided to the main interface 104, and then the bus operation on the internal system bus 102 is performed.
應了解的是該系統100在本質上係示例性且在不背離本發明的範圍下,幾種變化能被考量。舉例來說,取代用於選擇觸發的多工器114,一種間接的程度,例如辨認用於觸發的一位址之事件選擇欄112可被利用。進一步,應了解的是在此所描述的技術領域中也可有不同的性質與尺寸。 It will be appreciated that the system 100 is exemplary in nature and that several variations can be considered without departing from the scope of the invention. For example, instead of the multiplexer 114 for selecting a trigger, an indirect degree, such as an event selection field 112 that identifies the address for the trigger, can be utilized. Further, it should be understood that different properties and dimensions are also possible in the technical fields described herein.
第2圖揭示一種在該系統100內用於實施匯流排操作以精確計時的方法200。應了解的是在該方法200開始之前,該處理器或嵌入式控制器配置該等觸發描述符暫存器105。 FIG. 2 discloses a method 200 for implementing busbar operations for accurate timing within the system 100. It should be appreciated that the processor or embedded controller configures the trigger descriptor registers 105 prior to the start of the method 200.
在步驟202,該事件選擇欄112選擇一觸發,例如一中斷訊號116。根據該延遲時間欄110或一外部計時器,一段時間係在步驟204被取得。此觸發能在被取得的一段時間 後,活化相關的觸發描述符暫存器105。減少計數器118根據在步驟206的一段時間來倒數。一旦計數結束,與該觸發描述符暫存器105有關的匯流排操作在步驟208被執行。該硬體當執行該匯流排操作的同時,選擇適當的位址與資料。 At step 202, the event selection field 112 selects a trigger, such as an interrupt signal 116. A period of time is obtained at step 204 based on the delay time column 110 or an external timer. This trigger can be obtained for a while Thereafter, the associated trigger descriptor register 105 is activated. The reduction counter 118 counts down according to the period of time in step 206. Once the counting is complete, the bus operation associated with the trigger descriptor register 105 is performed at step 208. The hardware selects the appropriate address and data while performing the bus operation.
考慮該方法200如何能實施的一個範例。一個情況能夠被利用,舉例來說,如果在該特定晶片的一個接腳變低,一第二選擇的接腳應跟隨在10ms之後。要實現此結果,則該事件選擇欄112係配置來選擇一GPIO中斷。該GPIO係被配置而使得當該接腳具有高至低的轉變時,該GPIO訊號(該中斷訊號116的其中之一)變高。此外,該時脈欄120係被配置來選擇毫秒為時間單位,該延遲時間欄110包含「10」,該位址欄106包括該GPIO控制暫存器輸出接腳的位址,且該資料欄108包含「0」。因此,當GPIO 0觸發時,該事件選擇欄112選擇GPIO 1,從該延遲時間欄110將10載入到減少計數器118,且選擇毫秒為時脈單位。在10ms的延遲之後,該匯流排操作係被執行。該系統100執行一寫入操作至該GPIO控制暫存器,以改變該輸出接腳的狀態。 Consider an example of how the method 200 can be implemented. A situation can be utilized, for example, if one pin of the particular wafer goes low, a second selected pin should follow after 10 ms. To achieve this result, the event selection field 112 is configured to select a GPIO interrupt. The GPIO is configured such that when the pin has a high to low transition, the GPIO signal (one of the interrupt signals 116) goes high. In addition, the clock column 120 is configured to select milliseconds as a time unit, the delay time column 110 includes "10", the address field 106 includes an address of the GPIO control register output pin, and the data column 108 contains "0". Thus, when GPIO 0 is triggered, the event selection field 112 selects GPIO 1, loads 10 from the delay time column 110 to the reduction counter 118, and selects milliseconds as the clock unit. After a delay of 10 ms, the bus operation is performed. The system 100 performs a write operation to the GPIO control register to change the state of the output pin.
藉由使用該中斷訊號116由一外部輸入接腳來取得,一寫入能在一外部事件後,被配置以發生一段的精確程序時間。其他中斷同樣地能被使用。舉例來說,一個系統能將動作基於來自例如I2C的一個控制器之事件,或在溫度監控器所偵測的一超溫事件,或依據偵測一選擇電壓位準 的一模擬比較電路。這些及其他可能出現的情況在所屬的技術領域將是顯而易見的。 By using the interrupt signal 116 to be retrieved by an external input pin, a write can be configured to occur for a precise program time after an external event. Other interrupts can be used as well. For example, a system can base an action on an event from a controller such as I2C, or an over-temperature event detected by a temperature monitor, or based on detecting a selected voltage level. An analog comparison circuit. These and other possible situations will be apparent in the art.
在另一範例中,該事件選擇欄112可選擇不同的一個中斷訊號116,例如比較計時器。通常,該比較計時器利用全域時鐘。假設一個要求指令,其係一匯流排操作必須要在一計時器計數兩秒以後,執行一串列週邊介面(SPI,Serial Peripheral Interface)。在此,該位址欄106指出該SPI埠,且該資料欄108運載一啟動位元來啟動該SPI以開始傳輸。因為該段時間係由該比較計時器來取得,該延遲時間欄110包含「0」。該事件選擇欄112係被配置來選擇比較計時器1,且該比較計時器係被配置來算至兩秒。在兩秒以後,該匯流排操作在該SPI埠被啟動。 In another example, the event selection field 112 can select a different one of the interrupt signals 116, such as a comparison timer. Typically, this comparison timer utilizes a global clock. Assuming a request instruction, it is necessary for a bus operation to perform a serial peripheral interface (SPI) after two seconds of counting. Here, the address field 106 indicates the SPI, and the data field 108 carries a boot bit to initiate the SPI to begin transmission. Since the period of time is obtained by the comparison timer, the delay time column 110 contains "0". The event selection field 112 is configured to select the comparison timer 1, and the comparison timer is configured to count to two seconds. After two seconds, the bus operation is initiated at the SPI.
如上所述,如果一個以上的匯流排操作被觸發,則該優先編碼器126排序在匯流排操作之間。此排序能以數字順序發生,低數字事件優先在高數字事件之前。另外,該延遲時間能根據該時脈欄120與該多工器122預先按比例排列。此配置允許時間單位視需求而為微秒或毫秒。應了解的是,在此所指定的單位在本質上係示例性,且任何較佳的時間單位可被使用。 As described above, if more than one bus operation is triggered, the priority encoder 126 is ordered between bus operations. This sorting can occur in numerical order, with low digital events prior to high digital events. In addition, the delay time can be pre-scaled according to the clock column 120 and the multiplexer 122. This configuration allows time units to be microseconds or milliseconds as needed. It should be understood that the units specified herein are exemplary in nature and any preferred time unit can be used.
使用該延遲時間欄110,一比較計時器中斷可觸發兩個事件,一個是具有零延遲及第二個是具有非零延遲。如果兩個匯流排操作寫入至相同的GPIO資料暫存器,則此機制能被使用來產生時脈。此機制也能排序兩個外部訊號。此外,舉例來說,此機制也能藉由第一寫入該裝置結構暫 存器來配置某些其他硬體邏輯裝置,然後藉由寫入另一暫存器來啟動該裝置。適當的排序能藉由設定該延遲時間欄110來維持,以增加用於每個排序的匯流排操作之值。 Using the delay time column 110, a compare timer interrupt can trigger two events, one with zero delay and the second with non-zero delay. If two bus operations are written to the same GPIO data register, this mechanism can be used to generate the clock. This mechanism can also sort two external signals. In addition, for example, this mechanism can also be temporarily written by the device structure. The memory is configured to configure some other hardware logic device and then boot the device by writing to another register. Appropriate ordering can be maintained by setting the delay time field 110 to increase the value of the bus operation for each sort.
此機制的一範例係如下所述。為了開始一SPI操作,啟動一直接記憶體存取(DMA,direct memory access)控制器與一SPI控制器,其係涉及兩個寫入至兩個不同的暫存器。兩個觸發描述符暫存器105係被配置,且其觸發一比較計時器訊號,該比較計時器訊號在未來會發動兩秒。該第一觸發描述符暫存器105具有0ms的延遲時間,同時該第二觸發描述符暫存器具有1ms的延遲時間。該第一觸發描述符暫存器105觸發,然後該優先編碼器126排隊等候該匯流排操作。然後,該第二觸發描述符暫存器105係被啟動。排序係藉由該延遲時間被執行,同時該優先編碼器126可被利用來排序該匯流排操作。因此,幾個匯流排操作能根據相同的事件被觸發,且保證適當的排序。 An example of this mechanism is as follows. To initiate an SPI operation, a direct memory access (DMA) controller and an SPI controller are initiated, which involve writing two writes to two different registers. Two trigger descriptor registers 105 are configured and trigger a compare timer signal that will be activated for two seconds in the future. The first trigger descriptor register 105 has a delay time of 0 ms while the second trigger descriptor register has a delay time of 1 ms. The first trigger descriptor register 105 is triggered, and then the priority encoder 126 is queued for the bus operation. The second trigger descriptor register 105 is then activated. The ranking is performed by the delay time while the priority encoder 126 can be utilized to order the bus operation. Therefore, several bus operations can be triggered based on the same event and ensure proper sequencing.
一種用於觸發匯流排操作的替代機制係使用軟體。軟體能執行一寫入操作至一觸發描述符暫存器,以排除用於比較計時器或接腳中斷的需求。當結合在每個觸發描述符暫存器105內的延遲計時器時,軟體能藉由單一寫入至控制暫存器來抵消事件的精確計時排序。這種軟體寫入的一種應用係如下所述。 An alternative mechanism for triggering bus operations is to use software. The software can perform a write operation to a trigger descriptor register to eliminate the need to compare timer or pin interrupts. When combined with a delay timer within each trigger descriptor register 105, the software can offset the precise timing ordering of events by a single write to the control register. One application of such software writing is as follows.
藉由該等觸發描述符暫存器105所定義的動作係被執行一次,在此之後該觸發描述符暫存器被停用。然而,軟體能擴充該功能至多個時間執行。在此,該方法200能涉 及兩個軟體觸發事件及一個硬體觸發事件,其中該軟體能決定該硬體事件是否應該重複。交合邏輯係擴充功能可被使用時的範例。考慮一個狀態,如果第一接腳變低來反應第一事件,則發生第二事件,其係再50ms之後同樣地第二接腳變低。一旦該第一事件發生,軟體可能感測該第二事件,其係已發生在第二接腳。在此,該軟體能決定該第二事件是否應重新啟動。 The actions defined by the trigger descriptor registers 105 are executed once, after which the trigger descriptor register is deactivated. However, the software can extend this functionality to multiple time executions. Here, the method 200 can be involved And two software trigger events and a hardware trigger event, wherein the software can determine whether the hardware event should be repeated. An example of how the intersection logic can be used when it is extended. Considering a state, if the first pin goes low to reflect the first event, a second event occurs, which is followed by a second pin that goes down after another 50 ms. Once the first event occurs, the software may sense the second event, which has occurred at the second pin. Here, the software can determine whether the second event should be restarted.
考慮另一個範例。16位元的傳輸需要32個訊號轉換。實施上述所擴充的功能,該方法200將不需要32個觸發描述符暫存器105,但可以藉由軟體來管理少量的暫存器,藉以更新該觸發描述符暫存器105。觸發描述符暫存器105的排序能被配置,且該傳輸能只使用八個觸發描述符暫存器105來實行。第一組的四個觸發描述符暫存器105係根據第一事件啟動來開始傳輸資料。第二組的四個觸發描述符暫存器105係啟動第二事件。第一組的四個觸發描述符暫存器105的其中之一能設定計時器,其係在完成後能提供中斷至該嵌入式控制器。該嵌入式控制器接受中斷,以藉由完成的第一組指示資料傳輸。然後該軟體重新配置用於進一步資料傳輸的第一組之觸發描述符暫存器105。在此,軟體有足夠的時間來更新該第一組。以此方法,任意數量的資料可只使用少量觸發描述符暫存器105來傳輸。該硬體機構能透過軟體擴充,同時維持該硬體的精確。 Consider another example. A 16-bit transmission requires 32 signal conversions. Implementing the expanded functionality described above, the method 200 would not require 32 trigger descriptor registers 105, but a small number of registers can be managed by software to update the trigger descriptor register 105. The ordering of the trigger descriptor register 105 can be configured and the transfer can be performed using only eight trigger descriptor registers 105. The first set of four trigger descriptor registers 105 initiates the transfer of data based on the first event initiation. The second set of four trigger descriptor registers 105 initiates a second event. One of the first set of four trigger descriptor registers 105 can set a timer that, upon completion, can provide an interrupt to the embedded controller. The embedded controller accepts an interrupt to transmit the data by the first set of instructions. The software then reconfigures the first set of trigger descriptor registers 105 for further data transfer. Here, the software has enough time to update the first group. In this way, any amount of data can be transmitted using only a small number of trigger descriptor registers 105. The hardware mechanism can be expanded by the software while maintaining the accuracy of the hardware.
所屬技術領域之通常知識者將了解上述所討論的步驟在所揭示的具體配置可被合併或改變。該等所說明的步驟 被用來解釋所示之具體實施例,且應預料到正在進行中技術發展將改變本發明中特定函數的執行方式。這些圖式不用來限制本發明所揭示之範圍,僅藉由參照該等附加的申請專利範圍來判定。 Those of ordinary skill in the art will appreciate that the steps discussed above may be combined or altered in the particular configurations disclosed. The steps described It is intended to be illustrative of the specific embodiments shown, and it is contemplated that an in- The drawings are not intended to limit the scope of the invention, which is determined by reference to the appended claims.
100‧‧‧系統 100‧‧‧ system
102‧‧‧內部系統匯流排 102‧‧‧Internal system bus
104‧‧‧主介面 104‧‧‧ main interface
105‧‧‧觸發描述符暫存器 105‧‧‧Trigger Descriptor Register
106‧‧‧位址欄 106‧‧‧Address Bar
108‧‧‧資料欄 108‧‧‧Information Bar
110‧‧‧延遲時間欄 110‧‧‧Delay time column
112‧‧‧事件選擇欄 112‧‧‧Event selection bar
128‧‧‧位址多工器 128‧‧‧ address multiplexer
130‧‧‧資料多工器 130‧‧‧Data multiplexer
200‧‧‧方法 200‧‧‧ method
202-208‧‧‧步驟 202-208‧‧‧Steps
該等圖式的描述陳列如下並說明本發明一些示例性具體實施例。所有的圖式中,類似的參考元件符號歸類於相同或功能類似的元件。該等圖式在本質上係說明性,並非按比例繪製。 The description of the drawings is set forth below and illustrates some exemplary embodiments of the invention. In all figures, similar reference component symbols are classified as identical or functionally similar components. The drawings are illustrative in nature and are not to scale.
第1圖係說明一種用於實施匯流排操作以精確時間的系統。 Figure 1 illustrates a system for implementing busbar operations for precise time.
第2圖係說明在第1圖的系統中,一種用於實施匯流排操作以精確時間的方法。 Figure 2 illustrates a method for implementing busbar operations for precise time in the system of Figure 1.
100‧‧‧系統 100‧‧‧ system
102‧‧‧內部系統匯流排 102‧‧‧Internal system bus
104‧‧‧主介面 104‧‧‧ main interface
105‧‧‧觸發描述符暫存器 105‧‧‧Trigger Descriptor Register
106‧‧‧位址欄 106‧‧‧Address Bar
108‧‧‧資料欄 108‧‧‧Information Bar
110‧‧‧延遲時間欄 110‧‧‧Delay time column
112‧‧‧事件選擇欄 112‧‧‧Event selection bar
114‧‧‧多工器 114‧‧‧Multiplexer
116‧‧‧中斷訊號 116‧‧‧Interrupt signal
118‧‧‧減少計數器 118‧‧‧Reducing counters
120‧‧‧時脈欄 120‧‧‧ clock bar
122‧‧‧多工器 122‧‧‧Multiplexer
126‧‧‧優先編碼器 126‧‧‧Priority encoder
128‧‧‧位址多工器 128‧‧‧ address multiplexer
130‧‧‧資料多工器 130‧‧‧Data multiplexer
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