TWI581103B - Method and system for implementing bus operations with precise timing - Google Patents

Description

Method and system for implementing bus operation with precise timing

The present invention relates to the field of embedded systems and, more particularly, to bus operations (storage and memory read and write) within an embedded system.

In an embedded control system, a plurality of request instructions may authorize certain actions to occur in response to an event. Some requirements are immediate; that is, the response must occur at a well-defined time after the initial event.

Another common feature is embedded controller support, which exchanges information with one or more devices via communication. Agreements are usually well defined in the form of pulse edges and allow for small amounts of interference. Many communication protocols, such as Philips' I2C, directly support hardware. However, when designing the hardware, an embedded controller may be required to support an unanticipated agreement. One method for solving this problem is called "bit pulse" where the controller directly switches the pins for each transfer bit or byte.

A conventional solution (or a processor) is used for traditional solutions that deal with events that are not known at the time of designing the device. The processor, using a program (part of the device firmware), can check the input and decide how to respond to a changed stimulus input or event. This method is very flexible, especially if the firmware for the embedded controller can be modified. However, there are a number of limitations, as described below.

Usually, the processor has multiple implementations on the input and output signals. The ability to perform operations, but these capabilities are based on cost. If the response must be timely, the processor will most likely request an interrupt indicating an event of interest to it. These interrupts can consume a significant amount of time, and therefore the processor response can also occur. In addition, processing interrupts can require many processor cycles, which means that the processor cannot operate on other functions while responding to events. Another limitation is that using a processor to perform a simple response would require considerable power, in addition to the instruction and data memory, while the processor can require thousands of gates to process the indications that require the reflection.

Further, using a "bit pulse" to implement a protocol may be unsatisfactory for a number of reasons. The processor may not be fast enough to switch bits at the required rate, or may lack sufficient capabilities to perform other required tasks at the same time. Because the load on the processor may change over time, if not impossible, it is difficult for the firmware to maintain a precise time relationship between the bit and the byte of the protocol, thus making the implementation non-compliant The requirements of the agreement.

The present invention describes a system for implementing busbar operations for accurate timing. The system includes a trigger descriptor register that is used to describe a bus operation. The trigger descriptor register includes a bus definition column, which further includes a data column and an address bar for providing data information and address information to the bus operation. The trigger descriptor register also includes an event selection field that selects a trigger for the bus operation. a processor system has The ability to configure this trigger descriptor register.

Another embodiment of the present invention is a method for implementing busbar operations for accurate timing. The method involves providing a trigger descriptor register including a bus definition column, the bus definition column further including a data column and an address bar. The trigger descriptor register also includes an event selection bar for selecting operations for the bus. The method selects a trigger for the bus operation based on the event selection field. The method then performs the bus operation based on the address bar and the data column.

The following detailed description is in conjunction with the drawings. The exemplified embodiments are described to illustrate the subject matter of the invention, and are not intended to limit the scope of the subject matter, which is defined by the scope of the appended claims.

summary

Hardware is usually designed for a specific set of functions. Therefore, hardware is inflexible and cannot usually be extended to other functions without physical changes. Even when the hardware was built, these agreements were not anticipated, and the disclosed methods and systems were able to assist the implementation of the agreement with hardware. The described exemplary system provides a set of triggers that are capable of performing read and write based on an event to eliminate interference from the processor. Here, since the interruption is assisted by hardware, the execution uncertainty can be reduced and the execution time can be reduced. Certain embodiments of the present invention are particularly well-suited for assisting in interrupts, which involve a small amount of work or termination, such as triggering several write operations. Further, embodiments of the present invention allow for the ordering of events, such as first allowing a signal to be sent Raw, then perform a function after a defined time.

Detailed description paragraph

Figure 1 illustrates a system 100 for implementing busbar operations for accurate timing. The system 100 has the ability to perform a bus processing (read or write) through an internal system bus 102, such as an Advanced High-performance Bus (AHB). Each of these processes can be triggered by an interrupt signal provided by a suitable source, such as a timer. Even if an embedded controller or processor ignores the interrupt, the interrupt itself will still occur in order to be obscured. This bus operation can also be triggered by software writing, which will be explained in more detail below.

The system 100 includes a primary interface 104 (e.g., an AHB primary interface) and a set of trigger descriptor registers 105, which are defined as bus operations. The AHB main interface also provides sorting. Each trigger descriptor register 105 includes a bit field 106 and a data field 108. An event selection field 112 indicates one or more interrupt signals that can trigger the bus operation. Several interrupt signals can be logically combined by OR-ing or AND-ing the interrupt. Additionally, a delay time column 110 can be provided to indicate the length of a period of time.

Further, a trigger descriptor register 105 can include a plurality of columns indicating whether a bus operation reads or writes, the number of bytes is read or written, or whether I/O is initiated. Additionally, a condition bar can include an indication of whether the embedded controller is in a sleep state, in a low power state, or whether an external bus is activated. According to the condition bar, a trigger can be activated.

The event selection field 112 is actuated as a selection for a multiplexer 114. Device. The device accepts input signals, such as interrupt signals 116, such as comparison timer signals, other timer signals, or a General Purpose Input/Ouput (GPIO) interrupt. The event selection field 112 selects a signal (trigger) from the interrupt signal 116 for the bus operation. In an implementation, the trigger can be generated by any one of the triggers. For example, the event selection field 112 at the trigger descriptor register 105 can be a bit vector corresponding to all possible triggers, rather than just a short bit field that encodes a trigger. This structure may have the advantage of connection logic in which an output is displayed, either for an external input response or by another event delay, whichever occurs first.

Used to provide the required period of time and ordering, the delay time column 110 provides a selection to an external timer, such as a comparison timer. The period of delay is loaded to a counter that acts as a timer for sequencing. This delay time can be shorter than the approximate delay stored in an external timer because the signal does not need to schedule the interrupt logic. This configuration facilitates accurate timing during the bus operation. Figure 1 demonstrates how the delay time column 110 can initialize a decrease counter, which can, for example, count down to zero according to the time indicated in the delay time column 110. After the countdown, the bus operation is triggered based on the interrupt signal 116 loaded to the down counter. In FIG. 1, the trigger descriptor register 105 includes a clock column 120 as a selector for the multiplexer 122 to allow selection of time units, commonly referred to as milliseconds or microseconds. A decrease counter 118 utilizes the selected time unit. Those of ordinary skill in the art will appreciate that although a reduction counter is described herein, any type of A counter can be used to perform a reciprocal of a period of time.

A priority encoder 126 can include sorting bus operations based on the identification number provided to each bus operation. In addition, priority information can be associated with each bus operation. However, those of ordinary skill in the art will appreciate that prioritization may be provided to a ranked bus operation in accordance with several known techniques.

The first diagram shows the output of the priority encoder 126 as a selector for the two multiplexers - an address multiplexer 128 and a data multiplexer 130. In this way, the system selects appropriate address information and materials for performing the bus operation. The address and data information is provided to the main interface 104, and then the bus operation on the internal system bus 102 is performed.

It will be appreciated that the system 100 is exemplary in nature and that several variations can be considered without departing from the scope of the invention. For example, instead of the multiplexer 114 for selecting a trigger, an indirect degree, such as an event selection field 112 that identifies the address for the trigger, can be utilized. Further, it should be understood that different properties and dimensions are also possible in the technical fields described herein.

FIG. 2 discloses a method 200 for implementing busbar operations for accurate timing within the system 100. It should be appreciated that the processor or embedded controller configures the trigger descriptor registers 105 prior to the start of the method 200.

At step 202, the event selection field 112 selects a trigger, such as an interrupt signal 116. A period of time is obtained at step 204 based on the delay time column 110 or an external timer. This trigger can be obtained for a while Thereafter, the associated trigger descriptor register 105 is activated. The reduction counter 118 counts down according to the period of time in step 206. Once the counting is complete, the bus operation associated with the trigger descriptor register 105 is performed at step 208. The hardware selects the appropriate address and data while performing the bus operation.

Consider an example of how the method 200 can be implemented. A situation can be utilized, for example, if one pin of the particular wafer goes low, a second selected pin should follow after 10 ms. To achieve this result, the event selection field 112 is configured to select a GPIO interrupt. The GPIO is configured such that when the pin has a high to low transition, the GPIO signal (one of the interrupt signals 116) goes high. In addition, the clock column 120 is configured to select milliseconds as a time unit, the delay time column 110 includes "10", the address field 106 includes an address of the GPIO control register output pin, and the data column 108 contains "0". Thus, when GPIO 0 is triggered, the event selection field 112 selects GPIO 1, loads 10 from the delay time column 110 to the reduction counter 118, and selects milliseconds as the clock unit. After a delay of 10 ms, the bus operation is performed. The system 100 performs a write operation to the GPIO control register to change the state of the output pin.

By using the interrupt signal 116 to be retrieved by an external input pin, a write can be configured to occur for a precise program time after an external event. Other interrupts can be used as well. For example, a system can base an action on an event from a controller such as I2C, or an over-temperature event detected by a temperature monitor, or based on detecting a selected voltage level. An analog comparison circuit. These and other possible situations will be apparent in the art.

In another example, the event selection field 112 can select a different one of the interrupt signals 116, such as a comparison timer. Typically, this comparison timer utilizes a global clock. Assuming a request instruction, it is necessary for a bus operation to perform a serial peripheral interface (SPI) after two seconds of counting. Here, the address field 106 indicates the SPI, and the data field 108 carries a boot bit to initiate the SPI to begin transmission. Since the period of time is obtained by the comparison timer, the delay time column 110 contains "0". The event selection field 112 is configured to select the comparison timer 1, and the comparison timer is configured to count to two seconds. After two seconds, the bus operation is initiated at the SPI.

As described above, if more than one bus operation is triggered, the priority encoder 126 is ordered between bus operations. This sorting can occur in numerical order, with low digital events prior to high digital events. In addition, the delay time can be pre-scaled according to the clock column 120 and the multiplexer 122. This configuration allows time units to be microseconds or milliseconds as needed. It should be understood that the units specified herein are exemplary in nature and any preferred time unit can be used.

Using the delay time column 110, a compare timer interrupt can trigger two events, one with zero delay and the second with non-zero delay. If two bus operations are written to the same GPIO data register, this mechanism can be used to generate the clock. This mechanism can also sort two external signals. In addition, for example, this mechanism can also be temporarily written by the device structure. The memory is configured to configure some other hardware logic device and then boot the device by writing to another register. Appropriate ordering can be maintained by setting the delay time field 110 to increase the value of the bus operation for each sort.

An example of this mechanism is as follows. To initiate an SPI operation, a direct memory access (DMA) controller and an SPI controller are initiated, which involve writing two writes to two different registers. Two trigger descriptor registers 105 are configured and trigger a compare timer signal that will be activated for two seconds in the future. The first trigger descriptor register 105 has a delay time of 0 ms while the second trigger descriptor register has a delay time of 1 ms. The first trigger descriptor register 105 is triggered, and then the priority encoder 126 is queued for the bus operation. The second trigger descriptor register 105 is then activated. The ranking is performed by the delay time while the priority encoder 126 can be utilized to order the bus operation. Therefore, several bus operations can be triggered based on the same event and ensure proper sequencing.

An alternative mechanism for triggering bus operations is to use software. The software can perform a write operation to a trigger descriptor register to eliminate the need to compare timer or pin interrupts. When combined with a delay timer within each trigger descriptor register 105, the software can offset the precise timing ordering of events by a single write to the control register. One application of such software writing is as follows.

The actions defined by the trigger descriptor registers 105 are executed once, after which the trigger descriptor register is deactivated. However, the software can extend this functionality to multiple time executions. Here, the method 200 can be involved And two software trigger events and a hardware trigger event, wherein the software can determine whether the hardware event should be repeated. An example of how the intersection logic can be used when it is extended. Considering a state, if the first pin goes low to reflect the first event, a second event occurs, which is followed by a second pin that goes down after another 50 ms. Once the first event occurs, the software may sense the second event, which has occurred at the second pin. Here, the software can determine whether the second event should be restarted.

Consider another example. A 16-bit transmission requires 32 signal conversions. Implementing the expanded functionality described above, the method 200 would not require 32 trigger descriptor registers 105, but a small number of registers can be managed by software to update the trigger descriptor register 105. The ordering of the trigger descriptor register 105 can be configured and the transfer can be performed using only eight trigger descriptor registers 105. The first set of four trigger descriptor registers 105 initiates the transfer of data based on the first event initiation. The second set of four trigger descriptor registers 105 initiates a second event. One of the first set of four trigger descriptor registers 105 can set a timer that, upon completion, can provide an interrupt to the embedded controller. The embedded controller accepts an interrupt to transmit the data by the first set of instructions. The software then reconfigures the first set of trigger descriptor registers 105 for further data transfer. Here, the software has enough time to update the first group. In this way, any amount of data can be transmitted using only a small number of trigger descriptor registers 105. The hardware mechanism can be expanded by the software while maintaining the accuracy of the hardware.

Those of ordinary skill in the art will appreciate that the steps discussed above may be combined or altered in the particular configurations disclosed. The steps described It is intended to be illustrative of the specific embodiments shown, and it is contemplated that an in- The drawings are not intended to limit the scope of the invention, which is determined by reference to the appended claims.

100‧‧‧ system

102‧‧‧Internal system bus

104‧‧‧ main interface

105‧‧‧Trigger Descriptor Register

106‧‧‧Address Bar

108‧‧‧Information Bar

110‧‧‧Delay time column

112‧‧‧Event selection bar

128‧‧‧ address multiplexer

130‧‧‧Data multiplexer

200‧‧‧ method

202-208‧‧‧Steps

The description of the drawings is set forth below and illustrates some exemplary embodiments of the invention. In all figures, similar reference component symbols are classified as identical or functionally similar components. The drawings are illustrative in nature and are not to scale.

Figure 1 illustrates a system for implementing busbar operations for precise time.

Figure 2 illustrates a method for implementing busbar operations for precise time in the system of Figure 1.

100‧‧‧ system

102‧‧‧Internal system bus

104‧‧‧ main interface

105‧‧‧Trigger Descriptor Register

106‧‧‧Address Bar

108‧‧‧Information Bar

110‧‧‧Delay time column

112‧‧‧Event selection bar

114‧‧‧Multiplexer

116‧‧‧Interrupt signal

118‧‧‧Reducing counters

120‧‧‧ clock bar

122‧‧‧Multiplexer

126‧‧‧Priority encoder

128‧‧‧ address multiplexer

130‧‧‧Data multiplexer

Claims (22)

A system for accurately performing timing for implementing bus operation, the system comprising: a processor; a system bus operative to receive read operations and write operations; and a trigger descriptor register for use Defining a bus operation to be performed on the system bus, the trigger descriptor register includes: a bus definition column, which includes a data column and an address bar, configured to provide pre-written data Information and address information for performing the bus operation; and a trigger selection field configured to select a trigger signal for the bus operation, wherein the trigger signal is triggered without any processor control One of the bus operations is hardware assisted execution to transmit the pre-written data information and the address information via the system bus; and wherein the processor is operative to configure the trigger descriptor register. The system of claim 1, wherein the trigger descriptor register further comprises a delay time field configured to store a time value. The system of claim 2, further comprising a counter configured to count according to a period of time, wherein the bus operation is performed according to the data column and the address bar at the end of the counting, The period of time is obtained by one or more of the following: the delay time column; or An external timer. The system of claim 1, wherein the trigger descriptor register comprises a clock bar for selecting two or more time units. The system of claim 1, wherein if the plurality of trigger signals have been selected, further comprising a priority encoder configured to manage the prioritization of the bus operations. The system of claim 2, wherein the trigger selection field and the delay time column are utilized to link two or more interrupt signals together. The system of claim 1, wherein the software can restart a trigger descriptor register. The system of claim 1, wherein the trigger descriptor register further comprises one or more of the following columns: a condition bar that identifies various conditions within the system; a bus launch pad Whether it indicates whether the bus operation associated with the trigger descriptor register is started; or a read/write column indicating that the bus operation associated with the trigger descriptor register is a read Take an operation or a write operation. The system of claim 1, wherein the trigger signal is an interrupt signal fed to the processor, and wherein the interrupt signal can be obscured. The system of claim 9, wherein the interrupt signal is a subset of two or more interrupt signals. A method for performing bus operation with precise timing, the method package Included: providing a processor; providing a system bus that is operable to receive a bus read or write operation; and programming a trigger descriptor by the processor, wherein the trigger descriptor comprises: a bus definition bar And comprising a data column and an address bar; a trigger selection field configured to select a trigger signal for performing a bus read or write operation, wherein the trigger signal triggers the bus read or write operation Executing; selecting a trigger signal according to the programmed trigger selection field for triggering execution of the bus operation; and executing the bus according to the address bar and the data column without processor interference operating. The method of claim 11, further comprising the step of: obtaining a period of time by one or more of: a delay time column; or an external timer; and counting according to the period of time, wherein the trigger description The character further includes the delay time column. The method of claim 11, further comprising selecting between the two or more time units according to a clock bar within the trigger descriptor. For example, in the method of claim 11, if a plurality of trigger signals have been selected, the priority of managing the bus operation is further included. The method of claim 12, further comprising linking the two or more trigger signals together by using the trigger selection field and the delay time column. The method of claim 11, further comprising restarting a trigger descriptor by software. The method of claim 11, wherein the trigger descriptor register further comprises one or more of the following columns: a condition bar that identifies various conditions regarding the hardware; a bus launch bar Whether it indicates whether the bus operation associated with the trigger descriptor is activated; or a read/write column indicating that the bus operation associated with the trigger descriptor is a read operation or a write operating. The method of claim 11, wherein the trigger signal is an interrupt signal fed to the processor, and wherein the interrupt signal can be masked. The method of claim 11, wherein the interrupt signal is a subset of two or more interrupt signals. A system for accurately performing timing for implementing busbar operations, the system comprising: a system busbar; a busbar processing unit coupled to the system busbar and operable Performing a bus read or write operation without processor control, wherein the bus read or write operation is based on an address and related data, and the bus processing unit includes: a trigger descriptor temporarily a buffer for describing a bus operation to be performed on the bus bar of the system, the trigger descriptor register comprising: a bus definition column including data for storing the address and data a column and an address bar configured to provide pre-written data information and address information for performing the bus operation; and a trigger selection field configured to select a trigger signal for the bus operation, The trigger signal triggers execution of the bus operation without processor interference, thereby transmitting the pre-written data information and the address information via the system bus; and the processor is operable to configure the trigger Descriptor register. The system of claim 20, wherein the bus processing unit further comprises a main interface coupled to the system bus and operable to perform read access and write access to the system bus . The system of claim 21, wherein the system bus is an advanced high performance bus (AHB).