JP2009163531A - Interruption management mechanism and microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of execution times of interruption processing in a CPU and to improve the processing efficiency of the CPU. <P>SOLUTION: In a microcomputer (10) for executing data transfer between the CPU (20) and a memory (60) through a serial interface (50), an interruption management mechanism (40) for managing an interruption request of the serial interface (50) includes state transition circuits (42f, 42g) and an interruption request issue circuit (42). The state transition circuits (42f, 42g) transit their states according to a sort of the interruption request and the number of issues in accordance with the issue of the interruption request from the serial interface (50). The interruption request issue circuit (42) issues an interruption request to the CPU (20) when the states of the state transition circuits (42f, 42g) are transited to prescribed states. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an interrupt management mechanism and a microcomputer.

  In a microcomputer equipped with a serial interface compatible memory (memory having a 1-bit data input / output unit), a serial communication circuit (serial interface) is installed as a circuit for performing write access / read access to the memory. Data transfer between a CPU (Central Processing Unit) and a memory is performed via a serial communication circuit. When accessing the memory, the serial communication circuit performs a sequence operation for changing the operation state in the order of “command transmission operation”, “address transmission operation”, “data transmission operation / data reception operation”, and changes the operation state. Each time a transition is made, an interrupt request is issued to the CPU. Therefore, in a microcomputer equipped with a serial interface compatible memory, interrupt processing is repeatedly executed by the CPU during data transfer between the CPU and the memory.

In addition, as a prior art document relevant to this invention, patent document 1, 2 is mentioned, for example. Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique for performing data transfer between microcomputers at high speed and efficiently with respect to the microcomputer. Patent Document 2 discloses a technique for efficiently executing DMA transfer by reducing the number of times transfer information is set for a DMA (Direct Memory Access) controller.
Japanese Patent Laid-Open No. 4-169955 JP 2003-256356 A

  In a microcomputer equipped with a serial interface compatible memory, the CPU needs to execute an interrupt process every time an interrupt request is issued by the serial communication circuit when transferring data between the CPU and the memory. There is a problem in that the processing efficiency of the CPU is lowered because the processing to be executed cannot be concentrated.

  The present invention has been made in view of such problems, and in a microcomputer in which data transfer between a CPU and a memory is performed via a serial interface, the number of CPU interrupt processing executions is reduced to reduce the CPU. It aims at improving processing efficiency.

  The interrupt management mechanism is an interrupt management mechanism that manages an interrupt request of a serial interface in a microcomputer in which data transfer between the CPU and the memory is performed via the serial interface, and includes a state transition circuit and an interrupt request issue circuit. Prepare. In the state transition circuit, as the serial interface issues an interrupt request, the state transitions according to the type of interrupt request and the number of times it is issued. The interrupt request issue circuit issues an interrupt request to the CPU as the state transition circuit changes to a predetermined state.

  For example, the state transition circuit includes first and second registers and first and second counters. The first register holds information indicating the number of state transitions when accessing the memory in the serial interface. The second register holds information indicating the number of data transfers at the time of accessing the memory in the serial interface. The first counter counts the number of times an interrupt request is issued due to the state transition of the serial interface. The second counter counts the number of issuance of interrupt requests accompanying the data transfer of the serial interface after the count operation of the first counter is performed the number of times corresponding to the information in the first register. The interrupt request issuing circuit issues an interrupt request to the CPU as the count operation of the second counter is performed a number of times corresponding to the information in the second register.

  In a microcomputer in which data transfer between the CPU and the memory is performed via a serial interface, the number of CPU interrupt processes can be reduced, and the CPU processing efficiency can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows an embodiment of the present invention. The microcomputer 10 includes a CPU 20, an interrupt controller 30, an ISU (Interrupt Scheduling Unit) 40, an SPI (Serial Peripheral Interface) 50, and an SPI-compatible memory 60.

  The CPU 20 executes various processes according to a program stored in a program memory (not shown). When any one of the plurality of interrupt signals including the interrupt signals IRQT and IRQR is activated, the interrupt controller 30 notifies the CPU 20 of an interrupt number assigned in advance to the activated interrupt signal and performs interrupt processing. Is requested to the CPU 20. As a result, the CPU 20 executes the interrupt process corresponding to the interrupt number notified from the interrupt controller 30.

  The ISU 40 includes a transmission / reception unit 41 and a control unit 42. The transmission / reception unit 41 includes a transmission buffer 41a and a reception buffer 41b. The transmission / reception unit 41 stores data supplied from the CPU 20 via the system bus BUS in the transmission buffer 41a in accordance with the write access to the transmission buffer 41a by the CPU 20. The transmission / reception unit 41 supplies the data stored in the reception buffer 41b to the CPU 20 via the system bus BUS in accordance with the read access to the reception buffer 41b by the CPU 20. Further, the transmission / reception unit 41 performs write access / read access to the registers in the SPI 50 in accordance with instructions from the control unit 42. The transmission / reception unit 41 supplies the data stored in the transmission buffer 41a to the SPI 50 as write data at the time of write access to the register in the SPI 50. The transmission / reception unit 41 stores the read data supplied from the SPI 50 in the reception buffer 41b at the time of read access to the register in the SPI 50. When the transmission / reception unit 41 recognizes that the data stored in the transmission buffer 41a is data for setting a register (such as the mode setting register 52a) in the SPI 50, the transmission / reception unit 41 writes to set the register in the SPI 50. Implement access.

  The control unit 42 includes a transfer setting register 42a, a state management counter 42f, and a transfer count counter 42g. The transfer setting register 32a is a register accessible by the CPU 20, and includes a transfer start bit 42b, an interrupt setting bit 42c, a transfer sequence setting bit 42d, and a transfer data length setting bit 42e. The transfer start bit 42b is a bit for instructing the operation start of the ISU 40. For example, the transfer start bit 42b is set to “1” when the operation of the ISU 40 is started. The interrupt setting bit 42c is a bit for setting one of the interrupt signals IRQTS and IRQRS as a count factor of the transfer number counter 42g. For example, the interrupt setting bit 42c is set to “0” when the interrupt signal IRQTS is set as the count factor of the transfer count counter 42g, and “1” when the interrupt signal IRQRS is set as the count factor of the transfer count counter 42g. Set to The transfer sequence setting bit 42d is a bit for setting the number of state transitions when accessing the memory 60 in the SPI 50. For example, the transfer sequence setting bit 42d is a sequence operation that changes the operation state in the order of "command transmission operation", "upper address transmission operation", and "data transmission operation / data reception operation" when accessing the memory 60 in the SPI 50. Is set to “0” (when the number of state transitions when accessing the memory 60 in the SPI 50 is 2). The transfer sequence setting bit 42d is in the order of "command transmission operation", "upper address transmission operation", "lower address transmission operation", and "data transmission operation / data reception operation" when accessing the memory 60 in the SPI 50. It is set to “1” when a sequence operation for changing the operation state is performed (when the number of state transitions when accessing the memory 60 in the SPI 50 is 3). The transfer data length setting bit 42e is a bit for setting the transfer data length between the SPI 50 and the memory 60 (corresponding to the number of data transfers between the SPI 50 and the memory 60) in the data transmission operation / data reception operation of the SPI 50. For example, the transfer data length setting bit 42e is set to “0” when the transfer data length between the SPI 50 and the memory 60 in the data transmission operation / data reception operation of the SPI 50 is 1 byte, and the data transmission operation / data of the SPI 50 is set. It is set to “1” when the transfer data length between the SPI 50 and the memory 60 in the reception operation is 2 bytes.

  The state management counter 42f sets, as a counter value, the number of state transitions of the SPI 50 corresponding to the set value of the transfer sequence setting bit 42d as the transfer start bit 42b is set to “1”. Specifically, when the transfer sequence setting bit 42d is set to “0”, the state management counter 42f sets the counter value to 2 as the transfer start bit 42b is set to “1”. When the transfer sequence setting bit 42d is set to “1”, the counter value is set to 3 as the transfer start bit 42b is set to “1”. The state management counter 42f performs a down-count operation every time the interrupt signal IRQTS is activated, and stops the down-count operation when the counter value becomes zero.

  The transfer counter 42g counts the transfer data length (number of bytes) between the SPI 50 and the memory 60 corresponding to the set value of the transfer data length setting bit 32e as the transfer start bit 42b is set to "1". Set as a value. Specifically, when the transfer data length setting bit 42e is set to “0”, the transfer number counter 42g sets the count value to 1 as the transfer start bit 42b is set to “1”. When the transfer data length setting bit 42e is set to “1”, the count value is set to 2 as the transfer start bit 42b is set to “1”. Then, the transfer count counter 42g performs the down-count operation every time the one set by the interrupt setting bit 42c in the interrupt signals IRQTS and IRQRS is activated after the state management counter 42f stops the down-count operation. The countdown operation is stopped when the counter value reaches zero.

  As the transfer start bit 42b is set to “1”, the control unit 42 instructs the transmission / reception unit 41 to perform a write access to the transmission register 51a in the SPI 50. When the interrupt signal IRQTS is set as the count factor of the transfer count counter 42g by the interrupt setting bit 42c, the control unit 42 executes the SPI 50 as the state management counter 42f or the transfer count counter 42g performs the down-count operation. The transmission / reception unit 41 is instructed to perform write access to the transmission register 51a. Further, when the interrupt signal IRQRS is set as the count factor of the transfer counter 42g by the interrupt setting bit 42c, the control unit 42 performs the state management counter 42f as the state management counter 42f performs the down-counting operation. If the counter value of the SPI 50 is not 0, a write access to the transmission register 51a in the SPI 50 is instructed to the transmission / reception unit 41. A write access to 52a is instructed. When the interrupt signal IRQRS is set as the count factor of the transfer number counter 42g by the interrupt setting bit 42c, the control unit 42 receives the reception register 51b in the SPI 50 as the transfer number counter 42g performs the down-count operation. Is instructed to the transmission / reception unit 41. Further, as the transfer counter 42g stops the down-counting operation (as the counter value of the transfer counter 42g becomes 0), the control unit 42 sets the transfer counter 42g by the interrupt setting bit 42c. If the interrupt signal IRQTS is set as the count factor, the interrupt signal IRQT is activated, and if the interrupt signal IRQRS is set as the count factor of the transfer count counter 42g by the interrupt setting bit 42c, the interrupt signal IRQR is activated.

  The SPI 50 includes a transmission / reception unit 51 and a control unit 52. The transmission / reception unit 51 includes a transmission register 51a, a reception register 51b, and a shift register 51c. Here, it is assumed that the transmission register 51a, the reception register 51b, and the shift register 51c are configured as 8-bit registers. The transmission / reception unit 51 stores the data supplied from the ISU 40 in the transmission register 51a in accordance with the write access to the transmission register 51a by the ISU 40. The transmission / reception unit 51 transfers the data stored in the transmission register 51a to the shift register 51c in accordance with an instruction from the control unit 52, and sequentially supplies the serial data SO to the memory 60 by the shift operation of the shift register 51c. Further, the transmission / reception unit 51 sequentially fetches the serial data SI by the shift operation of the shift register 51c according to the instruction of the control unit 52, and stores the 8-bit data in the shift register 51 and stores it in the shift register 51c. Data is transferred to the reception register 51b. The transmission / reception unit 51 supplies the data stored in the reception register 51b to the ISU 40 along with the read access to the reception register 51b by the ISU 40.

  The control unit 52 includes a mode setting register 52a, a clock generation unit 52b, and an interrupt generation unit 52c. The mode setting register 52a is accessible by the ISU 40 and is a register for setting the operation mode (transmission mode / reception mode) of the SPI 50. For example, the mode setting register 52a is set to “0” when the SPI 50 is set to the transmission mode, and is set to “1” when the SPI 50 is set to the reception mode. The clock generator 52b generates a clock SCK that defines the transition timing of the serial data SO and SI. The interrupt generation unit 52c activates the interrupt signal IRQTS as data is transferred from the transmission register 51a to the shift register 51c in the transmission / reception unit 51, and data is transferred from the shift register 51c to the reception register 51b in the transmission / reception unit 51. As a result, the interrupt signal IRQRS is activated. The control unit 52 instructs the transmission / reception unit 51 to transfer data from the transmission register 51a to the shift register 51c when the SPI 50 is set to the transmission mode by the mode setting register 52a, and the SPI 50 is received by the mode setting register 52a. When the mode is set, the transmission / reception unit 51 is instructed to transfer data from the shift register 51c to the reception register 51b.

  When determining that the first 8-bit command in the serial data SO is a write command, the memory 60 sequentially writes subsequent 16-bit data to 16 memory cells corresponding to the subsequent 16-bit address. Further, when the memory 60 determines that the first 8-bit command in the serial data SO is a read command, the memory 60 reads the data held in 16 memory cells corresponding to the subsequent 16-bit address and sends it to the SPI 50 as serial data SI. Supply sequentially.

  FIG. 2 shows a data transfer operation from the CPU to the memory in the microcomputer of FIG. In the operation of FIG. 2, it is assumed that the number of state transitions when accessing the memory 60 in the SPI 50 is 3, and the transfer data length between the SPI 50 and the memory 60 in the data transmission operation of the SPI 50 is 2 bytes.

  First, the CPU 20 sets a register (such as the transfer setting register 42a) in the ISU 40 by a write access via the system bus BUS (step 101). At this time, in the control unit 42 of the ISU 40, the interrupt setting bit 42c is set to “0”, the transfer sequence setting bit 42d is set to “1”, and the transfer data length setting bit 42e is set to “1”.

  Next, the CPU 20 stores data for setting a register (such as the mode setting register 52a) in the SPI 50 in the transmission buffer 41a in the ISU 40 by write access via the system bus BUS (step 102). When the transmission / reception unit 41 of the ISU 40 recognizes that the data stored in the transmission buffer 41a is data for setting a register in the SPI 50, it sets the register in the SPI 50 by write access using the data ( Step 111). At this time, the mode setting register 52a in the SPI 50 is set to “0”.

  Subsequently, the CPU 20 sequentially stores the command (write command), upper address, lower address, first data, and second data in the transmission buffer 41a in the ISU 40 by write access via the system bus BUS (step S40). 103).

  Then, the CPU 20 sets the transfer start bit 42b in the ISU 40 to “1” by write access via the system bus BUS (step 104). Thereby, the control unit 42 of the ISU 40 sets the counter value CNTA of the state management counter 42f to 3 and sets the counter value CNTB of the transfer count counter 42g to 2, and the transmission / reception unit 41 of the ISU 40 performs write access. The command stored in the transmission buffer 41a is stored in the transmission register 51a in the SPI 50 (step 112). The transmission / reception unit 51 of the SPI 50 transfers the command stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c. The control unit 52 of the SPI 50 In 51, the interrupt signal IRQTS is activated as the command is transferred from the transmission register 51a to the shift register 51c (step 121).

  When the interrupt signal IRQTS is activated, the state management counter 42f in the ISU 40 performs a down-count operation, and the transmission / reception unit 41 of the ISU 40 converts the upper address stored in the transmission buffer 41a in the SPI 50 by write access. The data is stored in the transmission register 51a (step 113). The transmission / reception unit 51 of the SPI 50 transfers the upper address stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c. The control unit 52 of the SPI 50 As the upper address is transferred from the transmission register 51a to the shift register 51c in the unit 51, the interrupt signal IRQTS is activated again (step 122).

  When the interrupt signal IRQTS is activated again, the state management counter 42f in the ISU 40 performs a down-count operation, and the transmission / reception unit 41 of the ISU 40 stores the lower address stored in the transmission buffer 41a in the SPI 50 by write access. Is stored in the transmission register 51a (step 114). The transmission / reception unit 51 of the SPI 50 transfers the lower address stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c. The control unit 52 of the SPI 50 As the lower address is transferred from the transmission register 51a to the shift register 51c in the unit 51, the interrupt signal IRQTS is activated again (step 123).

  When the interrupt signal IRQTS is activated again, the state management counter 42f in the ISU 40 performs a down-count operation, and the transmission / reception unit 41 of the ISU 40 receives the first data stored in the transmission buffer 41a by write access. The data is stored in the transmission register 51a in the SPI 50 (step 115). At this time, the state management counter 42f in the ISU 40 stops the down-counting operation because the counter value CNTA is 0. The transmission / reception unit 51 of the SPI 50 transfers the first data stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c. The control unit 52 of the SPI 50 Then, as the first data is transferred from the transmission register 51a to the shift register 51c in the transmission / reception unit 51, the interrupt signal IRQTS is activated again (step 124).

  When the interrupt signal IRQTS is activated again, the state management counter 42f in the ISU 40 stops the down-counting operation. Therefore, the transfer number counter 42g in the ISU 40 performs the down-counting operation, and the transmission / reception unit 41 of the ISU 40 By the write access, the second data stored in the transmission buffer 41a is stored in the transmission register 51a in the SPI 50 (step 116). The transmission / reception unit 51 of the SPI 50 transfers the second data stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c, and the control unit 52 of the SPI 50 The transmitter / receiver 51 activates the interrupt signal IRQTS again as the second data is transferred from the transmission register 51a to the shift register 51c (step 125).

  When the interrupt signal IRQTS is activated again, the transfer counter 42g in the ISU 40 performs a down-count operation (step 117). At this time, since the counter value CNTB is 0, the transfer count counter 42g in the ISU 40 stops the down-counting operation. The control unit 42 of the ISU 40 activates the interrupt signal IRQT as the transfer number counter 42g stops the down-counting operation (Step 117). When the interrupt signal IRQT is activated, the CPU 20 executes a process of resetting an interrupt flag in the interrupt process (step 105). Thereby, the data transfer from the CPU 20 to the memory 60 is completed.

  FIG. 3 shows a data transfer operation from the memory to the CPU in the microcomputer of FIG. In the operation of FIG. 3, it is assumed that the number of state transitions when accessing the memory 60 in the SPI 50 is 3, and the transfer data length between the SPI 50 and the memory 60 in the data receiving operation of the SPI 50 is 2 bytes.

  First, the CPU 20 sets a register (such as the transfer setting register 42a) in the ISU 40 by a write access via the system bus BUS (step 201). At this time, in the control unit 42 of the ISU 40, the interrupt setting bit 42c is set to “1”, the transfer sequence setting bit 42d is set to “1”, and the transfer data length setting bit 42e is set to “1”.

  Next, the CPU 20 stores data for setting a register (such as the mode setting register 52a) in the SPI 50 in the transmission buffer 41a in the ISU 40 by write access via the system bus BUS (step 202). When the transmission / reception unit 41 of the ISU 40 recognizes that the data stored in the transmission buffer 41a is data for setting a register in the SPI 50, it sets the register in the SPI 50 by write access using the data ( Step 211). At this time, the mode setting register 52a in the SPI 50 is set to “0”.

  Subsequently, the CPU 20 sequentially stores the command (read command), upper address, and lower address in the transmission buffer 41a in the ISU 40 by write access via the system bus BUS (step 203).

  Then, the CPU 20 sets the transfer start bit 42b in the ISU 40 to “1” by write access via the system bus BUS (step 204). Thereby, the control unit 42 of the ISU 40 sets the counter value CNTA of the state management counter 42f to 3 and sets the counter value CNTB of the transfer count counter 42g to 2, and the transmission / reception unit 41 of the ISU 40 performs write access. The command stored in the transmission buffer 41a is stored in the transmission register 51a in the SPI 50 (step 212). The transmission / reception unit 51 of the SPI 50 transfers the command stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c. The control unit 52 of the SPI 50 In 51, the interrupt signal IRQTS is activated as the command is transferred from the transmission register 51a to the shift register 51c (step 221).

  When the interrupt signal IRQTS is activated, the state management counter 42f in the ISU 40 performs a down-count operation, and the transmission / reception unit 41 of the ISU 40 converts the upper address stored in the transmission buffer 41a in the SPI 50 by write access. The data is stored in the transmission register 51a (step 213). The transmission / reception unit 51 of the SPI 50 transfers the upper address stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c. The control unit 52 of the SPI 50 As the upper address is transferred from the transmission register 51a to the shift register 51c in the unit 51, the interrupt signal IRQTS is activated again (step 222).

  When the interrupt signal IRQTS is activated again, the state management counter 42f in the ISU 40 performs a down-count operation, and the transmission / reception unit 41 of the ISU 40 stores the lower address stored in the transmission buffer 41a in the SPI 50 by write access. Is stored in the transmission register 51a (step 214). The transmission / reception unit 51 of the SPI 50 transfers the lower address stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c. The control unit 52 of the SPI 50 As the lower address is transferred from the transmission register 51a to the shift register 51c in the unit 51, the interrupt signal IRQTS is activated again (step 223).

  When the interrupt signal IRQTS is activated again, the state management counter 42f in the ISU 40 performs a down count operation (step 215). At this time, the state management counter 42f in the ISU 40 stops the down-counting operation because the counter value CNTA is 0. Since the counter value CNTA of the state management counter 42f is 0, the transmission / reception unit 41 of the ISU 40 sets the mode setting register 52a in the SPI 50 to “1” by write access in order to switch the operation mode of the SPI 50 from the transmission mode to the reception mode. "(Step 215).

  Thereafter, the transmission / reception unit 51 of the SPI 50 sequentially takes in the serial data SI supplied from the memory 60 by the shift operation of the shift register 51c, and when the 8-bit data is taken into the shift register 51c, it is stored in the transmission register 51a. The received data is transferred to the reception register 51b as the first data, and the control unit 52 of the SPI 50 transmits an interrupt signal as the first data is transferred from the shift register 51c to the reception register 51b in the transmission / reception unit 51. IRQRS is activated (step 224).

  When the interrupt signal IRQRS is activated, the transfer count counter 42g in the ISU 40 performs a down-counting operation, and the transmission / reception unit 41 of the ISU 40 performs the first access stored in the reception register 51b in the SPI 50 by read access. Data is stored in the reception buffer 41b (step 216).

  The transmission / reception unit 51 of the SPI 50 sequentially takes in the serial data SI supplied from the memory 60 by the shift operation of the shift register 51c, and when the 8-bit data is taken into the shift register 51c, it is stored in the transmission register 51a. The received data is transferred to the reception register 51b as the second data, and the control unit 52 of the SPI 50 transmits the interrupt signal IRQRS as the second data is transferred from the shift register 51c to the reception register 51b in the transmission / reception unit 51. Is activated again (step 225).

  When the interrupt signal IRQRS is activated again, the transfer count counter 42g in the ISU 40 performs a down-count operation, and the transmission / reception unit 41 of the ISU 40 performs the second access stored in the reception register 51b in the SPI 50 by read access. Are stored in the reception buffer 41b (step 217). At this time, since the counter value CNTB is 0, the transfer count counter 42g in the ISU 40 stops the down-counting operation. The control unit 42 of the ISU 40 activates the interrupt signal IRQR as the transfer number counter 42g stops the down-counting operation (Step 217).

  When the interrupt signal IRQR is activated, the CPU 20 executes a process for resetting an interrupt flag in the interrupt process, and then stores the 1 stored in the reception buffer 41b in the ISU 40 by a read access via the system bus BUS. The first data and the second data are obtained sequentially (step 205). Thereby, the data transfer from the memory 60 to the CPU 20 is completed.

  FIG. 4 shows the data transfer operation from the CPU to the memory in the conventional microcomputer. Note that the conventional microcomputer is the same as the microcomputer 10 of FIG. 1, except that the ISU 40 is removed, the interrupt signals IRQTS and IRQRS are supplied to the interrupt controller 30 instead of the interrupt signals IRQT and IRQR, and the SPI 50 is connected to the system bus BUS. It is configured as follows. In the operation of FIG. 4, it is assumed that the number of state transitions when accessing the memory 60 in the SPI 50 is 3, and the transfer data length between the SPI 50 and the memory 60 in the data transmission operation of the SPI 50 is 2 bytes.

  First, the CPU 20 sets a register (such as a mode setting register 52a) in the SPI 50 by a write access via the system bus BUS (step 301). At this time, the mode setting register 52a in the SPI 50 is set to “0”.

  Then, the CPU 20 stores the command (write command) in the transmission register 51a in the SPI 50 by write access via the system bus BUS (step 302). The transmission / reception unit 51 of the SPI 50 transfers the command stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c. The control unit 52 of the SPI 50 In 51, the interrupt signal IRQTS is activated as the command is transferred from the transmission register 51a to the shift register 51c (step 321).

  When the interrupt signal IRQTS is activated, the CPU 20 executes processing for resetting the interrupt flag in the interrupt processing, and then stores the upper address in the transmission register 51a in the SPI 50 by write access via the system bus BUS. (Step 303). The transmission / reception unit 51 of the SPI 50 transfers the upper address stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c. The control unit 52 of the SPI 50 As the higher address is transferred from the transmission register 51a to the shift register 51c in the unit 51, the interrupt signal IRQTS is activated again (step 322).

  When the interrupt signal IRQTS is activated again, the CPU 20 executes a process for resetting an interrupt flag in the interrupt process, and then writes a lower address to the transmission register 51a in the SPI 50 by a write access via the system bus BUS. Store (step 304). The transmission / reception unit 51 of the SPI 50 transfers the lower address stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c. The control unit 52 of the SPI 50 As the lower address is transferred from the transmission register 51a to the shift register 51c in the unit 51, the interrupt signal IRQTS is activated again (step 323).

  When the interrupt signal IRQTS is activated again, the CPU 20 executes processing for resetting an interrupt flag in the interrupt processing, and then writes the first data to the transmission register in the SPI 50 by write access via the system bus BUS. 51a is stored (step 305). The transmission / reception unit 51 of the SPI 50 transfers the first data stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c. The control unit 52 of the SPI 50 Then, as the first data is transferred from the transmission register 51a to the shift register 51c in the transmission / reception unit 51, the interrupt signal IRQTS is activated again (step 324).

  When the interrupt signal IRQTS is activated again, the CPU 20 executes processing for resetting the interrupt flag in the interrupt processing, and then transfers the second data to the transmission register in the SPI 50 by write access via the system bus BUS. 51a is stored (step 306). The transmission / reception unit 51 of the SPI 50 transfers the second data stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c, and the control unit 52 of the SPI 50 As the second data is transferred from the transmission register 51a to the shift register 51c in the transmission / reception unit 51, the interrupt signal IRQTS is activated again (step 325).

  When the interrupt signal IRQTS is activated again, the CPU 20 executes a process of resetting an interrupt flag in the interrupt process (step 307). Thereby, the data transfer from the CPU 20 to the memory 60 is completed.

  FIG. 5 shows a data transfer operation from a CPU to a memory in a conventional microcomputer. In the operation of FIG. 5, it is assumed that the number of state transitions when accessing the memory 60 in the SPI 50 is 3, and the transfer data length between the SPI 50 and the memory 60 in the data receiving operation of the SPI 50 is 2 bytes.

  First, the CPU 20 sets a register (such as a mode setting register 52a) in the SPI 50 by a write access via the system bus BUS (step 401). At this time, the mode setting register 52a in the SPI 50 is set to “0”.

  Then, the CPU 20 stores the command (read command) in the transmission register 51a in the SPI 50 by write access via the system bus BUS (step 402). The transmission / reception unit 51 of the SPI 50 transfers the command stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c. The control unit 52 of the SPI 50 In 51, the interrupt signal IRQTS is activated as the command is transferred from the transmission register 51a to the shift register 51c (step 421).

  When the interrupt signal IRQTS is activated, the CPU 20 executes processing for resetting the interrupt flag in the interrupt processing, and then stores the upper address in the transmission register 51a in the SPI 50 by write access via the system bus BUS. (Step 403). The transmission / reception unit 51 of the SPI 50 transfers the upper address stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c. The control unit 52 of the SPI 50 As the higher address is transferred from the transmission register 51a to the shift register 51c in the unit 51, the interrupt signal IRQTS is activated again (step 422).

  When the interrupt signal IRQTS is activated again, the CPU 20 executes a process for resetting an interrupt flag in the interrupt process, and then writes a lower address to the transmission register 51a in the SPI 50 by a write access via the system bus BUS. Store (step 404). The transmission / reception unit 51 of the SPI 50 transfers the lower address stored in the transmission register 51a to the shift register 51c and sequentially transmits it to the memory 60 as serial data SO by the shift operation of the shift register 51c. The control unit 52 of the SPI 50 As the lower address is transferred from the transmission register 51a to the shift register 51c in the unit 51, the interrupt signal IRQTS is activated again (step 423).

  When the interrupt signal IRQTS is activated again, the CPU 20 executes processing for resetting the interrupt flag in the interrupt processing, and then switches the operation mode of the SPI 50 from the transmission mode to the reception mode via the system bus BUS. As a result of the write access, the mode setting register 52a in the SPI 50 is set to “1” (step 405).

  Thereafter, the transmission / reception unit 51 of the SPI 50 sequentially takes in the serial data SI supplied from the memory 60 by the shift operation of the shift register 51c, and when the 8-bit data is taken into the shift register 51c, it is stored in the transmission register 51a. The received data is transferred to the reception register 51b as the first data, and the control unit 52 of the SPI 50 transmits an interrupt signal as the first data is transferred from the shift register 51c to the reception register 51b in the transmission / reception unit 51. IRQRS is activated (step 424).

  When the interrupt signal IRQRS is activated, the CPU 20 executes a process of resetting an interrupt flag in the interrupt process, and then stores 1 stored in the reception register 51b in the SPI 50 by read access via the system bus BUS. The second data is acquired (step 406).

  The transmission / reception unit 51 of the SPI 50 sequentially takes in the serial data SI supplied from the memory 60 by the shift operation of the shift register 51c, and when the 8-bit data is taken into the shift register 51c, it is stored in the transmission register 51a. The received data is transferred to the reception register 51b as the second data, and the control unit 52 of the SPI 50 transmits the interrupt signal IRQRS as the second data is transferred from the shift register 51c to the reception register 51b in the transmission / reception unit 51. Is activated again (step 425).

  When the interrupt signal IRQRS is activated again, the CPU 20 executes a process for resetting an interrupt flag in the interrupt process, and then stored in the reception register 51b in the SPI 50 by a read access via the system bus BUS. Second data is acquired (step 407). Thereby, the data transfer from the memory 60 to the CPU 20 is completed.

  As described above, in the conventional microcomputer, all interrupt requests issued by the SPI 50 are notified to the CPU 20 (interrupt controller 30) when transferring data between the CPU 20 and the memory 60, so the CPU 20 performs interrupt processing. Must be carried out 5 times. For this reason, the CPU 20 cannot concentrate on the processing that should be originally executed, and the processing efficiency of the CPU 20 is significantly reduced. On the other hand, in the microcomputer 10 (FIG. 1) according to the embodiment of the present invention, the interrupt request issued by the SPI 50 is managed by the ISU 40 during the data transfer between the CPU 20 and the memory 60. Only the interrupt request issued to the CPU 20 is notified to the CPU 20 (interrupt controller 30), so the CPU 20 only needs to execute the interrupt process once. For this reason, the CPU 20 can be devoted to the processing to be originally executed, and the processing efficiency of the CPU 20 can be greatly improved. Further, since it is not necessary to change the interface portion in the CPU 20, the interrupt controller 30 and the SPI 50 with the installation of the ISU 40, the processing efficiency of the CPU 20 can be easily improved.

  Although the present invention has been described in detail above, the above-described embodiment is merely an example of the present invention, and the present invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.

It is explanatory drawing which shows one Embodiment of this invention. It is explanatory drawing which shows the data transfer operation | movement from CPU to memory in the microcomputer of FIG. It is explanatory drawing which shows the data transfer operation | movement from memory to CPU in the microcomputer of FIG. It is explanatory drawing which shows the data transfer operation | movement from CPU to memory in the conventional microcomputer. It is explanatory drawing which shows the data transfer operation | movement from memory to CPU in the conventional microcomputer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Microcomputer; 20 ... CPU; 30 ... Interrupt controller; 40 ... ISU; 41 ... Transmission / reception part; 41a ... Transmission buffer; 41b ... Reception buffer; 42 ... Control part; 42a ... Transfer setting register; 42c. Interrupt setting bit; 42d Transfer sequence setting bit; 42e Transfer data length setting bit; 42f State management counter; 42g Transfer count counter; 50 SPI; 51 Transmission / reception unit; Register 51c Shift register 52 Control unit 52a Mode setting register 52b Clock generation unit 52c Interrupt generation unit 60 Memory BUS System bus IRQR, IRQRS, IRQT, IRQTS Interrupt signal; SCK: Clock; SI, S ‥ serial data

Claims (5)

An interrupt management mechanism for managing an interrupt request of the serial interface in a microcomputer in which data transfer between a CPU and a memory is performed via a serial interface,
As the serial interface issues an interrupt request, a state transition circuit whose state transitions according to the type of interrupt request and the number of times it is issued,
An interrupt management mechanism comprising: an interrupt request issuance circuit that issues an interrupt request to the CPU when the state transition circuit transits to a predetermined state. In the interrupt management mechanism according to claim 1,
The state transition circuit includes:
A first register holding information indicating the number of state transitions when accessing the memory in the serial interface;
A second register for holding information indicating the number of times of data transfer at the time of accessing the memory in the serial interface;
A first counter that counts the number of times an interrupt request is issued in accordance with the state transition of the serial interface;
A second counter that counts the number of issuance of interrupt requests accompanying data transfer of the serial interface after the count operation of the first counter is performed a number of times corresponding to the information in the first register;
The interrupt request issuing circuit issues an interrupt request to the CPU as the count operation of the second counter is performed a number of times corresponding to information in the second register. In the interrupt management mechanism according to claim 2,
The interrupt request accompanying data transfer of the serial interface includes a first interrupt request accompanying data transfer from the serial interface to the memory, and a second interrupt request accompanying data transfer from the memory to the serial interface,
The state transition circuit includes a third register that holds information indicating either the first interrupt request or the second interrupt request,
The interrupt management mechanism, wherein the second counter counts the number of times an interrupt request corresponding to information in the third register is issued in the first interrupt request and the second interrupt request. In the interrupt management mechanism according to claim 1,
A first buffer that stores output data of the CPU in response to a write request of the CPU and outputs the stored data to the serial interface according to a state of the state transition circuit;
An interrupt management mechanism comprising: a second buffer for storing output data of the serial interface according to a state of the state transition circuit and outputting the stored data to the CPU in response to a read request of the CPU . A microcomputer in which data transfer between a CPU and a memory is performed via a serial interface,
A microcomputer comprising the interrupt management mechanism according to any one of claims 1 to 4.

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