JP2012003325A - Computer system and interruption request processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the processing efficiency of a central processing unit by reducing loads put on the interruption processing of the central processing unit.SOLUTION: In a computer system 100, an interruption request processor M receives an interruption request notifying the end of predetermined processing outputted from a device D. The interruption request processor M determines whether or not the number of times of receiving the interruption request from the device D matches with a predetermined number F of times. The interruption request processor M outputs the execution request of the predetermined processing to the device D until the number of times of receiving the interruption request from the device D reaches the predetermined number F of times. When the number of times of receiving the interruption request from the device D matches with the predetermined number F of times, the interruption request processor M outputs the interruption request to a CPU 101.

Description

  The present invention relates to a computer system and an interrupt request processing method for processing an interrupt request from a device to a central processing unit.

  In a computer system, when a central processing unit accepts an interrupt request from a device, the central processing unit interrupts the program being executed, saves information for restarting the program to memory, and stores an interrupt processing program such as an interrupt handler. call. When the interrupt processing by the interrupt handler ends, the central processing unit resumes execution of the program based on the information saved in the memory.

  Conventionally, there are various techniques for interrupting a central processing unit in a computer system. For example, in an interrupt generation circuit in an integrated circuit device having a plurality of processor cores, there is a technique for preventing malfunctions when interrupt operations are performed in cooperation between processors by preventing occurrence of continuous interrupts in a short time. (For example, see Patent Document 1 below.) Also, in a multiprocessor system, there is a technique for transferring an interrupt request and interrupt information using a bus dedicated to interrupt that is different from a data transfer bus in order to prevent a decrease in data transfer throughput (for example, the following patent document) 2).

JP 2006-350435 A Japanese Patent Publication No.8-7694

  However, according to the above-described prior art, when the frequency of interrupts from the device to the central processing unit increases, software processing such as interrupt handlers increases, the load on the central processing unit interrupt processing increases and the processing efficiency decreases. There is a problem of inviting.

  In order to solve the above-described problems caused by the prior art, the present invention reduces the load on the interrupt processing of the central processing unit and can improve the processing efficiency of the central processing unit and interrupt request processing. It aims to provide a method.

  In order to solve the above-described problems and achieve the object, the disclosed computer system issues an execution request to devices that can communicate with each other via a bus, and notifies the end of predetermined processing from the device. A central processing unit that receives an interrupt request and executes an interrupt process, a device that notifies the end of the predetermined process executed in response to the execution request by outputting the interrupt request, and an output from the device A reception unit that receives the interrupt request; a determination unit that determines whether the number of receptions of the interrupt request from the device by the reception unit matches a predetermined number of times; and the number of times the interrupt request is received by the determination unit Until the number of times the interrupt request is accepted reaches the predetermined number. And an output unit which outputs the execution request to the device.

  Further, in order to solve the above-described problems and achieve the object, the disclosed interrupt request processing method outputs an interrupt request indicating the end of a predetermined process executed in response to an execution request from the central processing unit. The interrupt request is received from the notifying device, and it is determined whether or not the number of times the interrupt request is received from the device matches a predetermined number, and whether or not the number of times the interrupt request is received matches the predetermined number As a result of the determination, the execution request is output to the device until the number of received interrupt requests reaches the predetermined number.

  According to the computer system and the interrupt request processing method, it is possible to reduce the load applied to the interrupt processing of the central processing unit and improve the processing efficiency of the central processing unit.

1 is an explanatory diagram illustrating a computer system according to a first embodiment; FIG. 3 is an explanatory diagram of a computer system according to a second embodiment. It is explanatory drawing which shows an example of the memory content of a setting table. FIG. 6 is a block diagram illustrating an interrupt request processing device according to a second exemplary embodiment; FIG. 10 is a sequence diagram illustrating a processing procedure of the computer system according to the second embodiment. 6 is a timing chart showing an example of operation timing of the interrupt request processing device according to the second exemplary embodiment; 10 is a flowchart illustrating an example of an interrupt request processing procedure of the interrupt request processing device according to the second exemplary embodiment; FIG. 10 is an explanatory diagram of an example of a computer system according to a second embodiment; FIG. 10 is a sequence diagram illustrating an example of a processing procedure of the computer system according to the second exemplary embodiment. FIG. 9 is an explanatory diagram of a computer system according to a third embodiment.

  Exemplary embodiments of a computer system and an interrupt request processing method according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment 1)
FIG. 1 is an explanatory diagram of a computer system according to the first embodiment. In FIG. 1, a computer system 100 includes a CPU (Central Processing Unit) 101, a device D, and an interrupt request processing device M. In the computer system 100, the CPU 101, the device D, and the interrupt request processing device M are connected to each other via a bus 110 so as to communicate with each other.

  The CPU 101 is a central processing unit that controls the computer system 100. The CPU 101 receives an interrupt request from the device D and executes interrupt processing. Here, the interrupt request is, for example, a signal output to the CPU 101 when the device D satisfies a certain state or a specific condition.

  The device D is hardware that realizes a predetermined function, and is, for example, a module that includes an I / O (Input / Output) device and an interface. For example, the device D notifies the end of predetermined processing by outputting an interrupt request to the CPU 101. The predetermined process is a process for realizing the function of the device D. Examples of the device D include a memory controller, a DMAC (Direct Memory Access Controller), a magnetic disk, and an optical disk.

  The interrupt request processing device M processes an interrupt request output from the device D to the CPU 101. Here, some interrupt processes performed by the CPU 101 in response to an interrupt request from the device D include those that need to be performed via the CPU 101 and those that do not need to be performed via the CPU 101.

  For example, the CPU 101 may repeatedly execute an execution request to the device D to cause the device D to execute a predetermined process a plurality of times. In this case, the device D outputs an interrupt request for notifying the end of the predetermined process to the CPU 101 each time the predetermined process ends. The CPU 101 executes an interrupt process each time an interrupt request is received from the device D.

  Specifically, for example, when the CPU 101 receives an interrupt request from the device D, the CPU 101 interrupts processing of the program being executed, saves information for resuming the program to the memory, and stores an interrupt handler or the like. Call the interrupt processing program. That is, when the CPU 101 causes the device D to repeatedly execute a predetermined process F times, the CPU 101 performs software processing such as an interrupt handler F times.

  At this time, the interrupt handler analyzes the interrupt factor, clears the interrupt factor of device D, and issues an execution request to device D for the first to (F-1) interrupt requests of device D. . In response to the F-th interrupt request, for example, the interrupt handler makes an execution reservation of a program for performing another process using the execution result of a predetermined process repeated F times.

  Among such interrupt handler processes, the process for the last (F-th) interrupt request such as making a program execution reservation needs to be performed via the CPU 101. On the other hand, it is not necessary to perform processing for the interrupt request from the first time (F-1) when simply requesting execution of the predetermined processing to the device D via the CPU 101.

  However, even a process for simply executing an execution request to the device D requires several hundred cycles, so that the load on the CPU 101 increases when the interrupt frequency to the CPU 101 increases. In addition, when the CPU 101 accepts an interrupt request, it interrupts the program being executed and performs interrupt processing. Therefore, if the interrupt frequency for the CPU 101 increases, the CPU 101 cannot concentrate on the processing that should be executed, and the processing efficiency of the CPU 101 decreases. End up.

  Therefore, the computer system 100 according to the first embodiment includes an interrupt request processing device M that intercepts an interrupt request from the device D that the CPU 101 does not necessarily have to participate in and processes the interrupt request instead of the CPU 101. Hereinafter, a processing procedure of the interrupt request processing device M when the device D is caused to repeatedly execute a predetermined process F times will be described. Note that the CPU 101 may directly notify the device D of the first execution request to the device D, or the CPU 101 may notify the device D via the interrupt request processing device M.

  (1) The interrupt request processing apparatus M receives an interrupt request for notifying the end of predetermined processing output from the device D. That is, the interrupt request processing apparatus M receives an interrupt request that is originally notified directly from the device D to the CPU 101 prior to the notification to the CPU 101.

  (2) The interrupt request processing device M determines whether or not the number of interrupt requests received from the device D matches the predetermined number F. Here, the predetermined number of times F is the number of times that the device D repeatedly executes a predetermined process, and is arbitrarily set in advance.

  (3) The interrupt request processing apparatus M outputs an execution request for a predetermined process to the device D until the number of times the interrupt request is received from the device D reaches the predetermined number F. That is, the process of simply executing a predetermined process execution request to the device D does not need to be performed via the CPU 101, so the interrupt request processing apparatus M performs the process instead of the CPU 101.

  (4) As a result of repeating the above (1) to (3), the interrupt request processing device M interrupts the CPU 101 when it is determined that the number of interrupt requests received from the device D matches the predetermined number F. Output the request. That is, since the processing for the F-th interrupt request needs to be performed via the CPU 101, the CPU 101 is notified of the interrupt request from the device D.

  As described above, according to the computer system 100 according to the first embodiment, among the interrupt requests from the device D to the CPU 101, an interrupt request that does not require the CPU 101 to be directly involved is sent to the interrupt request processing device M. Can be processed. That is, when the device D repeatedly executes a predetermined process multiple times, after the CPU 101 makes an initial execution request to the device D, the device D executes the predetermined process multiple times without going through the CPU 101. Can be made. Further, since only the last interrupt request from the device D is notified to the CPU 101, the interrupt processing performed by the CPU 101 is one time. As a result, interrupt processing of the CPU 101 such as interrupting a program being executed and calling an interrupt handler can be reduced, and the load on the interrupt processing of the CPU 101 can be reduced and the processing efficiency of the CPU 101 can be improved. it can.

(Embodiment 2)
FIG. 2 is an explanatory diagram of a computer system according to the second embodiment. Note that description of portions similar to those described in the first embodiment is omitted. 2, the computer system 200 includes a CPU 201, a ROM (Read-Only Memory) 202, a RAM 203, an interrupt controller 204, devices D1 to Dn, and interrupt request processing devices M1 to Mn. In the computer system 200, the CPU 201, the ROM 202, the RAM 203, the interrupt controller 204, the devices D1 to Dn, and the interrupt request processing devices M1 to Mn are connected via a bus 210 so as to communicate with each other.

  The CPU 201 is a central processing unit that controls the computer system 200. The CPU 201 receives an interrupt request from the devices D1 to Dn via the interrupt controller 204 and executes interrupt processing. The ROM 202 stores various programs such as a boot program and an interrupt processing program. The RAM 203 is used as a work area for the CPU 201.

  The interrupt controller 204 receives interrupt requests from the devices D1 to Dn to the CPU 201 from the interrupt request processing devices M1 to Mn and notifies the CPU 201 of them. Specifically, for example, the interrupt controller 204 has an interrupt status register and an interrupt mask register for each interrupt factor of each device D1 to Dn. The interrupt status register is a register that holds the state of the interrupt factor. The interrupt mask register is a register that holds information indicating whether or not an interrupt to the CPU 201 is enabled.

  When an interrupt factor is asserted, the interrupt controller 204 stores the state of the factor in an interrupt status register corresponding to the interrupt factor. Then, the interrupt controller 204 outputs an interrupt request to the CPU 201 when the interrupt mask register corresponding to the interrupt factor is enabled. At this time, the interrupt controller 204 outputs an interrupt vector corresponding to the interrupt factor to the CPU 201. An interrupt vector is information for starting an interrupt processing program corresponding to an interrupt factor. The CPU 201 refers to the interrupt vector received together with the interrupt request and calls an interrupt processing program such as an interrupt handler.

  The devices D1 to Dn are modules such as a memory controller including an I / O device and an interface, a DMAC, an encoder, a decoder, a magnetic disk, and an optical disk, for example. The interrupt request processing devices M1 to Mn are mounted on the devices D1 to Dn, respectively. Each of the interrupt request processing devices M1 to Mn accepts and processes an interrupt request to the CPU 201 from each device D1 to Dn.

  Here, the initial setting performed by the CPU 201 in the computer system 200 will be described. The CPU 201 performs initial setting of the interrupt controller 204. Specifically, for example, the CPU 201 sets an interrupt vector corresponding to an interrupt factor, an interrupt request priority order, and the like in the interrupt controller 204. The priority order is information that determines the order in which interrupt requests are received when a plurality of interrupt requests occur simultaneously or when multiple interrupts occur.

  Further, the CPU 201 performs initial setting of the devices D1 to Dn. Specifically, the CPU 201 sets information necessary for each device D1 to Dn to execute a predetermined process in each device D1 to Dn. Specifically, for example, when performing data transfer between devices, the CPU 201 sends command contents such as a read command and a write command, a read destination and a write destination address, a transfer data amount, and the like to the devices D1 to Dn to be executed. Set.

  In addition, the CPU 201 performs initial setting of the interrupt request processing devices M1 to Mn. Specifically, for example, the CPU 201 performs initial setting of the interrupt request processing devices M1 to Mn with reference to the setting table 300 illustrated in FIG. Here, the contents stored in the setting table 300 will be described.

  FIG. 3 is an explanatory diagram showing an example of the contents stored in the setting table. In FIG. 3, the setting table 300 has fields for macro name, number register value, and ID register value. By setting information in each field, setting data 300-1 to 300-n are stored as records. Yes.

  Here, the macro name is the name of each interrupt request processing device M1 to Mn. The count register value is a register value of the count register R2 (see FIG. 4 described later) included in each interrupt request processing device M1 to Mn. The number register R2 is a register that stores the number of times each device D1 to Dn repeatedly executes a predetermined process.

  The ID register value is a register value of an ID register R3 (see FIG. 4 described later) included in each interrupt request processing device M1 to Mn. The ID register R3 is a register that stores an identifier of any one of the interrupt controller 204 and the interrupt request processing devices M1 to Mn. However, the ID register value “0xFFFFFFFF” is an identifier of the interrupt controller 204.

  As an example, taking the interrupt request processing device M1 as an example, the CPU 201 refers to the setting data 300-1, sets “F1” in the number register R2 of the interrupt request processing device M1, and stores it in the ID register R3. “0x00000001” is set. The setting table 300 is stored, for example, in the ROM 202 shown in FIG.

  In the following description, an arbitrary device among a plurality of devices D1 to Dn is denoted as “device Di” (i = 1, 2,..., N). An arbitrary interrupt request processing device among the plurality of interrupt request processing devices M1 to Mn is referred to as “interrupt request processing device Mi”. Further, among the plurality of devices D1 to Dn, another device different from the device Di is expressed as “device Dj” (j ≠ i, j = 1, 2,..., N). Further, among the plurality of interrupt request processing devices M1 to Mn, another interrupt request processing device different from the interrupt request processing device Mi is referred to as “interrupt request processing device Mj”.

(Functional configuration of interrupt request processing device Mi)
Next, a functional configuration of the interrupt request processing device Mi according to the second embodiment will be described. FIG. 4 is a block diagram of the interrupt request processing device according to the second embodiment. In FIG. 4, the interrupt request processing device Mi is configured to include a reception unit 401, a determination unit 402, an output unit 403, a counter 404, a number determination unit 405, and an ID determination unit 406. Each functional unit (accepting unit 401 to ID determining unit 406) is realized by, for example, a circuit for realizing each function. Specifically, for example, it can be realized by a state machine that realizes the functions of the respective functional units (receiving unit 401 to ID determining unit 406).

  The accepting unit 401 accepts an execution request for a predetermined process for the device Di from the CPU 201. Specifically, for example, the reception unit 401 receives from the CPU 201 a control signal for setting the value of the enable register R1 to assert via the bus 210. Here, the enable register R1 is a register that holds information indicating whether an execution request for a predetermined process for the device Di is valid. When the enable register R1 is asserted, it indicates that the execution request for the device Di is valid. On the other hand, if the enable register R1 is negated, it indicates that the execution request for the device Di is invalid.

  The accepting unit 401 accepts an execution request for a predetermined process for the device Di from another interrupt request processing device Mj. Specifically, for example, the accepting unit 401 accepts a ready signal via the bus 210 as an execution request for a predetermined process for the device Di. When the accepting unit 401 accepts an execution request for the device Di, the value of the enable register R1 is set to assert.

  The determination unit 402 determines whether an execution request for a predetermined process for the device Di is valid. Specifically, for example, when the enable register R1 is asserted, the determination unit 402 determines that the execution request for the device Di is valid. On the other hand, when the enable register R1 is negated, the determination unit 402 determines that the execution request for the device Di is invalid.

  Further, the determination unit 402 may determine whether or not the wait instruction is valid when the execution request for the predetermined process for the device Di is valid. Here, the wait instruction is for causing the device Di to wait until the preparation of another device Dj operating in conjunction with the device Di is completed.

  Specifically, for example, the determination unit 402 determines that the wait instruction is valid while the wait signal from another device Dj received by the reception unit 401 is asserted. On the other hand, when the wait signal from the other device Dj is negated, the determination unit 402 determines that the wait instruction is invalid. The wait signal from the other device Dj may be received directly from the other device Dj by the receiving unit 401 or may be received from the other device Dj via the device Di.

  Further, the determination unit 402 may determine that the wait instruction is valid until a predetermined time T has elapsed after the value of the enable register R1 is set to assert. Here, the fixed time T is a time taken until the preparation of the other device Dj is completed, and is set in advance. The determination unit 402 determines that the wait instruction is invalid when a predetermined time T has elapsed after the value of the enable register R1 is set to assert.

  When the determination unit 402 determines that the predetermined process execution request for the device Di is valid, the output unit 403 outputs the predetermined process execution request to the device Di. The output unit 403 may also output a predetermined process execution request to the device Di when it is determined that the predetermined process execution request for the device Di is valid and the wait instruction is invalid. Good. Thereby, after the preparation of another device Dj that operates in conjunction with the device Di is completed, an execution request for a predetermined process can be made to the device Di.

  Specifically, for example, the output unit 403 outputs a request for executing a predetermined process to the main function unit 410 of the device Di. Here, the main function unit 410 is a function unit of the device Di that executes a predetermined process, and notifies the CPU 201 of an interrupt request via the interrupt controller when the predetermined process ends. When the execution request for the predetermined process is output to the main function unit 410, the main function unit 410 executes the predetermined process.

  The accepting unit 401 accepts an interrupt request notified from the device Di to the CPU 201 via the interrupt controller prior to the notification to the CPU 201. Specifically, for example, the accepting unit 401 accepts an interrupt request output from the main function unit 410 of the device Di using an interrupt signal line that directly connects the interrupt request processing device Mi and the device Di.

  The counter 404 counts the number of times that the interrupt request is received by the receiving unit 401. Specifically, for example, each time the counter 404 receives an interrupt request by the receiving unit 401, the counter value is incremented to count the number of times the interrupt request has been received.

  The number determination unit 405 determines whether or not the number of times the interrupt request has been received matches the predetermined number Fi. Here, the predetermined number Fi is the number of times that the device Di repeatedly executes a predetermined process. The predetermined number Fi is preset as a register value of the number register R2. Specifically, for example, the number determination unit 405 determines whether or not the register value of the number register R2 matches the count value of the counter 404.

  The output unit 403 outputs a predetermined process execution request to the device Di until the number of times the interrupt request is received by the number determination unit 405 reaches the predetermined number Fi. Specifically, for example, when the register value of the number register R2 and the count value of the counter 404 do not match, the output unit 403 outputs a predetermined process execution request to the main function unit 410.

  Further, the output unit 403 may output an interrupt factor clear instruction to the main function unit 410 prior to outputting a request for executing a predetermined process. When receiving the interrupt factor clear instruction, the main function unit 410 changes the value of the interrupt factor bit and clears the interrupt factor. Thereby, it is possible to prevent an interrupt request from the device Di from being repeatedly generated.

  The ID determination unit 406 determines whether or not to notify the CPU 201 of the interrupt request when the number of times the interrupt request is received by the number determination unit 405 is determined to match the predetermined number Fi. Specifically, for example, the ID determination unit 406 determines whether or not the register value of the ID register R3 matches the identifier of the interrupt controller 204.

  If the register value of the ID register R3 matches the identifier of the interrupt controller 204, the ID determination unit 406 determines to notify the CPU 201 of an interrupt request. On the other hand, if the register value of the ID register R3 does not match the identifier of the interrupt controller 204, the ID determination unit 406 determines not to notify the CPU 201 of an interrupt request.

  Here, the identifier of the interrupt controller 204 is set to “0xFFFFFFFF”. For this reason, the ID determination unit 406 may determine that the identifier of the interrupt controller 204 matches when the logical product (AND) of the register values of the ID register R3 is “1”. On the other hand, when the logical product of the register values of the ID register R3 is “0”, the ID determination unit 406 determines that it does not match the identifier of the interrupt controller 204.

  Further, a storage device for storing the identifier of the interrupt controller 204 may be provided inside the interrupt request processing device Mi. In this case, the ID determination unit 406 compares the register value of the ID register R3 with the identifier stored in the storage device, and determines whether or not the identifier matches the identifier of the interrupt controller 204.

  When the number of times the interrupt request is received by the number determination unit 405 is determined to match the predetermined number Fi, the value of the enable register R1 is set to the negate by the determination unit 402. As a result, it is possible to prevent an execution request from the interrupt request processing device Mi to the device Di after the device Di repeatedly executes a predetermined process Fi times.

  The output unit 403 outputs an interrupt request from the device Di to the CPU 201 to the interrupt controller 204 when the ID determination unit 406 determines to notify the CPU 201 of an interrupt request. Specifically, for example, the output unit 403 outputs an interrupt request from the device Di using an interrupt signal line that directly connects the interrupt request processing device Mi and the interrupt controller 204.

  When the interrupt controller 204 receives an interrupt request of the device Di from the interrupt request processing device Mi, the interrupt controller 204 outputs an interrupt vector corresponding to the interrupt factor of the device Di together with the interrupt request of the device Di to the CPU 201. Thereby, the CPU 201 can be notified of an interrupt request that needs to be processed via the CPU 201.

  Further, when the ID determination unit 406 determines that the interrupt request is not notified to the CPU 201, the output unit 403 outputs an execution request for a predetermined process to another device Dj. Specifically, for example, the output unit 403 outputs an execution request for a predetermined process for the device Dj to another interrupt request processing device Mj identified from the register value of the ID register R3.

  More specifically, for example, the output unit 403 outputs a valid signal to the bus 210 and outputs a register value of the ID register R3. As a result, the ready signal is output to the other interrupt request processing device Mj identified from the register value of the ID register R3 by the bus 210.

  Then, when the other interrupt request processing device Mj receives the ready signal from the bus 210, it outputs an execution request for a predetermined process to the device Dj. In this way, by setting the identifier of the interrupt request processing device Mj mounted on the other device Dj to be operated next to the device Di in the ID register R3, the plurality of devices D1 to Dn can be set in an arbitrary sequence. Can be operated according to.

  In the above description, the interrupt request from the device Di is notified to the CPU 201 via the interrupt controller 204. However, the present invention is not limited to this. Specifically, for example, the output unit 403 may directly output an interrupt request from the device Di to the CPU 201 using an interrupt signal line that directly connects the CPU 201 and the interrupt request processing device Mi. .

  In the above description, the interrupt request processing device Mi outputs an interrupt factor clear instruction to the device Di to cause the device Di to clear the interrupt factor. However, the present invention is not limited to this. Specifically, for example, when the device Di receives an execution request for a predetermined process, the interrupt factor may be autonomously cleared.

(Processing procedure of computer system 200)
Next, a processing procedure of the computer system 200 according to the second embodiment will be described. Here, the identifier of the interrupt request processing device Mj is held in the ID register R3 of the interrupt request processing device Mi, and the identifier of the interrupt controller 204 is held in the ID register R3 of the interrupt request processing device Mj. A case will be described as an example.

  FIG. 5 is a sequence diagram of the processing procedure of the computer system according to the second embodiment. In the sequence diagram of FIG. 5, (1) the CPU 201 performs initial setting of the interrupt controller 204, the interrupt request processing devices Mi and Mj, and the devices Di and Dj. (2) The CPU 201 outputs an execution request for the device Di to the interrupt request processing device Mi. (3) The CPU 201 starts executing an arbitrary program.

  (4) Upon receiving an execution request for the device Di, the interrupt request processing device Mi outputs an execution request to the device Di. (5) Upon receiving an execution request from the interrupt request processing device Mi, the device Di executes a predetermined process. (6) The interrupt request processing device Mi receives from the device Di an interrupt request to the CPU 201 for notifying the end of predetermined processing.

  (7) The interrupt request processing device Mi clears the interrupt factor of the device Di and outputs an execution request to the device Di until the number of times the interrupt request is received from the device Di reaches Fi. (8) When the number of times that the interrupt request is received from the device Di reaches Fi times, the interrupt request processing device Mi clears the interrupt factor of the device Di and sends an execution request for the other device Dj to another interrupt request. Output to the processing device Mj.

  (9) When receiving an execution request for the device Dj from the interrupt request processing device Mi, the interrupt request processing device Mj outputs an execution request to the device Dj. (10) When the device Dj receives an execution request from the interrupt request processing device Mj, the device Dj executes a predetermined process. (11) The interrupt request processing device Mj receives from the device Dj an interrupt request to the CPU 201 for notifying the end of predetermined processing.

  (12) The interrupt request processing device Mj clears the interrupt factor of the device Dj and outputs an execution request to the device Dj until the number of interrupt requests received from the device Dj reaches Fj. (13) When the number of times the interrupt request is received from the device Dj reaches Fj, the interrupt request processing device Mj clears the interrupt factor of the device Dj and sends the interrupt request from the device Dj to the CPU 201 to the interrupt controller 204. Output to.

  (14) Upon receiving an interrupt request from the interrupt request processing device Mj, the interrupt controller 204 outputs an interrupt request from the device Dj to the CPU 201. (15) Upon receiving an interrupt request from the interrupt controller 204, the CPU 201 interrupts the program being executed and calls the interrupt handler. As a result, the interrupt request from the device Dj is processed by the interrupt handler.

(Operation timing of interrupt request processing device Mi)
Next, the operation timing of the interrupt request processing devices Mi and Mj according to the second embodiment will be described. Here, as in FIG. 5, the ID of the interrupt request processing device Mj is held in the ID register R3 of the interrupt request processing device Mi, and the ID of the interrupt controller 204 is stored in the ID register R3 of the interrupt request processing device Mj. A case where an identifier is held will be described as an example.

  FIG. 6 is a timing chart illustrating an example of operation timing of the interrupt request processing device according to the second embodiment. In FIG. 6, when the value of the enable register R1 is set to assert, the interrupt request processing device Mi counts the number of times an interrupt request is received from the device Di. When the number of interrupt requests received from the device Di reaches Fi, the interrupt request processing device Mi sets the value of the enable register R1 to negate and asserts the valid signal for one cycle to the bus 210 (FIG. 6 (a)).

  When the valid signal is asserted, the bus 210 asserts the ready signal for one cycle to the interrupt request processing device Mj ((b) in FIG. 6). When the ready signal is asserted, the interrupt request processing device Mj sets the value of the enable register R1 to assert ((c) in FIG. 6).

  When the value of the enable register R1 is set to assert, the interrupt request processing device Mj counts the number of times that an interrupt request is received from the device Dj. When the number of times that the interrupt request is received from the device Dj reaches Fj, the interrupt request processing device Mj sets the value of the enable register R1 to negate and sends the interrupt request from the device Dj to the CPU 201 to the interrupt controller 204. It outputs ((d) in FIG. 6). Thereby, the device Dj can be operated after the device Di without using the CPU 201.

(Interrupt request processing procedure of interrupt request processing device Mi)
Next, an interrupt request processing procedure of the interrupt request processing device Mi according to the second embodiment will be described. FIG. 7 is a flowchart of an example of an interrupt request processing procedure of the interrupt request processing device according to the second embodiment.

  In the flowchart of FIG. 7, first, the determination unit 402 determines whether or not the value of the enable register R1 is set to assert (step S701). Here, it waits for the value of the enable register R1 to be set to assert (step S701: No), and if it is set to assert (step S701: Yes), is the wait signal asserted by the determination unit 402? It is determined whether or not (step S702).

  If the wait signal is asserted (step S702: Yes), the determination unit 402 waits for the wait signal to be negated. If the wait signal is negated (step S702: No), the output unit 403 outputs an interrupt factor clear instruction to the device Di (step S703). Next, the output unit 403 outputs an execution request for a predetermined process to the device Di (step S704).

  After this, the reception unit 401 waits for an interrupt request from the device Di (step S705: No), and when an interrupt request is received (step S705: Yes), the counter 404 increments the count value (step S705). S706). Then, the number determination unit 405 determines whether or not the count value of the counter 404 matches the register value of the number register R2 (step S707).

  Here, when the count value of the counter 404 and the register value of the count register R2 do not match (step S707: No), the process returns to step S702. On the other hand, if the count value of the counter 404 matches the register value of the count register R2 (step S707: Yes), the output unit 403 outputs an interrupt factor clear instruction to the device Di (step S708).

  Next, the determination unit 402 sets the value of the enable register R1 to negate (step S709). Then, the ID determination unit 406 determines whether or not the register value of the ID register R3 matches the identifier of the interrupt controller 204 (step S710).

  If there is a mismatch (step S710: No), the output unit 403 asserts the valid signal for one cycle and outputs the register value of the ID register R3 to the bus 210 (step S711). A series of processing ends.

  On the other hand, if they match (step S710: Yes), the output unit 403 outputs an interrupt request from the device Di to the CPU 201 to the interrupt controller 204 (step S712), and the series of processing according to this flowchart ends.

  Thereby, an interrupt request that does not require the CPU 201 to be directly involved can be processed instead of the CPU 201. Further, by setting the identifier of the interrupt request processing device Mj mounted on the other device Dj in the ID register R3, the other device Dj that operates in conjunction with the device Di without going through the CPU 201. Can be operated.

(One Example of Computer System 200)
Next, an example of the computer system 200 according to the second embodiment will be described. FIG. 8 is an explanatory diagram of an example of the computer system according to the second embodiment. Here, the DMAC 801 and the memory controller 802 will be described as examples of the device Di in the computer system 200.

  The DMAC 801 controls DMA transfer of the computer system 200. The DMAC 801 is equipped with an interrupt request processing device M1. The memory controller 802 controls interfaces such as the RAM 203 and the NAND flash memory 803 of the computer system 200.

  Here, it is assumed that the CPU 201 uses the DMAC 801 to transfer data stored in the NAND flash memory 803 to the RAM 203. Here, the NAND flash memory 803 is a non-volatile semiconductor memory, and performs writing and reading in page units (for example, 512 [B] or 2048 [B]).

  For this reason, when data having a data amount larger than the page unit is read from the NAND flash memory 803, it is necessary to activate the DMAC 801 a plurality of times to transfer data. For example, if the data amount of the page unit of the NAND flash memory 803 is 2 [KB] and the total transfer data amount is 16 [KB], it is necessary to start the DMAC 801 8 times (= 16/2) to transfer data. is there. For this reason, the predetermined number of times F1 held in the number-of-times register R2 of the interrupt request processing device M1 is “F1 = 8”.

(One Example of Processing Procedure of Computer System 200)
Next, an example of a processing procedure of the computer system 200 according to the second embodiment will be described. FIG. 9 is a sequence diagram of an example of the processing procedure of the computer system according to the second embodiment.

  In the sequence diagram of FIG. 9, (1) the CPU 201 performs initial settings of the interrupt controller 204, the NAND flash memory 803, the DMAC 801, and the interrupt request processing device M1. Specifically, for example, the CPU 201 sets an interrupt vector, a priority order, and the like in the interrupt controller 204. In addition, the CPU 201 sets a read command, a read destination address, and the like in the NAND flash memory 803. Further, the CPU 201 sets the access address, the transfer data amount (here, the data amount in page units), and the like in the DMAC 801. Further, the CPU 201 sets the register value “8” of the number register R2 and the register value “0xFFFFFFFF” of the ID register R3 in the interrupt request processing device M1.

  (2) The CPU 201 outputs a transfer processing execution request to the DMAC 801 to the interrupt request processing device M1. (3) The CPU 201 starts executing an arbitrary program. (4) When receiving the transfer process execution request to the DMAC 801, the interrupt request processing device M1 outputs a transfer process execution request to the DMAC 801.

  (5) Upon receiving an execution request from the interrupt request processing device M1, the DMAC 801 executes a data transfer process from the NAND flash memory 803 to the RAM 203. Specifically, for example, the DMAC 801 repeats the process of taking the data stored in the NAND flash memory 803 into the buffer inside the DMAC 801 and writing it to the RAM 203 until the data for one page is transferred.

  (6) The interrupt request processing device M1 receives from the DMAC 801 an interrupt request to the CPU 201 for notifying the end of transfer processing. (7) When one page of data is read, the NAND flash memory 803 asserts a wait signal to the interrupt request processing device M1, and starts reading the next page of data. Specifically, for example, the NAND flash memory 803 asserts a wait signal directly connected to the interrupt request processing device M1 via the bus 210 and switches pages.

  (8) The NAND flash memory 803 negates a wait signal to the interrupt request processing device M1 when the reading of the next page of data is completed. Specifically, for example, the NAND flash memory 803 negates a wait signal directly connected to the interrupt request processing device M1 via the bus 210.

  (9) The interrupt request processing device M1 clears the interrupt factor of the DMAC 801 and outputs an execution request for transfer processing to the DMAC 801 until the number of interrupt requests received from the DMAC 801 reaches eight. Specifically, for example, the interrupt request processing device M1 outputs a transfer processing execution request to the DMAC 801 after waiting for a wait signal to be negated from the NAND flash memory 803.

  (10) When the number of times the interrupt request is received from the DMAC 801 reaches eight, the interrupt request processing device M1 clears the interrupt factor of the DMAC 801 and outputs the interrupt request from the DMAC 801 to the CPU 201 to the interrupt controller 204. . (11) Upon receiving an interrupt request from the interrupt request processing device M1, the interrupt controller 204 outputs an interrupt request from the DMAC 801 to the CPU 201. When receiving an interrupt request from the interrupt controller 204, the CPU 201 interrupts the program being executed and calls the interrupt handler. Then, an interrupt request from the DMAC 801 is processed by the interrupt handler.

  According to an embodiment of the computer system 200, it is possible to reduce the load on the interrupt processing of the CPU 201 when performing data transfer, and to improve the processing efficiency of the CPU 201. Specifically, instead of the CPU 201, the interrupt request processing device Mi can process the first to seventh interrupt requests from the DMAC 801. For this reason, the CPU 201 only needs to perform an interrupt process for the last (eighth) interrupt request from the DMAC 801. As a result, the CPU 201 can devote itself to processing that should be originally executed, and the processing efficiency of the CPU 201 can be improved.

  As described above, according to the computer system 200 according to the second embodiment, the interrupt request processing device Mi receives an interrupt request instead of the CPU 201 until the number of times that the interrupt request is received from the device Di reaches the predetermined number Fi. Can be processed. That is, interrupt requests from the plurality of devices D1 to Dn to the CPU 201 can be distributed and processed in the plurality of interrupt request processing devices M1 to Mn. As a result, the interrupt processing of the CPU 201 such as interrupting the program being executed and calling the interrupt handler can be reduced, and the load on the interrupt processing of the CPU 201 can be reduced to improve the processing efficiency of the CPU 201. it can.

  Also, according to the computer system 200, by setting the identifier of the interrupt controller 204 in the ID register R3, when the number of interrupt requests received reaches the predetermined number Fi, an interrupt request from the device Di is sent to the CPU 201. You can be notified. Thereby, the CPU 201 can be notified of an interrupt request that needs to be processed via the CPU 201.

  Further, according to the computer system 200, by setting the identifier of the interrupt request processing device Mj in the ID register R3, when the number of received interrupt requests reaches the predetermined number Fi, the other device Dj is notified. An execution request for a predetermined process can be made. Thereby, a plurality of devices D1 to Dn can be operated according to an arbitrary sequence without using the CPU 201.

  Further, in order to install the interrupt request processing device Mi in the computer system 200, it is not necessary to change the interface portion of the CPU 201, the interrupt controller 204, and the device Di. Therefore, the processing efficiency of the CPU 201 can be improved without changing the circuit configuration of the CPU 201, the interrupt controller 204, and the device Di.

(Embodiment 3)
Next, a computer system 1000 according to the third embodiment will be described. In the third embodiment, the computer system 1000 is provided with a dedicated bus for performing communication between the interrupt request processing devices Mi and Mj. In addition, illustration and description are abbreviate | omitted about the location similar to the location demonstrated in Embodiment 1,2.

  FIG. 10 is an explanatory diagram of a computer system according to the third embodiment. In the computer system 1000, the CPU 201, the ROM 202, the RAM 203, the interrupt controller 204, and the devices D1 to Dn are connected to each other via a bus 210 so as to communicate with each other. In the computer system 1000, the interrupt controller 204 and the interrupt request processing devices M1 to Mn are communicably connected via an interrupt dedicated bus 1010.

  Here, the interrupt request processing device Mi communicates with other interrupt request processing devices Mj via the interrupt dedicated bus 1010. Specifically, for example, the output unit 403 outputs an execution request for another device Dj to another interrupt request processing device Mj via the interrupt dedicated bus 1010. The accepting unit 401 accepts an execution request for the device Di from another interrupt request processing device Mj via the interrupt dedicated bus 1010.

  Further, the interrupt request processing device Mi communicates with the interrupt controller 204 via the interrupt dedicated bus 1010. Specifically, for example, the output unit 403 outputs an interrupt request from the device Di to the CPU 201 to the interrupt controller 204 via the interrupt dedicated bus 1010.

  As described above, according to the computer system 1000 according to the third embodiment, communication between the interrupt request processing devices Mi and Mj can be performed via the interrupt dedicated bus 1010 different from the bus 210. As a result, it is possible to prevent the bandwidth of the bus 210 from being compressed by communication between the interrupt request processing devices Mi and Mj, and to prevent a decrease in the throughput of the bus 210. In addition, since it is not necessary to match the communication protocol between the interrupt request processing devices Mi and Mj with the communication protocol of the bus 210, it is possible to reduce the effort of the system designer.

  The interrupt request processing device Mi described in the present embodiment is an application specific IC (hereinafter simply referred to as “ASIC”) such as a standard cell or a structured ASIC (Application Specific Integrated Circuit), or a PLD (Programmable) such as an FPGA. It can also be realized by Logic Device). Specifically, for example, by defining the function of the above-described interrupt request processing device Mi (reception unit 401 to ID determination unit 406) by HDL description, logically synthesizing the HDL description and giving it to the ASIC or PLD The interrupt request processing device Mi can be manufactured.

  In addition, each function unit (reception unit 401 to ID determination unit 406) of the interrupt request processing device Mi realizes its function by causing the CPU 201 to execute a program stored in a storage device such as the ROM 202 or the RAM 203, for example. You may decide to do it. The interrupt request processing method described in the present embodiment can be realized by a computer such as a personal computer or a workstation having each function unit (accepting unit 401 to ID determination unit 406).

100, 200, 1000 Computer system 101, 201 CPU
110, 210 bus 202 ROM
203 RAM
204 Interrupt Controller 401 Reception Unit 402 Judgment Unit 403 Output Unit 404 Counter 405 Number of Times Determination Unit 406 ID Determination Unit 1010 Interrupt Dedicated Bus D, D1 to Dn Device M, M1 to Mn Interrupt Request Processing Device

Claims (5)

As a result of executing an execution request to devices that can communicate with each other via a bus, a central processing unit that receives an interrupt request that notifies the end of a predetermined process from the device and executes an interrupt process;
A device that notifies the end of the predetermined process executed in response to the execution request by outputting the interrupt request;
A receiving unit that receives the interrupt request output from the device;
A determination unit that determines whether the number of times the interrupt request is received from the device by the reception unit is equal to a predetermined number;
As a result of determining whether or not the number of times the interrupt request is accepted by the determination unit matches the predetermined number of times, the execution request is issued to the device until the number of times the interrupt request is accepted reaches the predetermined number of times. An output section to output,
A computer system comprising: The output unit is
2. The computer system according to claim 1, wherein the interrupt request is output to the central processing unit when it is determined that the number of times the interrupt request is received by the determination unit matches the predetermined number of times. For each device that can communicate with the central processing unit, the reception unit, the determination unit (hereinafter referred to as “first determination unit”), the output unit, and the interrupt request are sent to the central processing unit. An interrupt request processing device including a second determination unit that determines whether or not to notify,
The second determination unit includes:
If it is determined by the first determination unit that the number of times the interrupt request has been received from the device matches the predetermined number, it is determined whether to notify the central processing unit of the interrupt request;
The output unit is
3. The execution request for another device different from the device is output when the second determination unit determines not to notify the central processing unit of the interrupt request. Computer system. The interrupt request processing devices are connected so as to be able to communicate with each other by another bus different from the bus,
The output unit is
The computer system according to claim 3, wherein the execution request for the other device is output via the other bus. An interrupt request processing device including a reception unit, a determination unit, and an output unit,
An accepting step of accepting the interrupt request from a device that notifies the end of the predetermined process executed in response to the execution request from the central processing unit by outputting an interrupt request by the accepting unit;
A determination step of determining whether or not the number of times the interrupt request has been received from the device by the reception step is equal to a predetermined number by the determination unit;
As a result of determining whether or not the number of times the interrupt request has been accepted by the determination step matches the predetermined number by the output unit, until the number of times the interrupt request has been received reaches the predetermined number of times to the device An output step for outputting the execution request;
An interrupt request processing method characterized by executing:

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