JP6535516B2 - Multi-programmable device system and control method thereof - Google Patents

Description

    The present invention relates to a communication method between processors and other devices, and more particularly, to a technology for realizing high-speed data communication that includes a shared memory and a plurality of devices.

  Traditionally, when an operation change / instruction for communication etc. is given from a device A to a device B via a shared memory, if the setting data is rewritten so as to immediately change the behavior of the other party, the change Of the areas allocated for setting data by software in order to know the contents, it is necessary to search and know all the relevant areas in order to know which has changed. In the communication field that requires high-speed responsiveness, the delay (latency) required for this search has been a problem.

  In the invention described in Patent Document 1, in order to reduce the load and processing time in communication between such devices (CPUs), the CPU 1 on the transmission side and the CPU 2 on the reception side use a shared memory, and block transfer type Communication data is exchanged via a shared data bus. Data transmission The CPU reads the buffer status flag from the shared memory, and if the data buffer is not in use, the contents of the buffer status flag and transmission data are transferred to the shared memory in a single block transfer and then received. The data receiving request is sent to the CPU, and the data receiving CPU receives the data receiving request as an interrupt, takes data from the data buffer, rewrites the buffer status flag to an unused state, and transfers data between the CPUs Have a configuration to be performed.

  Such a shared memory circuit has a problem that the cost for mounting is high when a general-purpose product is used. When a shared memory block is built in an FPGA, etc., although it is possible to realize the function, it also includes other peripheral control circuits, so the degree of integration of the circuits is increased and it takes a lot of time for verification and the product is released early. There was a problem that was difficult. Therefore, according to the invention of Patent Document 2, the FPGA is provided with a selector, and according to the situation where each CPU uses a shared memory, this selector selects an interrupt / busy signal and outputs it to the CPU to switch the operation mode . By doing this, it is possible to bring products to market early and provide a shared memory switching circuit that has low cost and expandability of memory capacity.

Patent Publication 5-81185 gazette JP, 2008-287571, A

  According to the conventional invention, high-speed data communication between multiple devices can be achieved to some extent, and the problem in implementation has also been solved. However, it has been insufficient to transmit a plurality of communication instructions between a plurality of devices or from one device with low latency while maintaining high responsiveness of quick notification. In addition, it is also difficult to freely increase the number of setting items required to change the operation in the design within the memory without changing the hardware. In particular, there has been a problem of lack of multiple interrupt processing capability when instructions from one device are multiplexed.

  To solve this problem, the present invention uses programmable devices to provide a means for one device to immediately notify another device of a change event that has been rewritten in the setting area.

The present invention comprises at least two programmable devices;
Shared memory,
A light monitoring circuit,
An address holding memory for storing write information on the shared memory;
The light monitoring circuit
Monitoring a write address from one programmable device to the shared memory, and performing a predetermined write to the shared memory;
The multi-programmable device system is controlled to notify the other processor of the write information stored in the address holding memory.

  Also, the present invention is characterized in that the holding memory is of FIFO type.

Furthermore, the present invention is an invention of the control method,
At least two programmable devices,
Shared memory,
A light monitoring circuit,
An address holding memory for storing write information on the shared memory;
A control method of a multi programmable device system provided with
One programmable device writing data modifications to the shared memory;
The write monitoring device detects an address related to the data modification and notifies the other programmable device when it is valid under a predetermined condition;
The write monitoring device storing the address information in an address holding memory;
The other programmable device recognizes and activates the notification and reads out the address information from the address holding memory;
A control method of a multi-programmable device system, comprising:
Further, the address holding memory may be characterized by the FIFO format.

Operation and effect of the invention

According to the present invention, when providing notification of change of data in setting data sharing in a programmable device, it is not necessary to mount a dedicated circuit of a fixed specification configured by hardware, and specification changes such as an increase in the number of setting parameters Can respond flexibly to
Also, once a multi-programmable device system has been created by a substrate, chip, etc., it has become possible to easily add and change setting parameters that can be notified of changes.

FIG. 1 shows a schematic view of a multi-programmable device system of the present invention. 1 shows a detailed configuration of a multi programmable device system according to an embodiment of the present invention. 1 shows a state transition chart of a multi-programmable device system according to an embodiment of the present invention. 1 schematically shows an address holding memory of a multi-programmable device system according to an embodiment of the present invention.

(1) Components of the Present Invention As shown in FIG. 1, the multi-programmable device system according to the present embodiment configures a plurality of programmable devices as active elements. The programmable device in the present application means a device provided with a CPU (Central Processing Unit) core that can be programmed by software and an associated local memory or input / output circuit. In the present application, this will be referred to simply as "device" hereinafter.

  In the following, the components will be described with reference to FIG. 2 which will be described in detail. First, with regard to the devices A and B, for example, the device A of 10 is a device that performs data change operation, and the device B of 20 is a device that needs to recognize the change. These are connected by a bus 500.

A memory 300 is a storage element device shared by the devices A and B via a bus. A so-called shared memory may be a general memory as long as it can be accessed by both one device A and the other device B, and any arbitration means for simultaneous accessibility and sharing may be used.

A control circuit 100 having a central function according to the present invention is called a light monitoring circuit. The data change notification control register 110, the address range determination unit 120, and the notification determination unit 130 are provided therein. Hereinafter, each functional part will be described, but in order to particularly describe the function that it outputs, the output arrow code in FIG. 2 indicates what each functional module performs.

The data change notification control register 110 is a part for setting data change notification which can be changed by a higher-level device through the bus 500, and transmitting and holding information to other functional parts. The output function includes a notification 111 on the address monitor condition, 112 to enable change notification to the devices A and B, and a read control 113 to the address holding memory 200.

The address range determination unit 120 is a unit that determines whether the accessed memory address is an address space to be monitored as a setting change. As a circuit for judging whether or not it falls within the range, it is sufficient if there is a method by a comparator, or a method by mask calculation, which can judge whether it is a space to be monitored or not. Then, the notification judgment unit 130 is notified of the judgment of the monitor condition 121.

The notification determination unit 130 notifies the devices A to B of change information (interruption) according to the determination result as to whether or not it is the monitor space from the address range determination unit 120, and the notification valid state notified from the data change notification control register 110. This is a part to be output 131. In addition, write control 132 of changed address information to the address holding memory 200 is performed.

The address holding memory 200 holds the history of the address to which the change is to be recorded by the notification judging unit 130, and the address space in which the change has occurred is sequentially read from the device notified of the change via the bus 500. Provide a memory function that makes it queryable. Functionally, since the present invention aims at multiple interrupt processing, it is FirstIn-FirstOut (FiFo), and any queue structure or ring buffer structure may be used as long as it is a buffer to that effect.

  In addition, when the internal bus of the bus 500 is subdivided, it is configured by a data bus, an address bus, a read / write instruction, and a bus control signal for indicating the validity of a request or the like. Since the write monitoring circuit 100 performs the function of snooping the bus 500, it can be added without adversely affecting the original function of the bus. Reference numeral 90 denotes a bus controller, which arbitrates the bus 500 between devices, but the configuration and algorithm thereof do not matter as long as the arbitration can be effected directly between the devices.

  Next, in order to explain the operation of each functional module and the flow of signals, it will be described based on the state transition chart of FIG.

(2) Operation of the Present Invention Initial Setting (Register Setting) Setting the operation of the light monitoring apparatus 100 according to an instruction from the device A is an example of the upper part of FIG. In this setting, settings relating to address monitoring conditions and settings for enabling change notification to devices A and B are made.

First, a monitor condition notification instruction is written from the device A to the data change notification register 110 (hereinafter, step S10 in the figure is S10). This is done by normal bus access.
The data change notification register 110 receiving this command notifies the address range determination unit 120 of the monitor condition (S111). Subsequently, the data change notification register 110 validates notification control to the notification determination unit 130 (S112). Thus, the preparation for the exchange with the device A and the device B was performed.

The following is the operation of the runtime, which is shown in the middle part of FIG.
2. Changing Setting of Notification Target This is a step of changing the setting to be notified (memory rewrite). Writing is performed from the device A to a target (altered) address of the memory 300 (S11). Since this is also communicated to the write monitoring circuit 100 at the same time, it becomes an instruction to change the location to the address range determination unit 120 that is the location.

  Subsequently, the address range determination unit 120 determines the corresponding monitor condition (S121). If it is correct, the notification determination unit 130 sends a change notification (interruption) to the device B (S131). At the same time, write processing of the address information is performed in the address holding memory 200 (S132). This write process needs to be performed according to the FIFO format.

3. Acquisition of Changed Information from Memory The device B interrupted in step S20 of transitioning from middle stage to lower stage instructs the data change notification control register 110 to prepare for access to the address holding memory 200 (S21). For example, the interrupt vector is analyzed and read from the address holding memory 200 is performed (S21). However, read control to the address holding memory 200 by the data change notification control register 110 is performed according to the FIFO format (S113). This is post-processing of the Out pointer described later.

  At the same time, the device B acquires a modified address from the address holding memory 200 (S22). This is setting acquisition. As a result, the information data related to the change from the device A based on the obtained address is known.

  The numbering of the steps described in the process flow of FIG. 3 is S (N + n), where N is the functional part and n is the sequence. This code should correspond to the output signal between the components of FIG.

Finally, FIG. 4 shows the outline of the contents of the address holding memory 200.
As Index, the In pointer / Out pointer indicates the position to be written to the buffer of the main holding memory or the position to be read from the one buffer.
-Buffer has a single word address value indicating the presence or absence of modification information from device A for a plurality of events (from the oldest in the figure to # 1, # 2, # 3, # 4) concerning the FIFO format. Are stored at. Device B obtains this to obtain modification data. In this example, the modified address resulting from the # 1 interrupt is read. However, # 2 and # 3 are still stacked without being processed, and the buffer of # 4 is used if there is a new write from device A. Thus, multiple interrupt processing is supported.

As another example, if a start address / end address (or data length) is stored as a set in a buffer, block memory transfer is possible, which is possible in the burst access mode. The number of buffers needs to be large enough to allow for the relationship between the number of interrupts and the processing capability of the device.

  Recently, in a multi-functionalized microcomputer system, mounting with a plurality of boards using a CPU is performed. Many examples combine the main CPU board with the peripheral IO boards that are sub. Further, even in a system having a core composed of a plurality of CPUs in one chip, such as a system on chip (SoC), it is general that the memory can be accessed from each via a bus. In the context of such development, the present invention is very effective when exchanging information via memory.

In particular, when sub CPU boards other than the originally defined specifications are added, if the setting of the light monitoring circuit 100 is made programmable from the device according to the present invention, new subs can be easily created without modifying the main CPU hardware. It can correspond to a CPU board.

  The design changes and additions described in the embodiments of the present application are possible, and even if such changes are made, they fall within the scope of the present invention without departing from the spirit of the present invention.

10 Device A
20 device B
90 bus controller 100 write monitoring circuit 110 data change notification control register 120 address range determination unit 130 notification determination unit 200 address holding memory 300 shared memory 500 bus

Claims (3)

At least two programmable devices,
Shared memory,
A light monitoring circuit,
An address holding memory for storing write information concerning the shared memory in a FIFO format ;
Bei to give a,
The light monitoring circuit
When one programmable device writes data to the shared memory, it is determined whether the address of the shared memory to which the data is written satisfies a predetermined condition.
When it is determined that the condition is satisfied, the other programmable device is notified of the writing of data, and the information of the address of the shared memory to which the data is written is recorded in the address holding memory as the writing information.
The other programmable device notified by the light monitoring circuit is
The information of the address is read from the address holding memory based on the notification from the write monitoring circuit,
A multi-programmable device system for acquiring data from the shared memory based on information of the address read from the address holding memory . At least two programmable devices,
Shared memory,
A light monitoring circuit,
An address holding memory for storing write information concerning the shared memory in a FIFO format ;
A control method of a multi programmable device system provided with
Comprising the steps of one of the programmable device writes data into the shared memory,
A step wherein the light monitoring circuit, an address of the shared memory data has been written to determine satisfy a predetermined condition, when it is determined that satisfy, for notifying the writing of data to the other programmable device,
The write monitoring circuit recording, as the write information, the information on the address of the shared memory where the data is written in the address holding memory;
Other programmable device, a step of reading the address information from said address holding memory based on the notification from the write monitoring circuit,
The other programmable device acquiring data from the shared memory based on the information of the address read from the address holding memory;
A method of controlling a multi-programmable device system, comprising: The light monitoring circuit, as long as the information of the address to the address holding memory is stored, and continues the step of notifying the other programmable device, control of the multi-programmable device system according to claim 2 Method.

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