JP2000181855A - Dma transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DMA transfer system by which a more complicated DMA(direct memory access) transfer system is realized by extending the function of a built-in DMA driver with poor function property. SOLUTION: The system is provided with CPU 101 having the built-in DMA driver 102 by which a transfer enable signal as against a channel and an address as against a memory are outputted by receiving a DMA transfer request signal from the channel and DMA transfer is realized, the plural channels 104 to be a DMA transfer object, a built-in DMA driver control circuit 103 which controls the built-in DMA driver 102 and is at an outer side of CPU and a DMA operation permitting circuit 105 executing control whether DMA transfer is permitted as against one of plural DAM including the built-in DMA driver 102 or not when complicated data transfer is realized by combining the other plural DMA drivers including the built-in DMA driver 102 in the system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer system for exchanging data between a memory and a device.

[0002]

2. Description of the Related Art Instead of a CPU (Central Processing Unit), DMA (Direct Memory Access) is often used to effectively transfer data between a memory such as a DRAM and a channel for executing arithmetic processing. Used.

In the DMA transfer, data transfer to more channels is realized, or the channels are provided with data stock means such as FIFO (first-in first-out) or the like, and the status of the FIFO is monitored to automatically execute the data transfer. It is required that the transfer be interrupted / resumed or that the entire system has a plurality of DMAs and that more complicated data transfer be realized while switching the operation permission.

In recent years, a CPU has a built-in DMA driver, which facilitates bus control, circuit design, and the like.
It is more advantageous to use this built-in DMA driver than to design a new DMA driver externally from the viewpoint of preventing an increase in circuit scale.

[0005]

However, the built-in DM
A driver has a limited number of channels that can be supported,
Insufficient functions such as the inability to suspend / resume the transfer according to the state of the channel or memory, or when switching between multiple DMA drivers is performed, the built-in DMA driver does not have an interface for giving and receiving DMA operation. Issues such as lack of expandability had arisen.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and a DM capable of realizing a more complicated DMA transfer system by extending the function of a built-in DMA driver having poor functionality.
It is intended to provide an A transfer system.

[0007]

SUMMARY OF THE INVENTION A DMA transfer system according to the present invention outputs a transfer enable signal for a channel and an address for a memory upon receiving a DMA transfer request signal from a channel to realize a DMA transfer.
CPU having A driver, a plurality of channels to be DMA-transferred, and CPU controlling built-in DMA driver
An external built-in DMA driver control circuit and a plurality of DMs
A DMA operation permission circuit for controlling which of the A drivers is permitted to perform the DMA transfer.

With this configuration, the built-in DM with poor functionality
A DMA transfer system capable of realizing a more complicated DMA transfer system by extending the function of the A driver can be provided.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 provides a built-in DMA driver which outputs a transfer enable signal for a channel and an address for a memory upon receiving a DMA transfer request signal from a channel to realize DMA transfer. CPUs, and a plurality of channels to be subjected to DMA transfer,
Built-in D outside the CPU that controls the built-in DMA driver
This DMA transfer system includes an MA driver control circuit and a DMA operation permission circuit that controls which of a plurality of DMA drivers is permitted to perform a DMA transfer.

According to a second aspect of the present invention, in the built-in DMA driver control circuit, a channel selecting means for selecting which one of the plurality of channels to execute the DMA transfer, DMA transfer request signal connection means for connecting a DMA transfer request to a transfer request signal of the built-in DMA driver; and a channel enable signal output by the built-in DMA driver which has received the DMA transfer request signal for a channel selected by the channel selection means. And a channel enable connection means for connecting to the internal DMA driver even in a system having channels exceeding the maximum number of channels supported by the internal DMA driver.
DMA transfer using the A driver is enabled.

According to a third aspect of the present invention, in the built-in DMA driver control circuit, a FIFO (first-in-first-out) is used as data stock means for data transfer to each channel.
First out), the FIFO status signal is used as a DMA transfer request signal from the channel, and the FIFO
By changing the DMA transfer request signal to the built-in DMA driver according to the change of the status signal, the interruption and restart of the DMA transfer can be realized by the FIFO state of the channel connected by the channel selecting means, and the interruption and restart of the DMA transfer can be realized. Using a built-in DMA driver that does not have the functions described above, it is possible to suspend / resume by the channel state.

According to a fourth aspect of the present invention, in the built-in DMA driver control circuit, DMA operation setting means for instructing the built-in DMA driver control circuit to perform a DMA operation; A means for outputting a request signal, and a DM
Only after recognizing the A operation permission signal does the DM from the channel
DMA that outputs A transfer request signal to built-in DMA driver
By having a transfer request signal output limiting means,
A built-in DMA driver that is not presumed to operate with A can operate with a plurality of DMAs.

According to a fifth aspect of the present invention, the built-in DMA driver control circuit has a built-in DM having limited functions and expandability.
A complicated DMA transfer can be performed using the A driver.

With the above configuration, the built-in D having poor functionality
A DMA transfer system capable of realizing a more complicated DMA transfer system by extending the functions of the MA driver is made possible.

(Embodiment 1) FIG. 1 is a block diagram of a DMA transfer system according to Embodiment 1 of the present invention, and is a diagram for explaining the invention of claim 1.

A CPU 101 has a built-in DMA driver.
And 102 is a built-in DMA driver. 1
02 according to the program, the CPU 101
The number of transfers, transfer method, memory address, transfer direction, etc. are set internally, and upon receiving a DMA transfer request from an external channel, an address access to memory (112) and an enable signal to the channel are output. FIG. 1 is a diagram according to claim 1 and is a main component of the present invention.
Although the A driver control circuit 103 is shown, a built-in DMA driver is directly connected to an external channel in the related art.

The built-in DMA driver control circuit 103 will be described in detail in the second and subsequent embodiments. 104 is a channel, which is singular or plural. A DMA 105 controls which of a plurality of DMA drivers including another DMA driver such as 106 is given an operation permission.
The operation permission circuit receives a permission request from a DMA driver such as 114 or 117 and returns a DMA operation permission signal such as 115 or 116 to each DMA driver according to a prescribed rule. Here, 114 and 115 are exchanges with the built-in DMA driver control circuit 103.

The channels 104 and the like output a transfer request signal from the channel to the built-in DMA driver control circuit 103 as shown at 110, and perform DMA transfer to the built-in DMA driver in the manner described in the second and subsequent embodiments. Transfer request signal 108 is transmitted.

Reference numeral 109 denotes an enable for a channel output from the built-in DMA driver. Specifically, a write enable is provided for a transfer from a memory to a channel, and a read enable is provided for a transfer from a channel to a memory. Is output at the timing of. This is DMA
The signal 111 is transmitted to the channel through the built-in DMA driver control circuit 103 similarly to the transfer request signal.

The built-in DMA driver 102 outputs a memory access signal 112 such as an address to the memory together with the enable to the channel, thereby realizing data transfer between the memory and the channel (113). Built-in DM with above configuration centering on built-in DMA driver control circuit
It becomes possible to construct a DMA transfer system using the A driver.

As described above, the DMA of the first embodiment
According to the transfer system, it is possible to construct a DMA transfer system using the built-in DMA driver by using the built-in DMA driver control circuit.

(Embodiment 2) FIG. 2 is a block diagram of a DMA transfer system according to Embodiment 2 of the present invention, and FIG. 3 is a timing chart thereof. The built-in DMA driver control circuit described in the first embodiment will be described with reference to chart 1 in FIGS.

A control register 202 is provided in the built-in DMA driver control circuit 103. The CPU 101 operated by a program controls necessary settings for the control register 202 through the register access 201. Here, the necessary setting is to select which of the plurality of channels is to be subjected to DMA transfer, in other words, which channel is to be connected to the built-in DMA driver.

Each channel outputs a channel transfer request signal 110 independently. A transfer request signal from a channel selected according to the contents set by the control register 202 is selected by the selector 204, and the built-in DM
It is transmitted as a DMA transfer request signal 108 to the A driver 102. Channel 10 set by this
4 can be transmitted to the built-in DMA driver 102 only.

This will be described with reference to chart 1 in FIG. T101 is a channel 1 transfer request signal output from channel 1, and T102 is a channel 2 transfer request signal. T103 is the setting content of the control register 202 in FIG. 2, and in the chart, channel 2 is set as a target of DMA transfer. Therefore, as shown in T104, the DMA transfer request signal 108 connected to the built-in DMA driver 102 is a signal having the same timing as the channel 2 transfer request signal because the channel 2 transfer request signal from the channel 2 is connected. I have. The channel 1 transfer request signal is ignored from the viewpoint of the built-in DMA driver 102.

Next, the enable to the channel will be described. Reference numeral 203 in FIG. 2 denotes a selector for switching which channel the enable signal 109 from the built-in DMA driver 102 is connected to, and determines the connection according to the contents set in the control register 202.
The actual enable signal for each channel is output as 111. In Chart 1, the internal DMA driver that has received the DMA transfer request signal in T104 outputs the channel enable shown in T105. In the chart, the timing is merely an example, and actually, the output timing of the channel enable differs depending on the CPU 101. T
Since channel 2 is selected as shown in 103,
Channel enable T105 is connected to channel 2 only. This is as shown in T106 and T107. As described above, by connecting the DMA transfer request signal and the channel enable signal to the selected channel using the channel selecting means, the built-in DMA driver 102 can be used even in a system exceeding the maximum number of channels supported by the built-in DMA driver 102. It is possible to construct a DMA transfer system using the DMA transfer system.

As described above, the DMA of the second embodiment
According to the transfer system, it is possible to perform a DMA transfer to a channel exceeding the number of channels that the built-in DMA driver can support.

(Embodiment 3) FIG. 4 is a block diagram of a DMA transfer system according to Embodiment 3 of the present invention, and FIG. 5 is a timing chart thereof.

The channel 104 has a FIFO 301 as a data stocking means. In the DMA transfer, data from the memory is written into the FIFO 301 or the data of the FIFO 301 is transferred to the memory.

In the second embodiment, the channel transfer request signal from each channel shown at 110 is merely output. However, data transfer may not be possible depending on the channel condition.
If the A transfer is continued, data that is not transferred may occur.

In the case of an externally designed DMA, the above problem can be avoided by adding a function of sequentially suspending and resuming the transfer while monitoring the state of the channel. However, the built-in DMA driver does not always have that function.
Even if O is installed so that the state can be monitored, interruption or the like cannot be performed, and the above problem cannot be solved.

Therefore, the built-in DMA driver control circuit 103
From the channel shown in the second embodiment to the built-in DMA
By using the status from the FIFO 301 for the channel transfer request signal to the driver control circuit 103,
The DMA transfer request signal transmitted to the built-in DMA driver 102 can be interrupted and restarted according to the FIFO state. The built-in DMA driver 102 does not execute data transfer unless the DMA transfer request signal is active, so that data that cannot be transferred does not occur.

This will be described with reference to chart 2 in FIG. FULL (EMPT
Y) The signal is the basis of the channel transfer request signal. In this case, when transferring from the memory to the channel (that is, FIFO), if the channel request signal is not FULL (T205), the channel request signal is activated (T206).
201) Non-active (T202). Conversely, for a transfer from a channel (ie, FIFO) to memory, E
If it is not MPTY, the channel request signal is made active, and if it is EMPTY, it is made non-active.

As the channel request signal changes as described above, the DMA transfer request signal to the actual built-in DMA driver becomes active only when transfer can be accepted on the FIFO side, becomes non-active otherwise, and becomes non-active. In this case, no enable signal is output to the channel as shown in T204, thereby preventing double writing and double reading. When the FIFO state becomes ready to accept the transfer, the DMA transfer request signal becomes active as shown in T207, and the output of the channel enable is restarted (T208).

As described above, the DMA of the third embodiment
According to the transfer system, the transfer can be interrupted and resumed by the channel state by using the built-in DMA driver which does not have the function of suspending and resuming by the channel state.

(Embodiment 4) FIG. 6 is a block diagram of a DMA transfer system according to Embodiment 4 of the present invention, and FIG. 7 is a timing chart thereof.

Reference numeral 402 denotes D for determining which DMA operation is permitted when a plurality of DMA drivers exist.
This is an MA operation permission circuit. This has multiple system buses for one memory, and independent D buses are provided for each system bus.
This is necessary when you have an MA. However built-in D
The MA driver is not designed to operate with a plurality of DMAs, and does not have an interface with the DMA operation permission circuit as described above.

Therefore, the built-in DMA driver control circuit 103
In the control register 202, the internal DMA driver 1
02 is added to the setting of the DMA operation command for instructing the operation of the operation No. 02.
Built-in DMA driver control circuit 10 receiving this command signal
3 outputs a DMA operation permission request signal 401 to the DMA operation permission circuit 402. DMA operation permission circuit 402
Receives a similar DMA operation permission request signal 405 from another DMA driver.

The DMA operation permission circuit that has received the operation permission signal determines which DMA driver is to be permitted. When it is determined, DMA operation permission signals 403 and 406 are output in order to notify it. Where the built-in DMA
In the output of the DMA transfer request signal generated in driver control circuit 103, tristate buffer 404
Is added to the connection of the DMA transfer request signal generated from each channel to the built-in DMA driver 102.
Unless the permission signal represented by the operation permission signal 403 is active, the DMA transfer request signal is not activated.

As a result, even if a transfer request from the channel is satisfied, the D operation to the built-in DMA driver 102 is performed as long as there is no permission from the DMA operation permission circuit 402.
The operation of the built-in DMA driver can be stopped without making the MA transfer request signal active. If this stops, another DMA driver can operate.

The above is described with reference to chart 3 in FIG. T301 is a DMA operation command signal set in the control register. The built-in DMA driver control circuit 103 receives this signal and outputs a DMA operation request signal to the permission circuit. This is T302. In response to this, a permission signal of T303 is returned from the permission circuit, and the channel transfer request signal T304 is connected to the built-in DMA driver 102 as a DMA transfer request signal for the first time (T3).
05). Before that, even if the channel transfer request signal is active as shown at T306, the DMA transfer request signal is in a non-active state because the permission signal is not active. After the DMA transfer request signal becomes active (T305), signals necessary for the DMA transfer operation such as channel enable are output as in the normal operation.

With the above configuration, it is possible to construct a DMA transfer system that operates with a plurality of DMA drivers, even if the built-in DMA driver does not operate with a plurality of DMA drivers.

As described above, the DMA of the fourth embodiment
According to the transfer system, it is possible to construct a system that operates the built-in DMA driver together with the plurality of DMA drivers.

(Fifth Embodiment) By combining all of the configurations of the second to fourth embodiments, the number of corresponding channels is limited, and interruption / resumption depending on the channel state is not supported. It solves the problems of the built-in DMA driver that does not have a mechanism that operates together with it, and makes it possible to construct a DMA transfer system having these functions. According to the DMA transfer system of the fifth embodiment, the number of channels is insufficient, the suspend / resume function is insufficient,
It is possible to make up for all the deficiencies in the functions that work with the MA driver.

[0045]

As described above, according to the present invention, a DMA transfer system capable of realizing a more complicated DMA transfer system by extending the function of the built-in DMA driver having poor functionality can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a DMA transfer system according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a DMA transfer system according to a second embodiment of the present invention.

FIG. 3 is a timing chart according to Embodiment 2 of the present invention.

FIG. 4 is a block diagram of a DMA transfer system according to a third embodiment of the present invention.

FIG. 5 is a timing chart according to Embodiment 3 of the present invention.

FIG. 6 is a block diagram of a DMA transfer system according to a fourth embodiment of the present invention.

FIG. 7 is a timing chart according to Embodiment 4 of the present invention.

[Explanation of symbols]

 101 CPU 102 Built-in DMA driver 103 Built-in DMA driver control circuit 104 Channel 105 DMA operation permission circuit 106 DMA driver 107 Memory 108 DMA transfer request signal 109 Channel enable 110 Channel transfer request signal 111 Channel enable 112 Memory access 113 Data transfer path 114 DMA operation Permission request signal 115 DMA operation permission signal 116 DMA operation permission signal 117 DMA operation permission request signal 201 Register access 202 Control register 203 Selector 204 Selector 301 FIFO 401 DMA operation permission request signal 402 DMA operation permission circuit 403 DMA operation permission signal 404 Tristate Buffer 405 DMA operation permission request signal 406 DMA operation permission signal

Claims (5)

[Claims] 1. A CPU having a built-in DMA driver for realizing a DMA transfer by outputting a transfer enable signal to a channel and an address to a memory upon receiving a DMA transfer request signal from the channel, and a DMA transfer target. C controlling a plurality of channels and a built-in DMA driver
A DMA transfer system comprising: a built-in DMA driver control circuit outside a PU; and a DMA operation permission circuit that controls which of a plurality of DMA drivers is permitted to perform a DMA transfer. 2. A built-in DMA driver control circuit, comprising: a channel selecting means for selecting which one of a plurality of channels to execute a DMA transfer; and a channel transfer request signal from the channel selected by the channel selecting means. D connected to the transfer request signal of the built-in DMA driver
MA transfer request signal connection means, and channel enable connection means for connecting a channel enable signal output by the built-in DMA driver that has received the DMA transfer request signal to the channel selected by the channel selection means, 2. The DMA transfer system according to claim 1, wherein a DMA transfer using a built-in DMA driver can be performed even in a system having channels exceeding the maximum number of channels corresponding to the DMA transfer. 3. The built-in DMA driver control circuit, wherein each channel is provided with a FIFO which is a data stock means for data transfer, a status signal of the FIFO is used as a DMA transfer request signal from the channel, and a built-in DMA driver control circuit is provided in accordance with a change in the FIFO status signal. By changing the DMA transfer request signal to the DMA driver, the DMA transfer is interrupted and resumed by the FIFO state of the channel connected by the channel selecting means, and the built-in DMA transfer interrupt / restart function is not provided. 3. The DMA transfer system according to claim 2, wherein interruption / resumption according to a channel state is enabled by using a DMA driver. 4. A built-in DMA driver control circuit, comprising: DMA operation setting means for instructing the built-in DMA driver control circuit to perform a DMA operation;
Means for outputting an operation permission request signal to an operation permission circuit, and a DMA transfer request for transmitting a channel transfer request signal from a channel to a built-in DMA driver only after recognizing a DMA operation permission signal returned in response to the request. 3. The DMA transfer system according to claim 2, wherein the provision of the signal output restricting means enables a built-in DMA driver which is not supposed to operate with a plurality of DMAs to operate with a plurality of DMAs. 5. The integrated DMA driver control circuit according to claim 1,
5. The DMA transfer system according to claim 2, wherein complicated DMA transfer is enabled by using a built-in DMA driver having limited functions and expandability.