KR100604569B1 - Apparatus for transceiving data between the processors and mobile terminal including the apparatus - Google Patents

Abstract

The present invention relates to a device for multi-processor data communication and a mobile communication terminal including the device, the data communication device,

A memory for data communication; A master processor for writing transmission data to the memory and reading received data written to the memory, and outputting control signals for granting an access right of the memory in response to input of control signals for accessing the memory; A plurality of slave processors for outputting control signals and transmission data and address information for accessing the memory; An address / data buffer unit configured to buffer data and address information transmitted and received between each of the slave processors and the memory; Interfaces the control signals for accessing the memory and the control signals for granting access to the memory between the slave processors and the master processor, and the address according to the control signal output from the slave processor granted the memory access rights. And a buffer controller for controlling the output of the data buffer unit.

Master, slave, multiprocessor.

Description

TECHNICAL FIELD [0001] The present invention relates to a multi-processor data communication device and a mobile communication terminal including the device.

1 is an exemplary system configuration of a one-to-many master-slave method.

Figure 2 is a block diagram of a multi-processor data communication apparatus according to an embodiment of the present invention.

3 is a detailed configuration example of the address / data buffer unit 40 in FIG. 2.

4 is a detailed circuit diagram of the buffer control unit 50 in FIG. 2.

5 is a flow diagram of data communication between multiple processors according to an embodiment of the present invention.

The present invention relates to a multiprocessor, and more particularly, to an apparatus for data communication between multiprocessors and a mobile communication terminal including the apparatus.

A system employing multiple processors, or multiprocessors, is often configured as a one-to-many master-slave system in which one processor executes the main program and the other processors serve only additional functions or functional functions. An example of such a one-to-many master-slave system is shown in FIG. 1.

Referring to FIG. 1, a plurality of slave CPUs 12a, 12b... Are connected to one master CPU 11 through DPRAM (Dual Ported Random Access Memory: 13a, 13b,...). DPRAM allows bidirectional reference and writing, and has the ability to send interrupt signals in both directions.

Therefore, each CPU is interrupted through DPRAM, and the interrupt vector function contains the code for communicating with the CPU that sent the interrupt and performing a specific task. Here, of course, the interrupted master CPU is configured so that it knows which CPU sent the interrupt. At this time, the interrupted CPU leaves the contents of the task to be instructed at the promised position on the DPRAM, so that the interrupted master CPU accesses the DPRAM connected to the interrupted CPU to perform data communication.

In a general multiprocessor system having the above-described configuration, it can be said that the system is complicated because DPRAM is provided between the slave parts and the master part to perform communication. The complexity of such a system is a limitation in reducing the weight and weight of the product, and the result is that the cost of the product increases due to the provision of multiple DPRAMs.

In addition, in a system with a multiprocessor having the above-described configuration, when some slave parts are turned off, the master recognizes that an interrupt signal of a low active state is generated and maintains a communication standby state. In this communication standby state, the corresponding slave part is turned off, resulting in a malfunction state in which communication is not performed. Furthermore, in the mobile communication terminals, a plurality of processors are employed to implement a multimedia. In this case, it is preferable to keep the idle processors in the off state to reduce the current consumption. However, turning off the idle processor causes a system malfunction problem as described above. Therefore, a new solution to this problem must be devised.

Accordingly, an object of the present invention was devised to solve the above-described problem, and a multiprocessor data communication device and apparatus capable of performing data communication with another processor using a memory provided in one of the multiprocessors In providing a mobile communication terminal comprising a,

Furthermore, the present invention provides a data communication apparatus and a mobile communication terminal capable of solving a malfunction problem caused by the turning off of some processors in performing data communication between multiple processors by sharing one memory.

Another aspect of the present invention is to provide a multi-processor data communication device and a mobile communication terminal including the device capable of reducing the total current consumption by efficiently turning off a processor in a dormant state among multiple processors without a system malfunction.

Multi-processor data communication apparatus according to an embodiment of the present invention for achieving the above object,

A memory for data communication;

A master processor for writing transmission data to the memory and reading received data written to the memory, and outputting control signals for granting an access right of the memory in response to input of control signals for accessing the memory;

A plurality of slave processors for outputting control signals and transmission data and address information for accessing the memory;

An address / data buffer unit configured to buffer data and address information transmitted and received between each of the slave processors and the memory;

Interfaces the control signals for accessing the memory and the control signals for granting access to the memory between the slave processors and the master processor, and the address according to the control signal output from the slave processor granted the memory access rights. And a buffer controller for controlling the output of the data buffer unit.

Furthermore, a mobile communication terminal including a multi-processor data communication apparatus according to an embodiment of the present invention,

A memory for data communication;

A master processor for writing transmission data to the memory and reading received data written to the memory, and outputting control signals for granting an access right of the memory in response to input of control signals for accessing the memory;

A plurality of slave processors for outputting control signals and transmission data and address information for accessing the memory;

An address / data buffer unit configured to buffer data and address information transmitted and received between each of the slave processors and the memory;

Interfaces the control signals for accessing the memory and the control signals for granting access to the memory between the slave processors and the master processor, and the address according to the control signal output from the slave processor granted the memory access rights. And a buffer controller for controlling the output of the data buffer unit.

In each of the above-described embodiments, the data communication memory may be an internal memory of the master processor or one DPRAM.

Therefore, since the present invention enables normal data communication between a plurality of slave processors and a master processor with only one DPRAM, the system structure can be simplified and the manufacturing cost can be reduced.

Furthermore, since the present invention uses the memory in the processor for data communication, there is an advantage in that it is possible to perform normal data communication between multiple processors without having a separate DPRAM.

In addition, even if any slave processor is turned off in a mobile communication terminal including a multi-processor, a system malfunction can be prevented in advance, thereby reducing the current consumption of the entire system by turning off the idle slave processor. Can also be obtained.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

First, FIG. 2 is a block diagram of a multi-processor data communication apparatus according to an embodiment of the present invention, and more specifically, includes one master processor 60 and two slave processors 20 and 30. The block diagram of the data communication device is illustrated. Such a data communication device may be implemented in a mobile communication terminal supporting a multimedia function. That is, the master processor 60 corresponds to MSM, which is a terminal main processor, and the slave processors 20 and 30 correspond to respective processors for obtaining a DMB implementation and a camera image. In the following description, a master processor and a slave processor will be referred to for convenience.

 3 illustrates a detailed configuration diagram of the address / data buffer unit 40 of FIG. 2, FIG. 4 illustrates a detailed circuit diagram of the buffer control unit 50 of FIG. 2, and FIG. 5 illustrates an embodiment of the present invention. Each of the multi-processor data communication flowcharts is illustrated.

Referring to FIG. 2, first, each of the slave processors 20 and 30 outputs control signals and transmission data and address information for accessing a data communication memory designated for data communication with the master processor 60. Control signals for accessing the memory will be described later, but include a slave status signal S0x_ACTIVE, a data read signal S0x_nRD, a data write signal S0x_nWR, and the like.

Meanwhile, the master processor 60 performing data communication with the slave processors 20 and 30 includes a data communication memory 70 and a CPU 80. Since the CPU 80 may be referred to as one processor along with other internal memories in the processor, the CPU 80 and the master processor 60 will be interpreted as the same without being strictly distinguished. The important thing is to distinguish the master processor and the memory 70 for data communication for performing data communication with the slave processors 20 and 30.

For reference, in the exemplary embodiment of the present invention, it is assumed that the memory 70 in the master processor 60 is used as the memory for data communication. However, as already known, the present invention may be implemented by setting the DPRAM as the memory for data communication.

Basically, the master processor 60 writes transmission data to the memory 70, reads reception data written to the memory 70, and control signals S0x_nIRQ, S0x_MON, for accessing the memory 70. In response to an input of ..), the control signals MACK0x, MINT0x, .. granting the access right of the memory 70 are output. The master processor 60 may grant memory access rights to the slave processors 20 and 30 according to any one of several known algorithms (eg, time division scheme,...).

Meanwhile, the address / data buffer unit 40 controls the buffer controller 50 to describe data S0x_D and address information S0x_A which are transmitted and received between each of the slave processors 20 and 30 and the memory 70. According to the buffering output. As shown in FIG. 3, these address / data buffer units 40 are equally provided with the slave processors.

Referring to FIG. 3, each of the address buffers 42 and 44 is independently connected to the slave side address bus and is commonly connected to the address bus of the master side, that is, the memory 70. The address buffers 42 and 44 include address information input from the slave side and various control signals, for example, a slave status signal S0x_ACTIVE, a data read signal S0x_nRD, a data write signal S0x_nWR, and a chip enable signal S0x_nCS and the like are outputted to the master side in accordance with the output enable signal S0x_OE input from the buffer controller 50.

Meanwhile, each of the data buffers 46 and 48 is also connected to the slave side data bus independently and has a structure in common with the master side data bus. The data buffers 46 and 48 temporarily store data input from the slave side or the master side, and according to the data transfer direction indication signal S0x_DIR and the output enable signal S0x_OE output from the buffer controller 50 to be described later. Output to the master or slave side.

Hereinafter, the buffer controller 50 controlling the output of the address / data buffer unit 40 described above will be described. The buffer controller 50 may be configured between the slave processors 20 and 30 and the master processor 60. The control signals S0x_nIRQ and S0x_MON for accessing the memory 70 and the control signals MINT0x and MACK0x for granting an access right to the memory 70 are interfaced. In addition, the buffer controller 50 controls the output of the address / data buffer unit 40 according to a control signal output from the slave processor granted the memory access right. The buffer controller 50 includes a gate array corresponding to each of the slave processors 20 and 30, and each gate array includes a plurality of gate elements as shown in FIG. 4.

Referring to FIG. 4, first, a gate array circuit existing in correspondence with each slave processor 20 and 30 is provided.

A first gate element 92 for generating a data write request signal S0x_nIRQ transmitted to the master by ORing the inverted value of the slave state signal S0x_ACTIVE outputted from the slave side and the data write request signal S0x_nINT;

A second gate element (93) for generating a memory access permission signal (M2S0x_ACK) transmitted to the slave by multiplying the memory access permission signal (MACK0x) and the slave status signal (S0x_ACTIVE) output from the master side;

A third gate element 94 generating a memory access termination signal S0x_MON transmitted to the master by logically multiplying the memory access termination signal S0x_nEND outputted from the slave side with the slave status signal S0x_ACTIVE;

A fourth gate element 95 for generating a data read permission signal M2S0x_nINT to be transmitted to the slave by multiplying the data read permission signal MINT0x and the slave status signal S0x_ACTIVE output from the master side;

A fifth gate configured to logically combine the chip enable signal S0x_nCS outputted from the slave side and the inverted slave state signal S0x_ACTIVE to generate the chip enable signal nMCS0x transmitted to the address / data buffer unit 40. An element 96;

A sixth gate element 97 delaying outputting the chip enable signal S0x_nCS output from the slave side to the address / data buffer unit 40;

Inverts the inverted value of the data read signal S0x_nRD outputted from the slave side and the inverted value of the chip enable signal S0x_nCS outputted from the slave side and instructs the data transfer direction to be transmitted to the address / data buffer unit 40. And a seventh gate element 100 generating a signal S0x_DIR.

For reference, the data transmission direction indication signal S0x_DIR is a signal indicating a direction in which data should be output to the slave side or the master side from the position of the data buffers 46 and 48.

By the gate array configured as described above, the buffer controller 50 may control the output of the data buffered in the address / data buffer unit 40 according to the control signal output from the slave processor granted the memory access right. Will be.

In addition, even when each slave processor 20, 30 is turned off, the low level slave status signal S0x_ACTIVE indicating the off state is inverted by the inverter 91 and mastered by the data write request signal S0x_nIRQ of the "high" level. Since it is transmitted to the side, the master processor 60 designed to respond to the "low" level data write request signal S0x_nIRQ is to perform data communication with another processor or perform other tasks.

Therefore, since the present invention operates the system normally without being affected even when the slave processor is turned off, it is possible to obtain an effect of preventing unnecessary current consumption by turning off the processors in the idle state.

Hereinafter, a data transmission / reception process in a data communication apparatus according to an exemplary embodiment of the present invention will be described in detail.

In FIG. 5, (a) shows a sequence when data is written to the memory 70 on the slave side, and (b) shows a sequence when data written to the memory 70 is read on the slave side. .

Referring to (a), the slave processor 20 for data communication first outputs its slave status signal S0x_ACTIVE to the address buffer 42 and the buffer controller 50. When the slave processor 20 outputs the data write request signal S0x_nINT to the "low" level in order to write data to the memory 70, the "low" level in the first gate element 92 of the buffer controller 50. The data write request signal S0x_nIRQ is generated and applied to the CPU 80 of the master processor 60. The CPU 80 interrupted by the "low" level data write request signal S0x_nIRQ generates and outputs a memory connection permission signal MACK0x in response to the data write request. The memory access permission signal MACK0x is applied to the second gate element 93 of the buffer controller 50 and logically combined as the "high" level memory access permission signal M2S0x_ACK to the slave processor 20.

The slave processor 20 outputs data and an address to be transmitted and control signals necessary for accessing the authorized memory 70. The output data and address are respectively address / data buffer unit 40. It starts to be buffered in the address buffer 42 and the data buffer 46 within.

Meanwhile, among the control signals output from the slave processor 20 to access the authorized memory 70, the chip enable signal S0x_nCS of the “low” level is the fifth gate element 96 in the buffer controller 50. Is applied to the address buffer 42 as the "low" level chip enable signal nMCS0x in conjunction with the "low" level slave enable signal S0x_ACTIVE. The address buffer 42 enabled by the chip enable signal nMCS0x starts to buffer address information and control signals (data read and data write signal) applied from the slave processor 20.

The chip enable signal nMCS0x input to the buffer controller 50 is delayed in the sixth gate element 97 and then output to the address buffer 42 and the data buffer 46 as the output enable signal S0x_OE. Is applied to the level. The address buffer 42 and the data buffer 44 output the buffered address information and data to the master in response to the " low " level output enable signal S0x_OE, thereby allocating the memory allocated to the slave processor 20. Data is written to a predetermined address in the area (70).

If the memory access end signal S0x_nEND is activated from the slave processor 20, the signal is transmitted to the master side as the memory access end signal S0x_MON through the third gate element 94 of the buffer controller 50. The side can be notified that the data transmission from the slave side has ended.

On the other hand, when the data read in the memory 70 is read from the slave side, the master processor 60 preferentially transmits the data read permission signal MINT0x of the "low" level to the slave side. This "low" level data read permission signal MINT0x is used to interrupt the corresponding slave processor 20 by being logically multiplied by the slave status signal S0x_ACTIVE in the buffer controller 50.

The slave processor 20 interrupted by the data read permission signal M2S0x_nINT outputs control signals necessary for reading data written to the memory 50, that is, a chip enable signal and a data read signal. Data read from the master side memory 70 may be transferred to the slave processor 20 through the data buffer 46.

Accordingly, the present invention enables normal data communication between multiple processors using one processor internal memory.

As described above, since the present invention uses the memory in the processor for data communication, it is possible to perform normal data communication between the multiprocessors without having a separate DPRAM and to simplify the system structure compared to the existing system. .

In addition, the present invention can prevent the system from malfunctioning even if any one of the slave processor is off in a system including a multi-processor, thereby reducing the current consumption of the entire system by turning off the idle slave processor There are also advantages.                     

On the other hand, the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. For example, in the exemplary embodiment of the present invention, a case in which a memory provided in the master processor is used for data communication has been described, but only one DPRAM may be provided without any modification so that data communication may be performed between the master and the slave processors. Therefore, the true technical protection scope of the present invention should be defined only by the appended claims.

Claims (10)

A memory for data communication; A master processor for writing transmission data to the memory and reading received data written to the memory, and outputting control signals for granting an access right of the memory in response to input of control signals for accessing the memory; A plurality of slave processors for outputting control signals and transmission data and address information for accessing the memory; An address / data buffer unit configured to buffer data and address information transmitted and received between each of the slave processors and the memory; Interfaces the control signals for accessing the memory and the control signals for granting access to the memory between the slave processors and the master processor, and the address according to the control signal output from the slave processor granted the memory access rights. And a buffer control unit for controlling the output of the data buffer unit. The apparatus of claim 1, wherein the data communication memory is an internal memory of the master processor.  The apparatus of claim 1, wherein the data communication memory is a DPRAM. The apparatus of claim 1, wherein the address / data buffer units are provided in equal numbers with slave processors, respectively. The method of claim 1, wherein the buffer controller includes a gate array corresponding to the slave processor, each gate array; A first gate element for generating a data write request signal transmitted to the master by ORing the inverted value of the slave state signal outputted from the slave side and the data write request signal; A second gate element for generating a memory access permission signal transmitted to a slave by multiplying the memory access permission signal outputted from a master side and the slave status signal; A third gate element for generating a memory access termination signal, which is logically multiplied by the memory access termination signal output from the slave side, with the slave status signal; A fourth gate element for generating a data read permission signal to be transmitted to the slave by multiplying the data read permission signal outputted from the master side and the slave status signal; A fifth gate element configured to logically combine the chip enable signal output from the slave side and the inverted slave state signal to generate a chip enable signal transferred to the address / data buffer unit; A sixth gate element which delays and outputs a chip enable signal output from a slave side to the address / data buffer unit; A seventh gate element configured to generate a data transfer direction indication signal transferred to the address / data buffer unit by ORing the inverted value of the data read signal outputted from the slave side and the inverted value of the chip enable signal outputted from the slave side; Multi-processor data communication apparatus comprising a. In a mobile communication terminal comprising a multi-processor data communication device, the data communication device, A memory for data communication; A master processor for writing transmission data to the memory and reading received data written to the memory, and outputting control signals for granting an access right of the memory in response to input of control signals for accessing the memory; A plurality of slave processors for outputting control signals and transmission data and address information for accessing the memory; An address / data buffer unit configured to buffer data and address information transmitted and received between each of the slave processors and the memory; Interfaces the control signals for accessing the memory and the control signals for granting access to the memory between the slave processors and the master processor, and according to the control signal output from the slave processor granted the memory access rights. And a buffer controller for controlling the output of the address / data buffer unit. The mobile communication terminal of claim 6, wherein the data communication memory is an internal memory of the master processor.  The mobile communication terminal of claim 6, wherein the memory for data communication is a DPRAM. The mobile communication terminal of claim 6, wherein the address / data buffer units are provided in equal numbers with slave processors, respectively. The method of claim 6, wherein the buffer controller comprises a gate array corresponding to the slave processor, each gate array; A first gate element for generating a data write request signal transmitted to the master by ORing the inverted value of the slave state signal outputted from the slave side and the data write request signal; A second gate element for generating a memory access permission signal transmitted to the slave by multiplying the memory access permission signal outputted from a master side and the slave status signal; A third gate element for generating a memory access termination signal, which is logically multiplied by the memory access termination signal output from the slave side, with the slave status signal; A fourth gate element for generating a data read permission signal to be transmitted to the slave by multiplying the data read permission signal outputted from the master side and the slave status signal; A fifth gate element configured to logically combine the chip enable signal output from the slave side and the inverted slave state signal to generate a chip enable signal transferred to the address / data buffer unit; A sixth gate element which delays and outputs a chip enable signal output from a slave side to the address / data buffer unit; A seventh gate element configured to generate a data transfer direction indication signal transferred to the address / data buffer unit by ORing the inverted value of the data read signal outputted from the slave side and the inverted value of the chip enable signal outputted from the slave side; Mobile communication terminal comprising a.

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