JPH01198850A - Direction control system - Google Patents

Abstract

PURPOSE:To prevent to decrease a reliability to latch reading-out data even when a distance to a farthest slave device is extended to 1/2 clock delay. CONSTITUTION:The direction control signal 1 of a 0 level to send reading-out data to a master device and generated in the master device 1 is one clock width and a timing is made the first one clock of a reading-out data area. The direction control in the master device 1 executes by passing a direction control signal through the double delay circuit 6 of the delaying quantity of a bidirectional bus 2 between the farthest slave devices 3 and the direction control in the farthest slave device 4 is executed without the use of the delay circuit. The direction control in other slave device 3 is executed through the delay circuit 7 of the double delaying quantity of a difference between the delaying quantity by the bidirectional bus 2 from the master device 1 and the delaying quantity by the bidirectional bus 2 between the master device and the farthest slave device 4. Thus, even when the distance to the farthest slave device 4 is extended to 1/2 clock width, the reliability of the latch can be increased.

Description

[Detailed Description of the Invention] [Summary] Regarding the direction control method of a bidirectional bus system, even if the distance of the bidirectional bus of the name of the farthest slave device is increased to 1/2 clock delay, the read data The purpose of this is to provide a direction control method that does not reduce the reliability of latching data.The width of the direction control signal, which directs the read data to the master device and is issued by the master device, is one clock width, and the timing is set at the beginning of the read data area. 1 clock, and the direction control in the master device is performed by passing the direction control signal through a delay circuit that is twice the delay amount of the bidirectional bus between the farthest slave devices. Direction f4 control is performed without using a delay circuit, and direction control in other slave devices is based on the amount of delay from the master device due to the bidirectional bus and between the master device and the farthest slave device. The configuration is such that the processing is performed through a delay circuit with a delay amount twice the difference from the delay amount due to the bidirectional bus.

[Industrial application field]

The present invention provides a CPU for each part (slave device) of a transmission device.
The present invention relates to an improvement in a direction control method for a bidirectional bus system, in which a master device having a master device sets an operating mode, reads out the status of each unit from the memory of each unit, and monitors the status of each unit.

[Conventional technology]

The direction control method of a conventional bidirectional bus system will be explained below with reference to the drawings.

Figure 4 is a block diagram of a conventional bidirectional bus system.
Figures 5 and 6 are time charts showing the direction control signals of each part in Figure 4 and the timing of each data. When the width of the control signal is one clock width, (A) shows the clock, (B) shows the write cycle and read cycle, and (C) to (1) correspond to the three points cw in Fig. 4. (C) is the timing of the direction control signal issued by the master device 1', (D) is the timing of the direction control signal at the slave device 3° where the direction control signal in (C) is delayed, (
E) is the timing of each data in slave device 3, (
F) (I) is the timing of each data at the entrance of the master device 1, (G) is the timing of the direction control signal at the farthest slave device 4 where the direction control signal in (C) is delayed, (H
) indicates the timing of each data in the farthest slave device 4.

In the following description, it will be assumed that the delay amount of the bidirectional bus 2 and the delay amount of the control signal line 5 are equal.

Slave devices 3' and 4 are connected to the bidirectional bus 2 from the master device 1' in FIG. 4, with slave device 4 being the farthest slave device.

In a bidirectional bus system, the write cycle and read cycle for writing and reading from the master device 1 to each slave device 3 and 4 have good throughput.
To simplify the configuration, as shown in FIGS. 5 and 6 (B), the width is 4 clocks, the write address and read address areas are the first 1 clock width, and the write data area is the next 1 clock width. The read data area is the following 2 clock widths.
The clock width is now used.

For example, when the CPU 8 of the master device 1'' writes data to the memory 14 of the slave device 3'', it writes data in the write address area in the write cycle of FIGS. 5 and 6(B).
Write the address of the write position in the slave device 3' and the memo 1J14 and a code indicating the write, write the write data in the write data area, provide it to the bidirectional bus interface 9 having a bidirectional buffer, and write the write data in the write data area. The direction control signal applied to the bidirectional bus interface 9 is a control signal and transmits the write address and write data to the bidirectional bus 2.

At this time, since the direction control signal is at the level of the level, the buffer 10. The direction control signal input to the slave devices 3° and 4 via the control signal line 5 is also a level signal, and the buffer 11
．． The direction control signal sent via 15 to the OR circuit 13.16 is also a signal of the level.

Since the write address is addressed to the slave device 3°, the level of the direction control signal is given to the bidirectional bus interface 12 having a bidirectional buffer of the slave device 3 through the OR circuit 13, and the write address and The write data is taken in and written to the corresponding address position in the memory 14.

When the CPU 8 of the master device 11' reads data from the memory 14 of the slave device 3', the slave device 3' and the memory 1J14 are stored in the read address area of the read cycle shown in FIGS. 5 and 6 (B). Write the address of the position to be read out and a code indicating the readout, and give it to the bidirectional bus interface 9. Also, the direction control signal given to the bidirectional bus interface 9 is set to the left side of the label, and the above readout address is written. to the bidirectional bus 2.

Then, in the slave device 3'', since the read address is addressed to the device itself, the direction control signal level is passed through the OR circuit 13 to the bidirectional bus interface 12 having a bidirectional buffer, and the read address is sent to the slave device 3''. The data is taken in and given to the memory 14, and the data at this read address is read out.

This read data is sent to the master device 1' via the bidirectional bus 2, fetched by the bidirectional bus interface 9, latched, and read by the CPU 8. As shown in (C), the first 1.5 clock width of the read data area is the θ level, and the direction control signal directs the open direction of the 0 level toward the master device 1, or as shown in FIG. 6(C). As shown, the first clock width of the read data area is θ level, and a direction control signal for directing the open direction of the 0 level toward the master device l is applied to the bidirectional bus interface 9, and the buffer lO and the control signal line 5 to the slave devices 3' and 4.

Slave devices W3'', 4 receive this via a buffer 11.15 and provide it to an OR circuit 13.16.

The read address is 1 because it is addressed to slave device 3.
, the OR circuit 13 is given a level, and a direction control signal of 0 level is given to the bidirectional bus interface 12. During this 0 level, the read data is sent to the master device 1 via the bidirectional bus 2. Master device 1
In the bidirectional bus interface 9 of ', FIG. 5(A)
It is latched at the latch position shown in FIG. 6 or the latch position shown in FIG. 6(A), and the CPU 8 takes in this data.

When writing data to the memory 18 of the slave device 4 and reading data from the memory 18, the same operation as described above is performed by setting the write address and the read address to desired addresses of the slave device 4 and the memory 18.

In these cases, the write address, write data, read address, and read data of the slave device 3
5 and 6, due to the delay caused by the bidirectional bus 2. It becomes as shown in (1).

As will be explained later, in the case of FIG. 5, there is a 1/8 clock delay up to the slave device W13', a 1/4 clock delay up to the farthest slave device 4, and in the case of FIG. The figure shows a 1/4 clock delay up to the slave device 3° and a 1/2 clock delay up to the farthest slave device 4, so the O level direction control signal is applied to the slave devices 3' and 4. , as shown in (D) and (G) of FIGS. 5 and 6. At this timing, the read data is sent to the master device 1, and the timing of the read data at the entrance of the master device 1 is delayed as shown in (D) and (G) of FIGS. Figure 6 (F) (1)
It becomes as shown in.

This means that if the slave device is located very close to the master device 1', there is no delay due to the bidirectional bus 2, so the timing of the read data at the entrance of the master device 1' in this case is Figure 5.

As shown in the recent read data shown in FIG. As shown in the farthest read data in Figures 5 and 6 (B), the position is at the very edge of the next cycle,
Moreover, in the case of FIG. 6, there is a limit to which the read data can be launched.

In other words, the delay of read data is the sum of the delay of the 0-level direction control signal due to the control signal line 5 and the delay of the read data due to the bidirectional bus 2, so that both up to the farthest slave device 4 The distance of the tropic bus 2 is θ in FIG.
If the level direction control signal is 1.5 clocks wide, there is a delay distance of 1/4 clock due to the latch position that latches the read data of the recent slave device, and in this case, the read data is delayed by 1/4 clock. Even if there is a slight movement, it can be latched and the reliability is high. However, if the θ level direction control signal is 1 clock width as shown in Fig. 6, the distance can be extended to a delay of 1/2 clock. The latch position is the limit, and if the read data moves slightly, it cannot be latched and reliability decreases.

[Problem to be solved by the invention]

In the conventional direction control method described above, the θ level direction control signal has a width of 1.5 clocks, and the
If the distance of bidirectional bus 2 is 1/4 clock delay, then
Although the reliability of latching the read data is high, there is a problem with the short distance.The 0-level direction control signal is set to 1 clock width, and the distance of the bidirectional bus 2 to the farthest slave device 4 is l/2. If the clock delay is increased, there is a problem that the reliability of latching read data decreases.

The present invention provides bidirectional bus 2 up to the farthest slave device 4.
The object of the present invention is to provide a direction control method that does not reduce the reliability of latching read data even if the distance between the two directions is increased to 1/2 clock delay.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention, in which (A) is a block diagram showing the configuration of a bidirectional bus system, (B) shows a write cycle and a read cycle, and (C) shows the read data for the master device. This shows an O level direction control signal.

As shown in FIG. 1(A), a plurality of slave devices 3.4 are connected to the bidirectional bus 2 from the master device 1, and the master device 1 reads and writes to each slave device 3.4. Both the write cycle and the read cycle are 4 clocks wide, as shown in FIG. The read data area uses the following two clock widths.

Direction control for receiving read data from the bidirectional bus 2 at the master device 1 and transmitting read data to the bidirectional bus 2 at each slave device 3.4 is performed by the master device 1. and the plurality of slave devices 3 and 4,
A direction control signal received using the control signal line 5 between the master device 1 and the plurality of slave devices 3.4 is used.

As shown in FIG. 1(A), the O-level direction control signal, which directs the read data in the direction of the master device L, issued by the master device 1 has a width of 1 clock and the timing is read as shown in FIG. 1(C). This is the first clock of the data area. The direction control in the master device 1 is performed by transmitting the direction control signal to a delay circuit 6 shown in FIG. The direction control at the farthest slave device 4 is performed without using a delay circuit. Direction control in other slave devices 3 is determined by the amount of delay caused by the bidirectional bus 2 from the master device 1 and the delay caused by the bidirectional bus 2 between the master device 1 and the farthest slave device 4. Figure 1 (A) of the delay amount which is twice the difference between the amount and the amount of delay.
This is done through a delay circuit 7 shown in FIG.

[For production]

According to the present invention, when performing direction control using a direction control signal, the 0-level direction control signal issued by the master device 1 and directing read data to the master device has a width of 1 clock, and the timing is set in the read data area. The direction control in the master device 1 is performed by passing the direction control signal through a delay circuit 6 with twice the delay amount of the bidirectional bus 2 between the farthest slave devices 4. The direction control in the farthest slave device 4 is performed without using a delay circuit, and the direction control in the other slave devices 3 is based on the amount of delay from the master device 1 by the bidirectional bus 2 and the direction control in the farthest slave device 4. Since the delay circuit 7 has a delay amount twice the difference between the delay amount due to the bidirectional bus 2 between the master device 1 and the farthest slave device 4, all the slaves at the entrance of the master device 1 The timing of the read data from the device and the timing of launching the read data of the master device 1 are also the timing of the read data shown in FIG. 1(B).

This means that up to the farthest slave device 4,
Since the sum of the delay of the 0-level direction control signal shown in the control signal line 5 and the delay of the read data to the master device t by the bidirectional bus 2 is one clock width, The distance of the two-way bus 2 is! /2 clock width can be achieved, and the latch position of the read data in the master device 1 can be performed in the middle of the read data shown in FIG. 1(B), so that the reliability of the latch can be increased.

〔Example〕

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 2 is a block diagram of a bidirectional bus system according to an embodiment of the present invention, FIG. 3 is a time chart showing the timing of direction control signals of each part in FIG. Corresponding to points c-g in the figure, (A) is the clock, (B) is the write cycle, read cycle, (C) is the timing of the 0-level direction control signal for directing read data to the master device 1, (D ) is the timing of the direction control signal passing through the delay circuit 6, (E) is the timing of the direction control signal at the entrance of the slave device 3, (F) is the timing of the direction control signal passing through the delay circuit 7, (G) indicates the timing of the direction control signal at the entrance of the farthest slave device 4.

In FIG. 2, the 0-level direction control signal issued by the master device 1 for directing read data to the master device 1 is as shown in FIG. 3(C), as in the case shown in FIG. 6(C). The first clock width of the read data area is different from the case shown in FIG. A delay circuit 6 is provided for direction control in the master device 1.
The farthest slave device 4 is the same as before,
The other slave devices 3 calculate the difference between the amount of delay caused by the bidirectional bus 2 from the master device 1 and the amount of delay caused by the bidirectional bus 2 between the master device 1 and the farthest slave device 4. The difference is that a delay circuit 7 with twice the amount of delay is provided, and direction control is performed through the delay circuit 7.

Therefore, the operation of the write cycle is the same as in FIG. 4, but the timing during the read cycle is different.

Focusing on this different point, we will discuss the launch of read data in the master device 1 in the read cycle in the third section.
This will be explained using figures.

The master device 1 transmits the 1-clock-width O-level direction control signal shown in FIG. It is delayed as shown in (D) through the double delay circuit 6, and is applied to the bidirectional bus interface 9, and (
The 0 level direction control signal shown in C) is sent to the buffer 10.
Control signal line5. They are sent to the respective slave devices 3.4 via buffers 11.15.

In the slave device 3, the 0-level direction control signal shown in (E) is transmitted based on the amount of delay from the master device 1 due to the bidirectional bus 2, and the amount of delay between the master device 1 and the farthest slave device 4. It is delayed as shown in (F) through the delay circuit 7 whose delay amount is twice the difference from the delay amount by the directional bus 2, and if the read address is for the own device, it is bidirectionally transmitted via the OR circuit 13. read data to the master device 1.

The farthest slave device 4 then sends the O-level direction control signal shown in (G) to the bidirectional bus interface 17 via the OR circuit 16 if the read address is for its own device, and reads the read data. is sent to master device 1.

Then, the read data from the slave device very close to the master device 1 and the farthest slave device 4 with a 1/2 clock delay from the master device 1 will also be at the read data position shown in (B) at the entrance of the master device fft. If the latch position is set at the center of the read data as shown in (A), the distance of the bidirectional buffer 2 to the farthest slave device 4 is increased and the read data can be reliably latched even with a 1/2 clock delay. You can improve your sexuality.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the master device 1
Even if the distance of the bidirectional buffer 2 from the slave device 4 to the farthest slave device 4 is increased by 1/2 clock delay, the reliability of latching the read data can be increased.

[Brief explanation of the drawing]

FIG. 1 is a diagram of the principle of the present invention; FIG. 2 is a block diagram of a bidirectional bus system according to an embodiment of the present invention; FIG. 3 is a time chart showing the timing of direction control signals of each part in FIG. 2; FIG. 4 is a block diagram of a conventional bidirectional bus system. In the figure, 1.1° is a master device, 2 is a bidirectional bus, 3.3', 4 are slave devices, 5 is a control signal line, 6.7 is a delay circuit, and 8 is a CPU. 9.12.17 is a bidirectional bus interface; 10.
11.15 is the buffer, 13.16 is the OR circuit,

Claims (1)

[Claims] A plurality of slave devices (3, 4) are connected to a bidirectional bus (2) from a master device (1), and the master device (1)
Therefore, the write cycle and read cycle for writing and reading data to each slave device (3, 4) are both 4 clocks wide, and both the write address and read address area are 1 clock width at the beginning, and the write data area is 4 clocks wide. Using the next 1 clock width and the next 2 clock widths for the read data area, the master device (1) receives read data from the bidirectional bus (2), and each slave device (
3, 4), the directional control for the transmission of read data onto the bidirectional bus (2) is issued by the master device (1), and in the plurality of slave devices (3, 4): In a bidirectional bus system using a direction control signal received using a control signal line (5) between the master device (1) and the plurality of slave devices (3, 4), the master device (1) issues the direction control signal. The width of the direction control signal for directing the read data to the master device is one clock width and the timing is the first one clock of the read data area, and the direction control in the master device (1) is performed by using the direction control signal as follows. The bidirectional bus (
2) is performed through a delay circuit (6) with twice the delay amount, the direction control at the farthest slave device (4) is performed without using a delay circuit, and the direction control at the other slave device (3) is performed. , the amount of delay due to the bidirectional bus (2) from the master device (1), and the amount of delay between the master device (1) and the farthest slave device (
4) The difference between the amount of delay caused by the bidirectional bus (2) between
A direction control method characterized in that control is performed through a delay circuit (7) with double the amount of delay.