JPH02278454A - Data transfer timing control system - Google Patents

Abstract

PURPOSE:To easily speed up the processing of a storage device by providing information concerning the speed of a memory used in a memory module, determining data transfer timing according to the information and transmitting the data transfer timing through control in the storage device and a bus to an opponent processor. CONSTITUTION:A memory module 4 outputs the speed of the used memory to a memory speed transmission line 14. A main control circuit 1 determines the timing of data transfer based on the information from the memory speed transmission line 14 and transmits the data transfer timing through the control in the storage device and a bus 10 to the opponent processor. Thus, when the memory module 4 using a high-speed memory chip is used, the data transfer ability of the storage device is improved and the performance of a system is easily improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data transfer timing control system, and in particular has information on the speed of memory used by a memory module, and uses that information to determine data transfer timing. , relates to a data transfer timing control method for transmitting data transfer timing to a partner processor via internal control of a storage device and a bus.

[Conventional technology]

Conventionally, in this type of data transfer timing control system, data transfer was performed at a constant timing, except that the transfer timing was delayed due to refresh.

[Problem to be solved by the invention]

In the conventional data transfer timing control method described above, data transfer is performed at a constant timing, except for the transfer timing being delayed due to refresh, so even if the speed of the memory chip used in the memory module is increased, the speed of the storage device cannot be increased. The disadvantage is that it cannot be easily realized.

An object of the present invention is to provide a data transfer timing control system that solves the above problems.

[Means to solve the problem]

In order to achieve the above object, the data transfer timing control method according to the present invention provides a memory module having a transmission means for transmitting the speed of the memory being used in a storage device of a system in which the storage device controls the data transfer timing of a bus. a main control circuit having a transmission means that determines the timing of data transfer from the transmission means of the memory module and transmits the data transfer timing to the internal control of the storage device and the bus; and a data control circuit that controls data between a bus and the memory module under control from the main control circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, the memory module 4 outputs the speed of the memory being used to the memory speed transmission line 14. The main control circuit 1 determines the timing of data transfer based on information from the memory speed transmission line 14, and when a command is received from the processor via the bus 10 (the command line is not shown),
Data transfer timing data transfer timing transmission line 1
1 to the bus 1G, a basic data control signal is output to the control line 13, and a basic memory module control signal is output to the control line 16. The memory module control circuit 2 outputs a memory module control signal to the control fi 17 based on the information from the control line 16. The memory module 4 stores data from the data line 15 in the case of data writing, and outputs the stored data to the data line 15 in the case of data reading, according to the signal on the control line 17. In the case of data writing, the data control circuit 3 inputs the write data from the bus 10 through the data line 12 based on information from the control line 13, performs certain processing, outputs it to the data line 15, and performs data reading. If data line 1
5 input the read data of the memory module 4,
It undergoes certain processing and is output to the bus 10 through the data line 12.

〔Effect of the invention〕

As explained above, the present invention includes a memory module that has a transmission means for transmitting the speed of the memory being used, and the timing of data transfer is determined by the transmission means of the memory module, and the timing of data transfer to the internal control of the storage device and the bus is determined. A main control circuit having a transmission means, a memory module control circuit that controls the memory module under control from the main control circuit, and a data control circuit that controls data between the bus and the memory module under control from the main control circuit. If a memory module using a high-speed memory chip is used, the data transfer capability of the storage device can be easily improved, and the system has the effect of easily achieving higher performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Main control circuit 2... Memory module control circuit 3... Data control circuit 4... Memory module 10... Bus 11... Data transfer timing transmission lines 12, 15...
・Data line 13.16.17...Control line 14・
・・Memory speed C Yudatsu line patent issued by Ibaraki NEC Co., Ltd.

Claims (1)

[Claims] (1) In a storage device of a system in which a storage device controls data transfer timing on a bus, a memory module has a transmission means for transmitting the speed of the memory being used, and the timing of data transfer is determined by the transmission means of the memory module. , a main control circuit having a transmission means for controlling the inside of the storage device and transmitting data transfer timing to the bus;
A memory module control circuit that controls the memory module under control from the main control circuit, and a data control circuit that controls data between a bus and the memory module under control from the main control circuit. Data transfer timing control method.