JPS6462741A - Main storage device - Google Patents
Main storage deviceInfo
- Publication number
- JPS6462741A JPS6462741A JP21990187A JP21990187A JPS6462741A JP S6462741 A JPS6462741 A JP S6462741A JP 21990187 A JP21990187 A JP 21990187A JP 21990187 A JP21990187 A JP 21990187A JP S6462741 A JPS6462741 A JP S6462741A
- Authority
- JP
- Japan
- Prior art keywords
- timing
- main storage
- signal
- signals
- access speed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To mix and mount, and control main storage cards whose access speeds are different, by providing a timing selecting part for selecting and outputting a necessary timing signal, based on address information, an operation discriminating signal and an access speed discriminating signal. CONSTITUTION:The titled device is provided with a timing generating part for generating the access speed discriminating signals 22, 23 for showing an access speed at every main storage card 1b, 2b, and also, generating plural kinds of timing signals at every various timing control signals, and a timing selecting part for selecting and outputting a necessary timing signal, based on address information 10, an operation discriminating signal 9 and access speed discriminating signals Ta, Tb, from in the timing signals. That is, by a timing control part 6b, a necessary timing control signal is generated dynamically, each time of its access in accordance with an access speed at every main storage card 1b, 2b. In such a way, main storage cards whose access speeds are different can be mixed and mounted, and controlled.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21990187A JPS6462741A (en) | 1987-09-02 | 1987-09-02 | Main storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21990187A JPS6462741A (en) | 1987-09-02 | 1987-09-02 | Main storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6462741A true JPS6462741A (en) | 1989-03-09 |
Family
ID=16742808
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21990187A Pending JPS6462741A (en) | 1987-09-02 | 1987-09-02 | Main storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6462741A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02278454A (en) * | 1989-04-20 | 1990-11-14 | Nec Ibaraki Ltd | Data transfer timing control system |
JPH06214870A (en) * | 1993-01-13 | 1994-08-05 | Nec Corp | Memory controller |
JPH07508611A (en) * | 1993-04-30 | 1995-09-21 | パッカード・ベル・エヌイーシー・インコーポレーテッド | Symmetric multiprocessing system with unified environment and distributed system functionality |
-
1987
- 1987-09-02 JP JP21990187A patent/JPS6462741A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02278454A (en) * | 1989-04-20 | 1990-11-14 | Nec Ibaraki Ltd | Data transfer timing control system |
JPH06214870A (en) * | 1993-01-13 | 1994-08-05 | Nec Corp | Memory controller |
JPH07508611A (en) * | 1993-04-30 | 1995-09-21 | パッカード・ベル・エヌイーシー・インコーポレーテッド | Symmetric multiprocessing system with unified environment and distributed system functionality |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4217637A (en) | Data processing unit with two clock speeds | |
MY108527A (en) | Memory cartridge having a multi-memory controller with memory bank switching capabilities and data processing apparatus | |
GB2084361B (en) | Random access memory arrangements | |
EP0267612A3 (en) | Timer/counter using a register block | |
GB1516817A (en) | Arrangements for performing logical operations | |
JPS6462741A (en) | Main storage device | |
JPS6420143A (en) | Data input/output device controlled by processor | |
EP0123896A3 (en) | Character and video mode control circuit | |
CH644987GA3 (en) | Electronic device having an alarm function | |
EP0660298A4 (en) | Image processing device and method therefor, and game machine having image processing part. | |
JPS5525176A (en) | Memory unit control system | |
KR890007300A (en) | Semiconductor memory | |
JPS55154177A (en) | Printer | |
JPS56156978A (en) | Memory control system | |
JPS56168481A (en) | Display device | |
JPS6429926A (en) | Fifo circuit | |
JPS56124944A (en) | Kanji (chinese character) information processing system | |
EP0261629A3 (en) | Display apparatus | |
JPS55146686A (en) | Magnetic bubble memory unit | |
JPS63241681A (en) | Circuit for supervising slip sending condition | |
JPS5734238A (en) | Write address designation circuit for character generating memory device | |
JPS5584090A (en) | Stack control system for logic control unit | |
KR910006971A (en) | Carrier output device | |
JPS6429925A (en) | Fifo circuit | |
JPS5470733A (en) | Information output unit |