JP6112412B2 - I / O control circuit and synchronization control method in I / O control circuit - Google Patents

Description

  The present invention relates to an input / output control circuit and a synchronization control method in the input / output control circuit, and more particularly to an input / output control circuit in which a plurality of IO expansion devices are connected on the same channel of a bus and a plurality of IOs in the input / output control circuit. The present invention relates to an expansion device synchronization control method.

  The number of IO signals (GPIO: General Purpose Input / Output) that can be controlled by a CPU (Central Processing Unit) is limited, and it may be difficult to control all necessary signals with the GPIO of the CPU. An IO expansion device is used in such a case. The IO expansion device is connected to a specific interface of the CPU, and its input / output is controlled by access (register control) to the IO expansion device via the interface.

  In general, one IO expansion device is connected to one channel of the interface. However, if the number of signals to be controlled by the IO expansion device increases, the IO expansion device must be changed to a device with a large circuit capacity or a large number of IOs, resulting in a large cost increase. Therefore, various methods have been proposed for increasing the number of signals that can be controlled without changing the IO expansion device.

  For example, the following Patent Document 1 discloses an input / output sharing unit that can control an input / output direction, a setting unit that sets whether the input / output sharing unit is an input point or an output point, and the input / output sharing unit. Transfer means for transferring input data to the internal processing means when the functions as an input point, and transferring output data from the internal processing means to the input / output sharing means when the input / output sharing means functions as an output point; , A data input / output control method is disclosed. In this publication, each IO port can be selectively assigned by SW, and any signal of any synchronous input / output device can be freely combined as an input or output.

  Patent Document 2 below relates to an I / O device including a control unit that performs input / output and interrupt control, and the I / O device includes a first bus, and the control unit includes the first bus. A command control unit that receives a command using a command line and returns a response, a data control unit that transmits and receives data using the data line of the first bus, and a data line of the first bus An interrupt control unit configured to transmit an interrupt to the host controller, and the I / O device is a device number for setting one or more second buses and a device number for communication between the I / O device and the host controller A configuration comprising setting means and mode setting means for setting an operation mode of the I / O device is disclosed. In this publication, an I / O device whose operation mode is set to the master mode is added as a hub, and the hub makes a command response and interrupt adjustment, thereby enabling connection of a plurality of I / O devices.

  Patent Document 3 below includes a one-chip microcomputer provided with a serial interface, and a general-purpose shift register IC that converts serial data output from the one-chip microcomputer into a plurality of bits of parallel data. A plurality of general-purpose logic ICs that output a plurality of bits of parallel data are cascade-connected, and the serial data is input to the first general-purpose logic IC that is cascade-connected. There is disclosed an I / O expansion circuit that latches data and outputs it as a plurality of bits of parallel data, and outputs serial data input before the latch timing to a general-purpose logic IC in the subsequent stage. In this publication, an output signal is expanded by cascading a plurality of shift registers.

  Patent Document 4 listed below is a data distributor that distributes and outputs print data output from a computer to a plurality of printing apparatuses, and is a computer for connecting to a peripheral device connection port provided in the computer. Port, a plurality of printing device side ports for connecting to the printing device, a port buffer associated with each printing device side port, and a plurality of ports for printing data input to the computer side port A configuration including a distribution unit that duplicates and outputs to a buffer is disclosed. In this publication, data output from a PC is received by a device such as a repeater hub and is repeatedly output to each printer.

JP 07-319592 A JP 2009-123141 A JP 2011-197981 A Japanese Patent Application Laid-Open No. 2003-075522

  However, when a plurality of IO expansion devices are connected to one channel, there arises a problem that individual IO expansion devices cannot be appropriately controlled. For example, in the read access from the CPU, each of the plurality of IO expansion devices outputs data to the CPU. Therefore, the CPU acquires data acquired from a specific external device connected to a predetermined IO expansion device. It is not possible to judge whether it is. Further, in the write access from the CPU, data is written to each of the plurality of IO expansion devices, so that it is not possible to control only a specific external device connected to a predetermined IO expansion device. In addition, it is possible to switch between a plurality of IO expansion devices using SW and a hub by using the technique of the patent document, but this method requires switching control and complicates the circuit configuration.

  Further, if the same signal is input to a plurality of IO expansion devices, there is a problem that the IO that can be expanded by the added IO expansion device cannot be used to the maximum extent. That is, when the same signal is input to the IO expansion device to which the input function is assigned and the IO expansion device to which the output function is assigned, the read signal and the input function are assigned to the IO expansion device to which the output function is assigned. IO is used to input a non-essential signal such as a write signal for the IO expansion device, and the number of IOs that can be expanded correspondingly decreases.

  The present invention has been made in view of the above problems, and its main object is to appropriately control each IO expansion device in a configuration in which a plurality of IO expansion devices are connected on the same channel of a bus. It is another object of the present invention to provide an input / output control circuit that can make maximum use of an IO that can be expanded by an IO expansion device and a synchronization control method in the input / output control circuit.

  One aspect of the present invention is an input / output control circuit in which a plurality of IO expansion devices are connected to the same channel of a specific bus of a CPU, and the plurality of IO expansion devices include an IO expansion device for input control. Each of the IO expansion devices has a register control unit configured of the same circuit, and the output control IO expansion device has a read control signal. In the write access from the CPU that is not input, the data output from the CPU is written in the IO expansion device for input control and the IO expansion device for output control, and the read access from the CPU Then, only the IO expansion device for input control outputs the value of the register managed by the register control unit as a response.

  One aspect of the present invention is an input / output control in which a plurality of IO expansion devices, each including an input control IO expansion device and an output control IO expansion device, are connected to the same channel of a specific CPU bus. A method for synchronous control of the plurality of IO expansion devices in a circuit, wherein each IO expansion device is provided with a register control unit composed of the same circuit, and the output control IO expansion device has a read control. In the write access from the CPU without inputting a signal, the data output from the CPU is written in the IO expansion device for input control and the IO expansion device for output control, and in the read access from the CPU In addition, only the IO expansion device for input control outputs a register value managed by the register control unit as a response. .

  According to the input / output control circuit and the synchronization control method in the input / output control circuit of the present invention, each IO expansion device can be appropriately controlled in a configuration in which a plurality of IO expansion devices are connected to the same channel of the bus. The IO that can be expanded by the IO expansion device can be utilized to the maximum extent.

  The reason is that when a plurality of IO expansion devices composed of an input control IO expansion device and an output control IO expansion device are connected to the same channel of a specific bus of the CPU, the output control A read control signal is not input to the IO expansion device. In write access from the CPU, data output from the CPU is written to a plurality of IO expansion devices. In read access from the CPU, an IO control device for input control is written. When only the register value is output to the CPU as a response and the data written to the output control IO expansion device is confirmed, the input control IO expansion device replaces the output control IO expansion device with a register. This is because the value is output as a response.

  In addition, the write control signal is not input to the input control IO expansion device, and the read control signal input to the output control IO expansion device has an inactive logic level in the IO expansion device. In the write access from the CPU, the data output from the CPU is written only in the IO expansion device for output control. In the read access from the CPU, the active read control signal is input. This is because only the IO expansion device outputs the register value as a response.

It is a figure explaining the write access and read access to the IO expansion device in the input / output control circuit according to one embodiment of the present invention. It is a figure explaining the write access and read access to the IO expansion device in the other input / output control circuit which concerns on one Embodiment of this invention. It is a figure which shows the structure of the input-output control circuit which concerns on one Example of this invention. It is a figure explaining the synchronous control method between IO expansion devices which concern on one Example of this invention. It is a figure explaining the IO number (in the case of a polling system) which can be expanded with the IO expansion device which concerns on one Example of this invention. It is a figure which shows the IO number (in the case of a collective interrupt system) which can be expanded with the IO expansion device which concerns on one Example of this invention. It is a figure which shows the register | resistor used with the input / output control circuit based on one Example of this invention. It is a flowchart figure which shows the input expansion IO control method in the input / output control circuit based on one Example of this invention. It is a flowchart figure which shows the output expansion IO control method (at the time of writing) in the input / output control circuit based on one Example of this invention. It is a flowchart figure which shows the output expansion IO control method (at the time of confirmation) in the input / output control circuit which concerns on one Example of this invention. It is a figure explaining the write access and read access to the IO expansion device in the conventional circuit. It is a figure explaining the write access and read access to the IO expansion device in other conventional circuits.

  As shown in the background art, the IO expansion device is used in the input / output control circuit. However, when the number of signals to be controlled by the IO expansion device increases, the IO expansion device is changed to a device with a large circuit capacity and the number of IOs. Changing it will incur an increase in cost. Further, when a plurality of IO expansion devices are used without changing the IO expansion device, each IO expansion device cannot be appropriately controlled, and the IO that can be expanded cannot be used to the maximum extent. There was a problem. This problem will be described with reference to the drawings.

  For example, as shown in FIG. 11, the CPU has a 3-channel parallel bus, device A is connected to channel 1, device B is connected to channel 2, and device C (IO expansion device) is connected to channel 3. Is connected. In this configuration, in the write access from the CPU shown in FIG. 11A, the select signal C and the write signal from the CPU are input to the device C, and the data output from the CPU is written to the device C. In the read access from the CPU shown in FIG. 11B, the select signal C and the read signal from the CPU are input to the device C, and the device C outputs data to the CPU. Therefore, in this configuration, the CPU can appropriately control the IO expansion device.

  In the configuration of FIG. 11, when the number of signals to be controlled by the device C (IO expansion device) increases, it is possible to connect two IO expansion devices of the device C1 and the device C2 to the channel 3 as shown in FIG. Is possible.

  However, in the write access from the CPU shown in FIG. 12A, the device C1 and the device C2 are connected to the same channel, and the select signal C and the write signal from the CPU are input to the device C1 and the device C2. Therefore, data output from the CPU is written to both the device C1 and the device C2. In the read access from the CPU shown in FIG. 12B, the device C1 and the device C2 are connected to the same channel, and the select signal C and the read signal from the CPU are input to the device C1 and the device C2. Therefore, both the device C1 and the device C2 output data to the CPU. Therefore, the CPU cannot appropriately control only the desired IO expansion device.

  Also, as shown in FIG. 12, regardless of whether the IO expansion device is for input control or output control, if the same signal is input to the device C1 and the device C2, the device C1 and the device C2 can be expanded. Cannot be used to the maximum. That is, the output control IO expansion device does not necessarily output data to the CPU, but if a read signal is input to the output control IO expansion device, the number of IOs that can be expanded is reduced accordingly. Similarly, it is not always necessary to write the data output from the CPU to the input control IO expansion device, but if a write signal is input to the input control IO expansion device, the number of IOs that can be expanded decreases accordingly. End up.

  Therefore, in one embodiment of the present invention, an output function is assigned in an input / output control circuit in which a plurality of IO expansion devices are connected on the same channel of the bus and an input / output function is assigned to each IO expansion device. In addition, a read signal is not input to the output control IO expansion device, or a write signal is not input to the input control IO expansion device to which the input function is assigned.

  That is, in the former case, the write access from the host (CPU) allows data to be written to both IO expansion devices to which the input / output function is assigned, and the read function from the CPU does not have the input function. Only the assigned IO expansion device for input control outputs data as a response. Specifically, as shown in FIG. 1, the CPU has a 3-channel parallel bus, device A is connected to channel 1, device B is connected to channel 2, and channel 3 is used for input control. In the configuration in which the two IO expansion devices of the device C1 and the output control device C2 are connected, the select signal C, the write signal, and the read signal are input to the input control device C1 for output control. Only the select signal C and the write signal are input to the device C2.

  In this case, in the write access from the CPU shown in FIG. 1A, the device C1 and the device C2 are connected to the same channel, and the select signal C and the write signal from the CPU are input to both. Data output from the CPU is written in both C1 and device C2. In the read access from the CPU shown in FIG. 1B, the select signal C from the CPU is input to the device C1 and the device C2. However, since the read signal is input only to the device C1, only the device C1 has Data is output to the CPU. In this configuration, in the write access from the CPU, data is written to both the device C1 and the device C2, but the device C1 is used for input control and does not output the written data to the external device, so no problem occurs. Further, since the same data is written to both the device C1 and the device C2, by using read access to the device C1 (that is, making the device C1 make a proxy response of the device C2), the data written to the device C2 is changed. Can be confirmed. Therefore, the CPU can appropriately control only the desired IO expansion device.

  In the latter case, read access from the CPU causes both IO expansion devices to which the input / output function is assigned to output data as a response, and output access is assigned to the write access from the CPU. Data is written only to a specific IO expansion device. Specifically, as shown in FIG. 2, only the select signal and the read signal are input to the device C1, and the select signal, the write signal, and the read signal are input to the device C2.

  In this case, in the write access from the CPU shown in FIG. 2A, the device C1 and the device C2 are connected to the same channel, and the select signal C from the CPU is input to the device C1 and the device C2. Since the signal is input only to the device C2, data is written only to the device C2. In the read access from the CPU shown in FIG. 2B, the select signal C and the read signal from the CPU are input to the device C1 and the device C2, but the read signal input to the device C2 is used as described later. By fixing to an inactive logic level in the device C2, only the device C1 to which an active read signal is input outputs data to the CPU. Therefore, the CPU can appropriately control only the desired IO expansion device.

  As described above, even when the IO expansion device to which the input function is assigned and the IO expansion device to which the output function is assigned are connected to the same channel of the bus, one IO expansion device is connected from the CPU. Since it appears to be connected, only the desired IO expansion device can be properly controlled. In addition, since no read signal is input to the IO expansion device to which the output function is assigned or no write signal is input to the IO expansion device to which the input function is assigned, the IO of the added IO expansion device is maximized. Can be used. Furthermore, since the circuits (register control units that control the registers) in the plurality of IO expansion devices can be shared, the design efficiency can be improved and the cost increase can be suppressed.

  In order to describe the above-described embodiment of the present invention in further detail, an input / output control circuit according to an embodiment of the present invention and a synchronous control method in the input / output control circuit will be described with reference to FIGS. . FIG. 3 is a diagram illustrating a configuration of the input / output control circuit of the present embodiment, and FIG. 4 is a diagram illustrating a synchronization control method between IO expansion devices of the present embodiment. 5 and 6 are diagrams illustrating the number of IOs that can be expanded by the IO expansion device, and FIG. 7 is a diagram illustrating registers of the IO expansion device. FIG. 8 is a flowchart showing input expansion IO control in the input / output control circuit of this embodiment, and FIGS. 9 and 10 are flowcharts showing output expansion IO control.

  The input / output control circuit of this embodiment includes a CPU (specifically, a CPU having an external interface function, called SoC (System-on-a-chip)), and 2 for input control and output control. One IO expansion device. Here, the configuration is the same as that of the embodiment, and as illustrated in FIG. 3, the configuration includes a CPU 10 and four devices (device A, device B, device C1, and device C2) controlled by the CPU 10. .

  In this embodiment, the CPU 10 has a three-channel parallel bus, and device A is connected to channel 1, device B is connected to channel 2, and devices C1 and C2 are connected to channel 3. The devices A and B are, for example, Nor-Flash memories, the boot data is stored in the Nor-Flash memory 20 connected to the channel 1, and the non-boot memory is connected to the Nor-Flash memory 30 connected to the channel 2. FW (firmware) is stored. The devices C1 and C2 are logic devices (hereinafter referred to as CPLD: Complex Programmable Logic Device). The CPLD1 (device C1) is assigned in advance as an IO expansion device 40 for input control, and the CPLD2 (device C2) is output controlled. Is assigned in advance as an I / O expansion device 50.

  Further, the CPU 10 selects a device connected to each channel (select signals A to C), a write signal for writing data to the device, a read signal for reading data from the device, Is output. The device A receives the select signal A, the write signal, and the read signal, and the device B receives the select signal B, the write signal, and the read signal. Further, in this example, on the assumption of the configuration shown in FIG. 1 of the embodiment, a select signal C, a write signal, and a read signal are input to CPLD1 (device C1), and CPLD2 (device C2) A select signal C and a write signal are input.

  FIG. 4 shows the configuration of CPLD1 (device C1) and CPLD2 (device C2). The CPLD 1 has a register control unit 41, and the CPLD 2 has a register control unit 51. The register control units 41 and 51 are common HW circuits described in RTL (Register Transfer Level), HDL (Hardware Description Language), and the like. The register control unit 41 includes an input control register 42 and an output control register 43, and the register control unit 51 includes an input control register 52 and an output control register 53. The output control register 43, CPLD2, and output control register 53 of CPLD1 are synchronized.

  CPLD1 mainly receives external sensor signals (input signals 1 to 3). On the other hand, power control signals (output signals 1 to 3) and the like are output to CPLD2. Here, CPLD2 is an IO expansion device 50 for output control, and it is not necessary to control input. Therefore, when adopting the configuration of FIG. 2 of the embodiment, input to the input control register 52 of CPLD2 is performed. The read signal to be read is fixed at an inactive logic level so that only the write signal can be used.

  In the input / output control circuit having such a configuration, in the write access from the CPU 10, CPLD1 and CPLD2 are connected to the same channel 3, and the select signal C and the write signal from the CPU 10 are input to both CPLD1 and CPLD2. Therefore, CPLD1 and CPLD2 both determine that they are write accesses to themselves, and fetch data into the output control registers 43 and 53. At this time, the output control register 43 of the CPLD 1 is not connected to the outside, and the fetched data is not output to the outside. Therefore, the CPU 10 can appropriately control only the CPLD 2 assigned in advance for output control. For example, when the input / output control circuit is incorporated in an image forming apparatus such as an MFP (Multi Function Peripheral), CPU power control, panel power control, FAX power control, and the like can be performed.

  In read access from the CPU 10, CPLD1 and CPLD2 are connected to the same channel 3, and the select signal C from the CPU 10 is input to CPLD1 and CPLD2, but the read signal is input only to CPLD1. Only the CPLD 1 judges that it is a read access to itself and outputs the data held in the input control register 42 to the CPU 10. Therefore, the CPU 10 can appropriately control only the CPLD 1 assigned in advance for input control. For example, when an input / output control circuit is incorporated in an image forming apparatus such as an MFP, a signal from a sensor for detecting a paper jam, a sensor for detecting opening / closing of a door, a sensor provided on a paper tray, or the like is acquired. And the state of the MFP can be determined.

  In the configuration of FIG. 2 of the embodiment (a configuration in which the write signal is input only to the CPLD 2), in the write access from the CPU 10, the CPLD 1 and CPLD 2 are connected to the same channel 3, and the select signal from the CPU 10 C is input to CPLD 1 and CPLD 2, but the write signal is input only to CPLD 2, so that only CPLD 2 is determined to be a write access to itself and data is taken into output control register 53. Therefore, it is possible to appropriately control only the CPLD 2 assigned in advance for output control.

  In the read access from the CPU 10, CPLD1 and CPLD2 are connected to the same channel 3, and the select signal C and the read signal from the CPU 10 are input to both CPLD1 and CPLD2. However, in CPLD2, the read signal is fixed at an inactive logic level, and data is not output to the CPU 10. Therefore, the CPU 10 can appropriately control only the CPLD 1 assigned in advance for input control.

  Next, the number of IOs of the IO expansion device will be described. FIG. 5 is a diagram for explaining the number of IOs that can be used by the IO expansion device. FIG. 5A shows the number of IOs when two IO expansion devices for input / output control are connected, (b), ( c) shows the number of IOs when the IO expansion device for input control and the IO expansion device for output control are connected. FIG. 5 shows an example in which a polling method is used in which the CPU 10 reads the state of each sensor signal input to the CPLD 1 by reading the IO expansion device for input control at a constant period. is there.

  Each IO expansion device receives a select signal, a write signal, a read signal, and a data signal for connection to the device bus. In the case of the IO expansion device for input / output control in FIG. 5A, assuming that there are N IOs that can be used as expansion IOs, an IO expansion device for input / output control having the same configuration is added. Since the select signal, write signal, read signal, and data signal are also input to the IO expansion device, the number of IOs that can be used as the expansion IO is similarly N.

  On the other hand, in the case of FIG. 5B, a select signal, a write signal, a read signal, and a data signal are input to the input control IO expansion device, and the input control IO expansion device can use N IO as expansion IO. However, since no read signal is input to the output control IO expansion device, the output control IO expansion device can use N + 1 IOs as expansion IOs. Similarly, in the case of FIG. 5C, a select signal, a write signal, and a data signal are input to the output control IO expansion device, and the output control IO expansion device can use N expansion IOs. Since no write signal is input to the input control IO expansion device, the input control IO expansion device can use N + 1 IOs as expansion IOs. Therefore, in the configuration of this embodiment, the IO of the IO expansion device can be utilized to the maximum extent.

  FIG. 5 shows the number of IOs of the IO expansion device when the polling method is adopted. However, in the polling, the CPU 10 needs to read at a constant cycle, so that the load on the CPU 10 increases. On the other hand, apart from this polling method, there is a method called an interrupt method. The interrupt method is a method of detecting a change in each sensor signal input in the CPLD 1 and notifying the CPU 10 by an interrupt signal when the change is detected. In this method, the load on the CPU 10 can be reduced.

  FIG. 6 is a diagram for specifically explaining the number of IOs that can be used by the IO expansion device when the interrupt method is adopted. In the case of a collective interrupt in which the detection of a plurality of sensor signals is notified to the CPU 10 by one interrupt. Show. In this case, CPLD1 and CPLD2 have an interrupt controller function for controlling interrupts. The CPLD1 interrupt controller function outputs a collective interrupt signal to the CPU 10 when it detects a sensor signal, and when the CPU 10 receives the collective interrupt signal, the CPLD1 To determine which sensor signal has changed.

  CPLD1 and CPLD2 are general-purpose logic devices, and power supply / GND and clock input are essential. The remaining IOs are called user IOs, and can be freely used by users. Assume that there are 25 user IOs in CPLD1 and CPLD2. In CPLD1, there are a total of 15 select signals, write signals, read signals, 8 data signals, 3 address signals, and collective interrupt signals, so the remaining 10 are used as expansion IOs (inputs 0 to 9). can do. On the other hand, in CPLD2, since the select signal, the write signal, the eight data signals, and the three address signals are 13 in total, the remaining 12 can be used as the expansion IO (outputs 0 to 11). Therefore, in the interrupt method, the number of IOs that can be used by the added IO expansion device can be further increased. In this embodiment, the number of data signals is eight, but the number of data signals is not limited to eight. In this embodiment, three address signals are used, but the number of address signals is not limited to three.

  FIG. 7 is an example of a register provided in CPLD1 and CPLD2 when the collective interrupt method is employed. CPLD1 and CPLD2 have three bits (eight) registers defined by three address signals, for example, output control register 1, output control register 2, input control register 1, input control register 2, interrupt factor register 1, an interrupt factor register 2, an interrupt factor clear register 1, and an interrupt factor clear register 2 are prepared.

  The output control register 1 (000) is an 8-bit register, and each bit corresponds to eight expansion IOs of the output control IO expansion device, and the expansion IO signal output from the CPLD 2 by rewriting each bit. (Outputs 0 to 7) can be controlled.

  The output control register 2 (001) is an 8-bit register, and each bit corresponds to four expansion IOs of the output control IO expansion device. Although the register has 8 bits, only the lower 4 bits are actually used, and the extended IO signals (outputs 8 to 11) output from the CPLD 2 can be controlled by rewriting each bit.

  The input control register 1 (010) is an 8-bit register, and each bit corresponds to eight expansion IOs of the input control IO expansion device. By reading each bit, the expansion IO input to the CPLD1 It is possible to know the state of the signals (inputs 0 to 7).

  The input control register 2 (011) is an 8-bit register, and each bit corresponds to two expansion IOs of the input control IO expansion device. Although the register is 8 bits, only the lower 2 bits are actually used, and the state of the extended IO signal (inputs 8 and 9) input to the CPLD 1 can be known by reading each bit. .

  In the interrupt factor register 1 (100), when the state of any one of the 8 bits of the input control register 1 changes, the value of the corresponding bit becomes “1”. When the value of any of the bits including the interrupt factor register 2 described later is “1”, the CPLD 1 outputs a collective interrupt signal to the CPU 10. In response to read access from the CPU 10, the CPLD 1 returns the value of the interrupt factor register 1.

  In the interrupt factor register 2 (101), when the state of any one of the two bits of the input control register 2 changes, the value of the corresponding bit becomes “1”. When the value of any of the bits including the interrupt factor register 1 is “1”, the CPLD 1 outputs a collective interrupt signal to the CPU 10.

  The interrupt factor clear register 1 (110) corresponds to the interrupt factor register 1, and when “1” is written to each bit of this register, the value of the bit of the corresponding interrupt factor register 1 is “0”. Cleared to "".

  The interrupt factor clear register 2 (111) corresponds to the interrupt factor register 2, and when “1” is written to each bit of this register, the value of the bit of the corresponding interrupt factor register 2 is “0”. Cleared to "".

  Next, a method of controlling CPLD1 and CPLD2 having the configuration shown in FIG. 6 using the register having the configuration shown in FIG. 7 will be described. First, input expansion IO control (control of the IO expansion device 40 for input control) will be described with reference to the flowchart of FIG.

  First, when one of the extended IO signals (inputs 0 to 9) input to CPLD1 changes (S101), register control unit 41 of CPLD1 outputs a collective interrupt signal to CPU 10 (S102).

  When detecting the collective interrupt signal (S103), the CPU 10 reads the interrupt factor register 1 (S104), and determines whether the value of any bit of the interrupt factor register 1 is “1” (S105). When the value of any bit of the interrupt factor register 1 is “1”, the CPU 10 reads the input control register 1 to check the state of the input signal (S106), and executes processing corresponding to each bit. Thereafter, the interrupt factor register 1 is cleared (S107), and the process returns to S104.

  On the other hand, when the values of all the bits of the interrupt factor register 1 are “0”, the CPU 10 reads the interrupt factor register 2 (S108), and the value of any bit of the interrupt factor register 2 is “1”. It is determined whether or not there is (S109). When the value of any bit of the interrupt factor register 2 is “1”, the CPU 10 reads the input control register 2 to check the state of the input signal (S110), and executes processing corresponding to each bit. Thereafter, the interrupt factor register 2 is cleared (S111), and the process returns to S108.

  The above flow will be described by taking as an example a case where the input / output control circuit of this embodiment is incorporated in an MFP. Assume that the state of the input 4 among the inputs 1 to 10 shown in FIG. 6 has changed. Here, the input 4 is a signal from the front cover opening / closing sensor of the MFP. When the state of the input 4 changes, the value of bit 4 of the interrupt factor register 1 becomes “1”, and a collective interrupt signal is output to the CPU 10. When detecting the collective interrupt signal, the CPU 10 reads the interrupt factor registers 1 and 2 and specifies which input signal has changed. After specifying the input signal, the input control register 1 is read to check whether the input 4 is currently in the “0” or “1” state. After checking the status, perform the corresponding processing (here, “front cover is open” display processing), and finally write “1” to bit 4 of interrupt factor clear register 1 to set interrupt factor register 1 clear.

  Next, output expansion control (control of the IO expansion device 50 for output control) will be described with reference to the flowcharts of FIGS. The output expansion IO control includes data writing and output value confirmation (reading).

  In the data writing, data is written to the output control registers of both CPLD1 and CPLD2 by the write access by the CPU 10 (S201). At this time, since no signal is output from CPLD2, only the output signal output from CPLD2 changes (S202). In confirming the output value, the CPU 10 reads the output control register (S301). At this time, since no read signal is input to CPLD2, CPLD1 returns the value of the output control register instead of CPLD2 (S302).

  The above flow will be described with a specific example. Assume that the state of output 0 shown in FIG. 6 is to be changed from “1” to “0”. Here, the signal of output 0 is a control signal for turning off the power of a certain device. The CPU 10 writes “0” in bit 0 of the output control register 1. At this time, the value of the output control register in CPLD1 is also rewritten at the same time. In response to the bit 0 of the output control register 1 being changed to “0”, the CPLD 2 changes the output 0 signal output from the CPLD 2 to “0”.

  When the CPU 10 confirms whether the output 0 signal has changed correctly, it reads the output control register. In the configuration of this embodiment, since the read signal is not connected to CPLD2, CPLD2 cannot respond to the register value of the output control register in response to the read request. However, since the output control register of CPLD1 holds the same value as the output control register of CPLD2, CPLD1 can return the register value. Thereby, the CPU 10 can read and confirm the register value of the output control register actually output from the CPLD2 from the CPLD1.

  The present invention is not limited to the above embodiment, and the configuration and control of the input / output control circuit can be changed as appropriate without departing from the spirit of the present invention.

  For example, in the above embodiment, the CPU 10 has a three-channel parallel bus, and device A is connected to channel 1, device B is connected to channel 2, and devices C1 and C2 are connected to channel 3. Further, as long as the input control IO expansion device 40 and the output control IO expansion device 50 are connected, the number of buses of the CPU 10 and the devices connected to the respective channels are arbitrary.

  The present invention can be used for an input / output control circuit in which a plurality of IO expansion devices are connected on the same channel of a bus, and a synchronization control method for a plurality of IO expansion devices in the input / output control circuit.

10 CPU
20 Nor-Flash memory 30 Nor-Flash memory 40 IO expansion device for input control 41 Register control unit 42 Input control register 43 Output control register 50 IO expansion device for output control 51 Register control unit 52 Input control register 53 Output control register

Claims (14)

An input / output control circuit in which a plurality of IO expansion devices are connected to the same channel of a specific bus of a CPU,
The plurality of IO expansion devices are configured with an IO expansion device for input control and an IO expansion device for output control,
Each of the IO expansion devices has a register control unit configured with the same circuit,
No read control signal is input to the output control IO expansion device,
In the write access from the CPU, the data output from the CPU is written to the IO expansion device for input control and the IO expansion device for output control.
In the read access from the CPU, only the IO expansion device for input control responds and outputs the value of the register managed by the register control unit.
An input / output control circuit characterized by that. In the write access, the data is written to a register managed by the register control unit of the IO expansion device for input control and a register managed by the register control unit of the IO expansion device for output control,
In the read access, the CPU can check the data written in the register of the output control IO expansion device by reading the value of the register of the input control IO expansion device.
The input / output control circuit according to claim 1. Each of the IO expansion devices has an interrupt controller function that detects a change in an input signal input from the outside and notifies the CPU of an interrupt signal when the input signal changes.
The input / output control circuit according to claim 1 or 2. A plurality of input signals are input to the IO control device for input control,
The interrupt controller function of the IO expansion device for input control writes a value corresponding to the state of each input signal to each bit of the specific register, and when the value of any bit changes, the collective interrupt signal is sent to the CPU Notify
The CPU can identify an input signal whose state has changed by reading the value of each bit of the specific register after receiving the collective interrupt signal.
The input / output control circuit according to claim 3. The CPU can initialize a value of a bit of the specific register corresponding to the predetermined bit of the other register by writing a predetermined value to a predetermined bit of another register different from the specific register.
The input / output control circuit according to claim 4. An input / output control circuit in which a plurality of IO expansion devices are connected to the same channel of a specific bus of a CPU,
The plurality of IO expansion devices are configured with an IO expansion device for input control and an IO expansion device for output control,
Each of the IO expansion devices has a register control unit configured with the same circuit,
No write control signal is input to the input control IO expansion device, and the read control signal input to the output control IO expansion device is the output control IO expansion device. Is fixed to an inactive logic level within
In write access from the CPU, data output from the CPU is written only in the IO expansion device for output control.
In the read access from the CPU, only the IO control device for input control to which an active read control signal is input responds and outputs the value of the register managed by the register control unit.
An input / output control circuit characterized by that. Each of the IO expansion devices has an interrupt controller function that detects a change in an input signal input from the outside and notifies the CPU of an interrupt signal when the input signal changes.
The input / output control circuit according to claim 6. The plurality of IO expansions in an input / output control circuit in which a plurality of IO expansion devices are connected to each other on the same channel of a specific bus of the CPU, the IO expansion devices for input control and the IO expansion devices for output control. A device synchronization control method comprising:
Each IO expansion device is provided with a register control unit composed of the same circuit,
The output control IO expansion device does not input a read control signal,
In the write access from the CPU, the data output from the CPU is written in the IO expansion device for input control and the IO expansion device for output control.
In the read access from the CPU, only the IO expansion device for input control responds and outputs the value of the register managed by the register control unit.
A synchronization control method characterized by the above. In the write access, the data is written to a register managed by the register control unit of the IO expansion device for input control and a register managed by the register control unit of the IO expansion device for output control,
In the read access, the CPU confirms the data written in the register of the output control IO expansion device by reading the value of the register of the input control IO expansion device.
The synchronization control method according to claim 8, wherein: Provide an interrupt controller function for each IO expansion device,
The interrupt controller function of the IO control device for input control detects a change in an input signal input from the outside, and notifies the CPU of an interrupt signal when the input signal changes.
The synchronous control method according to claim 8 or 9, characterized in that When a plurality of input signals are input to the IO control device for input control,
The interrupt controller function of the IO expansion device for input control writes a value corresponding to the state of each input signal to each bit of the specific register, and when the value of any bit changes, the collective interrupt signal is Notify the CPU,
The CPU specifies the input signal whose state has changed by reading the value of the specific register after receiving the collective interrupt signal.
The synchronous control method according to claim 10. The CPU initializes a value of a bit of the specific register corresponding to the predetermined bit of the other register by writing a predetermined value to a predetermined bit of another register different from the specific register.
The synchronization control method according to claim 11, wherein: The plurality of IO expansions in an input / output control circuit in which a plurality of IO expansion devices are connected to each other on the same channel of a specific bus of the CPU, the IO expansion devices for input control and the IO expansion devices for output control. A device synchronization control method comprising:
Each of the IO expansion devices is provided with a register control unit configured with the same circuit,
A write control signal is not input to the input control IO expansion device, and a read control signal input to the output control IO expansion device is input to the output control IO expansion device. To the inactive logic level,
In the write access from the CPU, the data output from the CPU is written only in the IO expansion device for output control.
In the read access from the CPU, only the IO control device for input control to which an active read control signal is input responds and outputs the value of the register managed by the register control unit.
A synchronization control method characterized by the above. Provide an interrupt controller function for each IO expansion device,
The interrupt controller function of the IO control device for input control detects a change in an input signal input from the outside, and notifies the CPU of an interrupt signal when the input signal changes.
The synchronous control method according to claim 13, wherein:

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