JPH11250007A - Serial access system and device used for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce signal lines between devices with simple constitution, to eliminate wasteful transmission time and to transmit necessary information. SOLUTION: The serial access system changes an address signal A1 which is used between memories 102 and is made to be serial, the number of bits on a data signal D1 which is made to be serial, an address signal A2 which is used between a micro processor 101 and an I/O device 103 and which is made to be serial and the number of bits on a data signal D2 which is made to be serial in accordance with the memory 102 and the I/O device 103 from the micro processor 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a serial access system in which access between devices is performed using a serialized address signal and a serialized data signal. The present invention particularly relates to a serial access system that changes the number of bits of a serialized address signal or the number of bits of a serialized data signal according to a device.

[0002]

2. Description of the Related Art Conventionally, in a system including a main device and a plurality of peripheral devices, access between devices is performed by a parallel address signal, a parallel data signal, and some other signals. However, in this system, the number of output terminals of the address signal and the data signal is steadily increased, and the number of pins of the device is correspondingly increased, resulting in an expensive package. For this reason, there have been problems such as an increase in the number of signal lines between devices and an increase in the size of the substrate, and a need for a multilayer substrate to reduce the size of the substrate. As one method for solving this problem, there is a method of transferring data between devices by combining an address signal and a data signal into a serial bus as disclosed in Japanese Patent Application Laid-Open No. 5-173958.

However, this conventional technique has the following problems. First, although the number of signal lines between the devices is reduced, the number of bits required for exchanging one data signal between the devices is large because the address signal and the data signal are serialized together into one signal line. And it can't be much faster.

[0004] Second, a transmitting side requires a synthesizing circuit for synthesizing an address signal and a data signal, and a receiving side requires a separating circuit for separating these signals.
In addition, a complicated control circuit and control software are required for an arbitration function related to access through a bus connection.

Third, due to such a problem, this serial access system cannot be used between a microprocessor and a memory. In an actual system, a conventional parallel data bus is used between a processor and a memory. And a parallel address bus, and a specific peripheral IC uses the serial bus. For this reason, both signal lines are required, which eventually increases the number of pins of the microprocessor.

In order to solve such a drawback, Japanese Patent Application Laid-Open Nos. 5-53858 and 9-69074 disclose an address signal and a data signal for exchanging an address signal and a data signal between devices. It has been proposed to serialize data signals with a predetermined number of bits. However, when serializing a main device to a plurality of peripheral devices and transmitting an address signal and a data signal with a predetermined number of bits, the optimum number of bits often differs depending on each peripheral device. In particular, in the case of a device having a bit number larger than the bit number of the transmitted address signal and data signal, the transmitted signal has a shortage of information. Further, if the device receiving the signal has a smaller number of bits than the number of bits of the serialized and transmitted address signal and data signal, an extra signal is sent, and the transmission time becomes longer.

In particular, when a serialized address signal and data signal are transmitted from a microprocessor to a memory and written to the memory, even if an address signal smaller than the number of bits of the memory is transmitted, the address information is small. Cannot use memory with a large number of bits.

The number of pins of the memory changes between a memory having a small number of bits (for example, a 16-bit memory) and a memory having a large number of bits (for example, a 24-bit memory). A 16-bit memory can be attached to the bit memory terminal. In this case, it is desired that the data input / output terminal and the address input / output terminal are shared so that any of the memories can be used. However, when the number of bits of the address signal to be transmitted is fixed, the above-described disadvantage occurs because the number of bits of the signal is not appropriate for at least one of the memories.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional disadvantages and to provide a serial access system capable of transmitting a required amount of information without using useless transmission time.

[0010]

In order to achieve the above object, the present invention provides a main device, first and second peripheral devices connected to the main device, and a first peripheral device connected to the main device. Means for outputting a first address signal having a predetermined number of bits serialized to the device, and means for outputting an address signal having another number of bits serialized to the second peripheral device from the main device. Have. In the present invention, further, means for transmitting and receiving a first data signal having a predetermined number of bits serialized between the main device and the first peripheral device, and between the main device and the second peripheral device Means for transmitting and receiving a second data signal having another serialized bit.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the serial access system according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the serial access system according to the present invention. In the figure,
Reference numeral 101 denotes a microprocessor constituting a main device. The microprocessor 101 has two sets of serialized address signals and data signals. A memory 102 is one of the peripheral devices. Memory 102
Is a 16-bit memory corresponding to the serialized address signal A1 and the serialized data signal D1. 1
An I / O device 03 is another peripheral device.
The I / O device 103 is, for example, a communication processor, a communication interface, a printer interface, or the like, and corresponds to the serialized address signal A2 and the serialized data signal D2.

Microprocessor 101 and memory 102
Lines 104 to 109 are provided between the microprocessor 101 and the I / O device 103.
04 and lines 110 to 114 are provided. Track 10
4, a clock signal CK is supplied from the microprocessor 101 to the memory 102 and the I / O device 103. Microprocessor 10 through line 105
1 to the memory 102 are supplied with a serialized first address signal A1. The microprocessor 10
The transmission and reception of the serialized first data signal D1 is performed through the line 106 between the memory 1 and the memory 102. The chip select signal is a signal for selecting a partner device and setting an access period, and the first chip select signal CS1 is transmitted through the line 107 to the microprocessor 101.
To the memory 102. Further, a first read signal RD1 and a first write signal are supplied from the microprocessor 101 to the memory 102 through lines 108 and 109, respectively. First read signal R
D1 is the data signal D1 written in the memory 102
And the first write signal WR1
Is a signal for writing the data signal D1 to the memory 102.

A second address signal A2, a second chip select signal CS2, a second read signal RD2, a second read signal RD2 serialized from the microprocessor 101 to the I / O device 103 by the lines 110, 112 to 114. The write signal WR2 is supplied. Further, the microprocessor 101 and the I / O device 10 are connected by the line 111.
Transmission and reception of the serialized second data signal are performed between the three.

In FIG. 1, if the memory 102 is a 16-bit microcomputer, the first address signal A1 is 2 bits.
Four bits are required, and 16 bits are sufficient for the first data signal. Assuming that the I / O device 103 is a communication interface, the second address signal is 4
Eight bits are sufficient for the bit and the second data signal D2. As described above, the optimal number of bits of the address signal and the data signal differs depending on the device connected to the microprocessor 101. First or
By selecting the second chip select signals CS1 and CS2, the memory 102 or the I / O device 103 is selected, and the first or second address signal A is selected.
1, A2 and the first or second data signal D1, D2
2 is selected. Chip select signals CS1 and CS2
If both are selected, it is possible to access both the microcomputer 102 and the I / O device 103 simultaneously,
The processing speed of the microprocessor 101 is increased.

FIGS. 2A and 2B are time charts of the serial access system shown in FIG. FIG.
(A) shows 16-bit microprocessors 101 and 16
6 is a time chart between the memories 102 having a bit configuration,
A case where a 24-bit address signal A1 and a 16-bit data signal D1 are serialized in synchronization with a clock signal CK is shown. The access period of the address signal A1 and the data signal D1 is determined by the chip select signal CS1, and the access of the address signal A1 and the data signal D1 is performed during this period. When reading data stored in the memory 102, the read signal D1 is made active (in FIG. 2A, it is kept at a low level during this period). In FIG. 2A, the access period and the number of bits of the address signal A1 and the data signal D1 are determined by the chip select signal CS1, and when data is read from the memory 102, the read signal RD1
Is sent to the memory 102. The address signal A1 determines the read position of the memory 102, and the data D1 stored at that position is stored in the microprocessor 101.
Is read out.

FIG. 2B is a time chart showing access between the microprocessor 101 and an I / O device 103 such as a communication interface. Such I /
In the O device 103, the address signal A2 may be about several bits (in the figure, a 4-bit address signal), and the data signal D2 is suitably about 8 bits. In this figure, the I / O device 10 designated by the chip select signal CS2
3 is the data signal D of the I / O device 103 specified by the address signal A2 during the period specified by the signal CS2.
2 is read by the read signal RD2.

As described above, in this embodiment, the number of bits of the address signals A1 and A2 and the number of bits of the data signals D1 and D2 can be changed by the partner device accessing the microprocessor 101. There is no inaccurate transmission of information due to lack, and no waste of transmission time due to the unnecessarily large number of bits. Also, since the number of bits of the address signals A1, A2 and the data signals D1, D2 can be set freely,
For example, using a package having the same number of pins, a device such as a memory having a free configuration can be used regardless of whether it is 8 bits or 16 bits.

Further, a 4-bit microcomputer, an 8-bit microcomputer with improved functions, and a 16-bit microcomputer using the same substrate can be used.

In the embodiment of FIG. 1, each of the address signal A1 or A2 and the data signal D1 or D2 is serialized to one line, but in the present invention, it is necessary to serialize only one line. However, serialization may be performed by dividing into a plurality of lines such as two or three lines. As a result, an increase in the number of bits can be prevented, and a delay in access can be suppressed. In FIG. 1, the address signal A1 and the data signal D1 can be serialized and transmitted using two transmission lines. For example, the address signal A1 may be divided into an upper address signal AH and a lower address signal AL, and the data signal D1 may be divided into an upper data signal DH and a lower data signal DL to be serialized and exchanged. Microprocessor 101 to memory 102
Is read out, the 24-bit address signal A1 is divided into an upper address signal AH of 12 to 23 bits and an address signal AL of 0 to 11 bits, serialized and transmitted to the memory 102. The data signal D1 at the memory location determined by the address signals AH and AL is set to the upper data signal DH of 8 to 15 bits and 0
The data may be serialized and read out by dividing it into a lower data signal DL of up to 7 bits and input to the microprocessor 101.

Although an example has been described in which the address signal A1 and the data signal D1 are serialized two by two, another combination may be used. 24-bit address signal A
In the case of 1, for example, an 8-bit serial signal may be divided into three lines. That is, the upper address signal AH of 16 to 23 bits, the middle address signal AM of 8 to 15 bits, and the lower address signal AL of 0 to 7 bits may be transmitted separately. Further, serial transmission may be performed using two lines by dividing the data into 16 bits and 8 bits. In addition to dividing the data signal D1 into 8 bits,
Bits and 6 bits may be used, and the combination is arbitrary. Further, only the address signal A1 or only the data signal D1 may be divided into a plurality of pieces and serialized.

FIG. 3 is a block diagram showing an embodiment for serializing an address signal and a data signal in the microprocessor of FIG. In the figure, reference numeral 301 denotes a clock generation unit for generating a clock signal CK required as a synchronization signal for serialization. In the case of a microprocessor, a system clock may be used. This clock signal C
K is output through an output buffer amplifier 311 to an output terminal 314.
Is output to Reference numeral 302 denotes an address generator, and the address generator 303 outputs a parallel address signal.
Reference numeral 307 denotes a parallel-serial converter for serializing a parallel address signal output to the output line 303 of the address generation unit 302, and a clock signal C from the clock generation unit.
In synchronization with K, a serially converted address signal A1 having a bit number determined by a control signal from the bit number control unit is output. The address signal A1 is output to the terminal 315 through the output buffer amplifier 312.

Reference numeral 304 denotes a data control unit for generating a data signal or taking in a data signal. A parallel data signal is output to an output line 305, and a parallel data signal is input to an input line 306. . 308
Is a parallel / serial converter for serializing a parallel data signal, 309 is a serial / parallel converter for parallelizing a serial input data signal, and 310 is a bit number control for adjusting the number of bits for parallel / serial conversion or serial / parallel conversion The section adjusts the number of bits of the address signal A1 and the data signal D1 depending on the peripheral device to be accessed. The serialized data signal D1 input from the terminal 316 through the input / output buffer amplifier 313 is input to the serial-to-parallel converter 309, which synchronizes with the clock signal CK1 from the clock generator 301 to control the number of bits. The number of bits is adjusted by the control signal from the unit 310, converted into a parallel data signal, and supplied to the data control unit 304 via the line 306.

The parallelized data signal from the data control unit 304 is passed through a line 305 to a parallel / serial conversion unit 308.
Is synchronized with the clock signal CK from the clock generation unit 301, is converted into a serialized data signal D1 having the number of bits determined by the bit control signal from the bit number control unit 310, and is output to the terminal 316 of the input / output buffer amplifier 316. Is done. FIG. 3 shows a circuit for outputting the serialized address signal A1 and the serialized data signal D1, but the serialized address signal A2 and the data signal D1 having different numbers of bits from the address signal A1. Serialized data signal D with different number of bits
2 can be output using a similar circuit.

FIG. 4 is a block diagram showing another embodiment of the serial access system according to the present invention. The figure shows a system using a microprocessor in which address signals A1 and A2 and data signals D1 and D2 are serialized, a memory for inputting and outputting parallel address signals and data signals, and an I / O device. Reference numeral 401 denotes a microprocessor in which an address signal and a data signal are serialized. The number of bits of the address signals A1 and A2 and the number of bits of the data signals D1 and D2 are different from each other as in the case of FIG. Reference numeral 402 denotes a conventional type memory which inputs a parallel address signal PA1 and inputs / outputs a parallel data signal DP1, and 403 inputs a parallel address signal AP2 and inputs a parallel data signal AP1.
2 are input / output devices. An interface circuit 404 connects the microprocessor 401 and the memory 402. The interface circuit 404 converts the serial address signal A1 into an n-bit parallel address signal AP1 and converts the serialized data signal D1 into an n-bit data signal D1. A serial-parallel conversion for converting the data signal into a parallel data signal DP1 and a parallel-serial conversion for converting the n-bit parallel data signal AP1 from the memory 402 into a serial data signal D1 are performed. Reference numeral 405 denotes an interface circuit for connecting the microprocessor 401 and the I / O device 403, and has the same function as the interface circuit 404 of 404. The chip select signal CS1, read signal RD1, and write signal WR1 from the microprocessor 401 are directly input to and output from the memory 402.
Further, the chip select signal CS2, read signal RD2, and write signal WR2 from the microprocessor 401 are directly input / output to the I / O device 403, respectively.

In the embodiment shown, the memories 402 and I
Even if the / O device 403 is of a type that inputs and outputs parallel signals, the interface circuits 404 and 40
5, the serialized address signals A1, A2 and the data signals D1, D2 according to the present invention.
Can be used.

FIG. 5 is a block diagram showing still another embodiment of the serial access system according to the present invention. In this embodiment, signal lines necessary for access to peripheral devices are shown in FIG.
Are provided more than the signal lines shown in FIG.
The RAM and the I / O device can be simultaneously accessed while the OM is being accessed, or when several I / O devices such as a communication interface and a printer interface are provided, these interfaces can be simultaneously accessed. .

In the figure, 501 is a microprocessor, 502 is a read only memory (ROM), 503 is a random access memory (RAM), and 504 is an I / O device such as a communication processor. The microprocessor 501 and the ROM 502 are connected by lines 505 to 509. The clock signal CK and the address signal A are supplied to the ROM 502, the data signal D is read, and the first chip select signal CS1 and the The supply of the read signal RD to the ROM 502 is performed. The microprocessor 501 and the RAM 503 are connected by lines 505 to 507 and 509 to 511. The clock signal CK and the address signal A are supplied to the RAM 503 through the lines 505 to 507 and 509, respectively, and the data signal D is transmitted and received. RD RAM50
3 is provided. The second chip select signal CS1 is supplied to the RAM 503 through the line 510, and the write signal WR is supplied to the RAM through the line 511. Microprocessor 501 and I / O device 50
4 are connected by lines 505-507, 509, 511, 512, and lines 505-507, 509,
511, the clock signal CK and the address signal A
To the I / O device 504, transmission and reception of the data signal D, supply of the read signal RD and the write signal WR to the I / O device 504, and the I / O of the third chip select signal CS3 through the line 512. The supply to the device 504 is performed.

In the figure, the clock signal CK, the address signal A, the data signal D, the read signal RD, and the write signal WR are commonly used, and the chip select signals CS1, CS2,
In CS3, three peripheral devices, ROM 502 and RA
M 503 and I / O 504 are selected and accessed. Although the timing chart of each signal is not particularly shown, as described with reference to FIG.
3, the number of bits of the address signal A and the number of bits of the data signal D are changed between when accessing the I / O device 504. The number of bits of the address signal A and the data signal D can be determined by which of the chip select signals CS1, CS2 and CS3 is selected.

[0029]

According to the present invention, a serialized address signal is supplied from a main device to a plurality of peripheral devices, and a serialized data signal is transmitted and received between the main device and the plurality of peripheral devices. Since the number of pins of the device is reduced and the number of bits of the address signal and data signal is changed depending on the peripheral device, incomplete transmission of signals due to insufficient number of bits and loss of transmission time due to too many bits are prevented. Can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a serial access system according to the present invention.

FIG. 2 is a time chart of the serial access system shown in FIG. 1;

FIG. 3 is a block diagram showing one embodiment for serializing an address signal and a data signal in the microprocessor of FIG. 1;

FIG. 4 is a block diagram showing another embodiment of the serial access system according to the present invention.

FIG. 5 is a block diagram showing still another embodiment of the serial access system according to the present invention.

[Explanation of symbols]

101, 401, 501 ... microprocessor, 10
2, 402: memory, 103, 403, 504: I / O
Device, 301 clock generator, 302 address generator, 303 parallel address signal, 304 data controller, 307, 308 parallel-serial converter, 309
Serial-to-parallel converter, 310... Bit number control unit, 311, 3
12: output buffer amplifier, 313: input / output buffer amplifier, 404, 405: interface circuit, 502
... ROM, 503 ... RAM.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinya Imanishi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Multimedia Systems Development Division of Hitachi, Ltd. (72) Inventor Yuji Hatanaka Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa 292 Hitachi Multimedia Systems Development Headquarters, Ltd. (72) Inventor Masatoshi Miyakoshi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref. Hitachi, Ltd.Video Information Media Division (72) Inventor Koichi Takagi Kanagawa Prefecture 292 Yoshida-cho, Totsuka-ku, Yokohama-shi Multimedia System Development Division, Hitachi, Ltd.

Claims (10)

[Claims] 1. A main device, first and second peripheral devices connected to the main device, and a first bit having a predetermined number of bits serialized from the main device to the first peripheral device. A serial access system comprising: means for outputting an address signal; and means for outputting an address signal having another number of bits serialized from the main device to the second peripheral device. Means for transmitting and receiving a serialized first data signal between said main device and said first peripheral device; and means for serializing between said main device and said second peripheral device. 2. A serial access system according to claim 1, further comprising means for transmitting and receiving said second data signal. 3. A first device having a predetermined number of bits serialized between the main device and the first peripheral device.
And a means for transmitting and receiving a second data signal having another serialized bit between the main device and the second peripheral device. The serial access system according to claim 1. 4. A main device, first and second peripheral devices connected to the main device, and a first having a predetermined number of bits serialized between the main device and the first peripheral device. And a means for transmitting and receiving a data signal having another number of bits serialized between the main device and the second peripheral device. Access system. 5. A means for supplying a serialized first address signal from said main device to said first peripheral device, and a second address serialized from said main device to said second peripheral device. 5. The serial access system according to claim 4, further comprising means for supplying a signal. 6. A first circuit for generating a first chip select signal.
Chip select generating means, a second chip select signal generating means for generating a second chip select signal, a serialized first address signal having a predetermined number of bits, and a serialized second address signal having another number of bits. And a first and a second peripheral device connected to the main device, the main device having an address signal generating means for selectively generating the first chip select signal, and generating the first chip select signal. Supplying the first address signal to the first peripheral device, and generating a second chip select signal, thereby supplying the second address signal to the second peripheral device. And a serial address system. 7. Generating the first chip select signal to transmit and receive a serialized first data signal having a predetermined number of bits between the main device and the first peripheral device. And transmitting and receiving the serialized second data signal of another number of bits between the main device and the second peripheral device by generating the second chip select signal. 7. The serial address system according to claim 6, wherein 8. A main device, first and second interfaces connected to the main device, a first peripheral device connected to the first interface, and a first peripheral device connected to the second interface. A second peripheral device; means for outputting a first address signal of a predetermined number of bits serialized from the main device to the first interface;
Means for transmitting and receiving a serialized first data signal of a predetermined number of bits between the interfaces, and outputting a second address signal of another serialized number of bits from the main device to the second interface Means for transmitting and receiving a serialized second data signal of another number of bits between the main device and the second interface, and parallelizing the first address signal to generate the first data signal. Means for supplying from the interface to the first peripheral device; means for transmitting and receiving a signal obtained by parallelizing the first data signal between the first interface and the first peripheral device; Means for parallelizing the second address signal and supplying it from the second interface to the second peripheral device; Serial access system, characterized in that it consists of a means for performing exchange of parallelism signal of the first data signal between the face and said second peripheral device. 9. A parallel number converting unit for converting a parallel address signal into an address signal having a predetermined number of bits serialized by a control signal from the bit number controlling unit; A parallel / serial conversion unit for converting a signal into a data signal having a predetermined number of bits according to a control signal from the bit number control unit. 10. The device according to claim 9, further comprising a serial-to-parallel converter for converting the input serialized data signal into a parallel data signal.