JP3189746B2 - IC card reader / writer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an IC card reader / writer, and more particularly to a circuit capable of simultaneously accessing a plurality of IC cards.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a configuration of a conventional IC card reader / writer. Conventional IC
The card reader / writer is capable of accessing a plurality of IC cards, and FIG. 9 shows a configuration capable of accessing two IC cards.

The control unit 2 generates VCC1 and VCC2 as power supply signals for the IC card, RST1 and RST2 as reset signals, and CLK as a clock signal. IO which is a data transfer signal of an IC card
1, IO2 are wired-OR connected inside the IC card reader / writer 1. The SD which is a transmission data signal from a host (not shown) and the RD which is a reception data signal to the host are also connected in a wired OR manner inside the IC card reader / writer 1.

A clock signal CLK supplied to an IC card is common to a plurality of IC cards.

[0005]

The above-mentioned conventional IC card has the following problems.

The first problem is that in the conventional IC card reader / writer, communication with the host is half-duplex communication, and high-speed communication cannot be performed.

The reason is that the data transfer signals IO1 and IO2 of the IC card are wired-ORed.

A second problem is that in a conventional IC card reader / writer, it is not possible to simultaneously connect IC cards having different communication procedures.

The reason is that, similarly to the reason of the first problem, the data transfer signals IO1 and IO
2 is wired OR, and the clock signal CLK of the IC card is common.

Therefore, the present invention has been made in view of the above problems, and has as its object to improve the speed of communication with a host and improve the transmission efficiency and to connect an IC card having a different communication procedure. An object of the present invention is to provide an IC card reader / writer which enables the IC card reader / writer.

[0011]

In order to achieve the above object, an IC card reader / writer according to the present invention comprises a plurality of IC card side transmitting / receiving sections for transmitting / receiving data to / from an IC card corresponding to a plurality of IC cards. And a control unit for individually supplying a clock signal and a control signal to each of the plurality of IC cards, so that the plurality of IC cards can be processed simultaneously.

[0012]

Embodiments of the present invention will be described below. In a preferred embodiment, the IC card reader / writer of the present invention has a plurality of IC card side transmitting / receiving sections for accessing a plurality of IC cards. It also has a power supply signal (VCC) control unit, a reset signal (RST) control unit, and a clock signal (CLK) control unit that individually generate control signals for each IC card. In order to process a plurality of IC cards at the same time, an interrupt control unit that controls an interrupt from a plurality of IC card side transmitting / receiving units is provided.

In an embodiment of the present invention, a plurality of I
Since it has a C card side transmission / reception signal and an interrupt control unit, simultaneous processing of a plurality of IC cards is possible.

Also, a power supply signal (VCC) control unit, a reset signal (RST) control unit, a clock signal (CLK)
Since the control unit can individually generate control signals for each IC card, it is possible to simultaneously process IC cards having different communication procedures.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 is a diagram showing the overall configuration of an IC card reader / writer according to an embodiment of the present invention.

Referring to FIG. 1, in the present embodiment, the control unit 4 is connected with an SD signal as a transmission signal from a host (not shown) and an RD signal as a reception signal to the host.

A connection signal with the IC card is transmitted to each IC.
Four connection signals are provided for each card, an IO1 signal for performing data communication with the first IC card, a VCC1 signal for performing power supply to the IC card, an RST1 signal for performing a reset of the IC card, A CLK1 signal for supplying a prescribed frequency to the IC card is connected to the control unit 4. IO2 signal, VCC signal, RST signal,
The CLK2 signal is a signal having the same function as described above, and is a connection signal with the second IC card. Similarly, the IO7 signal, the VCC7 signal, the RST7 signal, and the CLK7 signal
This is a connection signal with the second IC card.

FIG. 2 is a block diagram showing the internal configuration of the control unit 4 in this embodiment. Referring to FIG. 2, the control unit 4 includes a host-side transmission / reception unit 5, a control unit 6, an IC card-side transmission / reception unit 7, an IC card transmission / reception unit 8,
And an IC card transmitting / receiving unit 9.

The SDATA * signal is an 8-bit data signal, and is output from the host transmitting / receiving section 5 to the control section 6. The RDATA * signal is an 8-bit data signal and is output from the control unit 6 to the host-side transmitting / receiving unit 5. The SINT signal is an interrupt request signal to the control unit 6. The SRD signal is a read control signal of the SDATA * signal. The RWR signal is a write control signal for the RDATA * signal. The HCS signal is a selection signal of the host-side transmission / reception unit 5.

The ICCSD * signal is an 8-bit data signal, and is output to the IC card side transmitting / receiving units 7, 8, and 9. The ICCRD * signal is an 8-bit data signal,
IC card side transmitting / receiving units 7, 8, 9 to control unit 6
Output to INT1 signal, INT2 signal and INT
The signal 7 is an interrupt request signal from the IC card side transmitting / receiving units 7, 8, 9 to the control unit 4. ICCS1 signal, I
The CCS2 signal and ICCS7 signal are sent to the control unit 7,
8 and 9 are selection signals. The ICCRD signal is a data read signal of the control units 7, 8, and 9. ICC
The WR signal is a data write signal for the control units 7, 8, and 9.

FIG. 3 shows the host-side transmitting / receiving section 5 shown in FIG.
FIG. 3 is a block diagram illustrating a configuration. Transmission Referring to FIG.
The host-side transmission / reception unit 5 includes a transmission data buffer unit 10 and a reception data buffer unit 11.

FIG. 4 is a block diagram showing the configuration of the IC card transmitting / receiving section 7 shown in FIG. Referring to FIG.
Transmission data buffer unit 12 and reception data buffer unit 1
3 is provided. The other I shown in FIG.
The C card transmitting / receiving section 8 and the IC card transmitting / receiving section 9 have the same configuration.

FIG. 5 is a block diagram showing the configuration of the control unit 6 shown in FIG. Referring to FIG. 6, the control unit 6 includes a CPU unit 14, an interrupt control unit 1
5, a control signal generator 16, a power supply (VCC) controller 17 for supplying power to each IC card, a reset (RST) controller 18 for generating a reset signal for each IC card, and a reset signal for each IC card Is provided. The interrupt control unit 15 receives the interrupt signal SINT from the host-side transmitting / receiving unit 5 and the interrupt signals INT1 to INT7 from the IC card-side transmitting / receiving units 7 to 9, and sends an interrupt request signal to the CPU 14 to the terminal INT of the CPU 14. An address signal from an address terminal AD * of the CPU 14 is connected to a control signal generator 16, a VCC controller 17, an RST controller 18, and a clock controller 19 via an internal address bus.
Is a control signal generator 16, VCC via an internal data bus.
Connected to the control unit 17, the RST control unit 18, the clock control unit 19, and SDATA * (ICCSSD *), RD
It is also connected to ATA * (ICCRD *).

Next, the operation of the present embodiment will be described with reference to the time charts of FIGS. FIG. 6 is a timing chart for explaining the operation when one IC card is connected to the IC card reader / writer of this embodiment.

The host issues an IC card initialization command to the SD card.
The signal is transmitted to the control unit 4 as a signal.

The control unit 6 (see FIG. 2)
After receiving the T signal, data is read from the host-side transmitting / receiving unit 5 and the VCC1 signal, the RST1 signal, and the CLK1 signal are output to the IC card 1.

The IC card 1 receives the VCC1 signal, RST1
An initial response signal of the IC card is output to the IO1 signal according to the signal CLK1.

After receiving the INT1 signal as an interrupt signal from the IC card side transmitting / receiving section 7 corresponding to the IC card 1, the control section 6 reads out the initial response signal of the IC card 1 from the IC card side transmitting / receiving section 7, The initial response signal of the IC card 1 is written to the host-side transmitting / receiving unit 5.

The control unit 4 transmits an initial response signal of the IC card 1 from the IC card transmitting / receiving unit 5 to the host as an RD signal.

Next, the host outputs a command signal to the IC card 1 as an SD signal.

After receiving the SINT signal, the control section 6 reads a command signal for the IC card 1 from the host-side transmitting / receiving section 5 and outputs an IO1 signal to the IC card 1.

The IC card 1 receiving this IO1 signal
Outputs the IO1 signal to the control unit 4 after processing the command signal. After receiving the INT1 signal which is an interrupt signal from the IC card side transmitting / receiving section 7 corresponding to the IC card 1, the control section 6
From the IC card 1 is read.

The control unit 4 writes the processing result of the IC card 1 to the host-side transmitting / receiving unit 5.

The host-side transmitting / receiving section 5 transmits the processing result of the IC card 1 to the host as an RD signal.

FIG. 7 is a time chart for explaining the operation when two IC cards are connected to the IC card reader / writer of this embodiment.

The host sends an initialization command for the IC card 1 to the SD signal. The control unit 4 includes the IC card 1
Output the VCC1 signal, the RST1 signal, and the CLK1 signal.

The IC card 1 outputs an initial response signal to the control unit 4 as an IO1 signal. The control unit 4 transmits an initial response signal of the IC card 1 to the host as an RD signal.

The host transmits an initialization command for the IC card 2 to the control unit 4 as an SD signal.

The control section 4 outputs a VCC2 signal, an RST2 signal, and a CLK2 signal to the IC card 2.

The IC card 2 transmits the initial response signal to the control unit 4 as an IO2 signal. The control unit 4 transmits an initial response signal of the IC card 2 to the host as an RD signal.

Next, the host transmits a command signal for the IC card 1 and the IC card 2 to the control unit 4 as an RD signal.

The control unit 4 includes the IC cards 1 and I
A command signal for the C card 2 is transmitted to the IC card 1 and the IC card 2 as an IO1 signal and an IO2 signal.

The IC card 1 outputs the command processing result to the control unit 4 as an IO1 signal. Control part 4
Transmits the command processing result of the IC card 1 to the host as an RD signal.

The IC card 2 outputs the command processing result to the control unit 4 as an IO2 signal. Control part 4
Transmits the command processing result of the IC card 2 to the host as an RD signal.

FIG. 8 is a diagram for explaining the operation when two IC cards are connected to the IC card reader / writer 3 of this embodiment, and one of the IC cards has a different communication procedure from the other IC cards. It is a time chart.

In the same manner as in FIG.
The card 2 sends an initial response signal to the host.

The host determines from the initial response signal of the IC card 2 that the IC card 2 is an IC card capable of changing the CLK2 signal which is a clock signal.

The host issues a clock frequency change command to SD
The signal is transmitted to the control unit 4 as a signal.

The control section 4 outputs the CLK2 signal whose clock frequency has been changed to the IC card 2. In addition, a clock frequency change command is transmitted to the IC card 2 as an IO2 signal.

The IC card 2 transmits the change of the clock frequency to the control unit 4 as an IO2 signal.

The control unit 4 transmits to the host that the clock frequency of the IC card 2 has been changed as an RD signal.

As described above, the IC card reader / writer of the present embodiment can perform simultaneous processing on a plurality of IC cards and can simultaneously perform processing on IC cards having different communication procedures.

[0053]

As described above, according to the present invention, the following effects can be obtained.

A first effect of the present invention is that simultaneous processing can be performed on a plurality of IC cards.

The reason is that, in the present invention, an IC card side transmitting / receiving unit is provided for each of a plurality of IC cards to be connected.

A second effect of the present invention is that it is possible to communicate with a plurality of IC cards according to different communication procedures.

The reason is that, in the present invention, each of a plurality of IC cards to be connected is provided with a control section for generating a VCC signal, an RST signal, and a CLK signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an IC card reader / writer according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a control unit according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a host-side transmitting / receiving unit according to an embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of an IC card transmitting / receiving unit according to an embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a control unit according to an embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of one embodiment of the present invention, and is a time chart when one IC card is connected.

FIG. 7 is a time chart for explaining the operation of one embodiment of the present invention, and is a time chart when two IC cards are connected.

FIG. 8 is a time chart for explaining the operation of one embodiment of the present invention, which is a time chart for setting different communication procedures for the IC card.

FIG. 9 is a block diagram showing a configuration of a conventional IC card reader / writer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Conventional IC card reader / writer 2 Control part 3 IC card reader / writer of this invention 4 Control part 5 Host side transmission / reception part 6 Control part 7 IC card side transmission / reception part 8 IC card side transmission / reception part 9 IC card side transmission / reception part 10 Transmission data Buffer unit 11 Receive data buffer unit 12 Transmission data buffer unit 13 Receive data buffer unit 14 CPU unit 15 Interrupt control unit 16 Control signal generation unit 17 VCC control unit 18 RST control unit 19 CLK control unit

Claims (2)

(57) [Claims] A plurality of IC card side transmitting / receiving sections for transmitting / receiving data to / from an IC card are provided for a plurality of IC cards, and a plurality of IC card transmitting / receiving sections are provided for each of the plurality of IC cards.
While sending and receiving data, the plurality of IC cards
A clock signal , a power supply signal,
A control unit for supplying a reset signal, respectively, further
, The process end is split from the plurality of IC card side transceiver
An IC card reader / writer , which is notified to the control unit by a built-in signal to enable simultaneous processing of the plurality of IC cards. 2. A host-side transmitting / receiving unit for controlling transmission / reception of data to / from a host, comprising a plurality of IC-card-side transmitting / receiving units corresponding to a plurality of IC cards for transmitting / receiving data to / from an IC card; A host-side transmission / reception unit;
And a control unit that is disposed between the signal section, the control section, CPU and a VCC controller for generating a power supply signal separately for each of the plurality of IC cards, said plurality of An RST control unit for individually generating a reset signal for each of the IC cards; a CLK control unit for individually generating a clock signal for each of the plurality of IC cards; and an interrupt signal from the host-side transmitting / receiving unit and the interrupt control unit receives an interrupt signal from the plurality of IC card side transceiver issues an interrupt request to the CPU, and seen including, this <br/> and which enables simultaneous processing of the plurality of IC cards An IC card reader / writer characterized by the above-mentioned.