JPH1175227A - Data communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of connections between 1st and 2nd substrates by storing transfer information outputted in parallel from a 1st CPU on a 1st substrate, and converting the transfer information into serial data with a 1st transmission instruction from the 1st CPU and sending the data to a 2nd CPU on a 2nd substrate when the stored transfer information reaches a predetermined prescribed amount. SOLUTION: The CPU 101A writes the information to be sent in a transmitting memory 103A in parallel and outputs the transmission instruction to a control register control circuit 102A when the written information reaches the prescribed amount. The control register control circuit 102A controls the transmitting memory 103A and a parallel-serial conversion part 104A to convert the information in the transmitting memory 103A into serial data, which are sent to the substrate B. The substrate B converts the information sent from the substrate A into parallel data by a serial-parallel conversion part 106B. Consequently, the frequency at which the CPU 101 outputs the transmission instruction can be decreased and a serial communication is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication device, and is applicable to, for example, data communication between CPUs of an exchange.

[0002]

2. Description of the Related Art As shown in FIG.
Is the RO connected via the interface circuit 2.
The M3 and the RAM 4 are appropriately accessed to perform processing, and a plurality of CPU blocks 6A including such elements are used.
In some cases, data communication may be performed between the CPU and the 6B (in other words, between the CPUs).

In such data communication between CPUs, data signals, address signals and control signals are generally transmitted and received. For example, if the CPU is MC68030 (manufactured by Motorola), the data signal and the address signal each have a maximum of 3
Two control signals: AS (address strobe), R
/ W (read / write), ACK (acknowledge), etc. are required. In data communication between CPUs, all of these signals are communicated in parallel, and in the case described above, one set of CPUs is used.
It is necessary to connect them with 67 signal lines.

In an exchange, for example, a CPU
For data communication between, as shown in FIG.
,..., 7 on which CPU blocks 6-1,.
−n are connected to each other by a back board 8.

[0005]

However, in a conventional data communication device between CPUs (for example, an exchange), the CP
Between the board composed of the U block and the backboard,
Since the data signal, the address signal, and the control signal are connected, the number of connectors to be connected increases, and there is a problem that the number of pins of the connector becomes insufficient due to an increase in the number of subscribers. In addition, since the number of connections is increased, there is a problem in that it is generally disadvantageous in terms of mounting.

Actually, in the case of an exchange, in addition to information used for communication between CPUs, main transmission information such as a voice signal is exchanged between boards. When the number of connections used for communication between CPUs is increased, the number of connections used for communication of main transmission information decreases due to physical restrictions, and the number of opposing substrates that can be connected decreases. Conversely, if the number of connections provided for the communication of the main transmission information is increased, the CP
The number of connections provided for communication between U is reduced, and from this point, the number of opposing substrates that can be connected is also reduced.

For this reason, there has been a demand for a data communication device which is advantageous in terms of mounting and which can realize data communication between CPUs in many combinations between CPUs without affecting communication of main transmission information.

[0008]

In order to solve the above-mentioned problems, the present invention provides a method for mounting a first C on a first substrate.
In a data communication device for transmitting and receiving transfer information between a PU and a second CPU mounted on a second substrate,
It has the following means.

That is, (1) the transfer information to be transmitted to the second or first CPU on the opposing second or first substrate is the first and second substrates respectively.
Alternatively, each time the transfer information is output in parallel from the second CPU, the transfer information is sequentially stored, and when the stored transfer information reaches a predetermined specified amount, the first or second transfer information on the own board is stored.
Transmission information storage control means for outputting a specified amount of transfer information in response to one transmission command from the CPU; and (2) each time a specified amount of transfer information is output from the transmission information storage control means, Parallel-to-serial conversion transmission means for converting transfer information into serial data and transmitting the serial data to the opposing second or first substrate; and (3) transmission from the parallel-to-serial conversion transmission means on the opposing second or first substrate. Serial-parallel conversion receiving means for receiving the transfer information, converting the received transfer information into parallel data and outputting the parallel data,
(4) Each time the transfer information is output from the serial / parallel conversion receiving means, the transfer information is stored. When the storage amount reaches a predetermined specified amount, the first or the second data on the own board is stored. In response to one reception command from the CPU 2, the stored transfer information is transferred to the first or second C
Receiving information storage control means for parallel output to the PU.

As described above, according to the present invention, in data communication between CPUs, information to be transmitted is once stored, and when the stored information reaches a certain prescribed amount, the prescribed amount of information is transmitted once by the CPU. Therefore, the number of times the CPU outputs the transmission command can be reduced. Further, by changing from parallel communication to serial communication, the number of connections can be reduced.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

(A) First Embodiment Hereinafter, a first embodiment in which a data communication device according to the present invention is applied to data communication between CPUs in an exchange will be described with reference to the drawings.

As shown in FIG. 1, the first embodiment includes a substrate A and a substrate B. The substrates A and B have the same configuration. Therefore, the configuration of the substrate A will be described below as an example. In FIG. 1, in order to distinguish between the constituent parts of the substrate A and the constituent parts of the substrate B, “A” is added to the constituent parts of the substrate A, and “B” is added to the constituent parts of the substrate B. Attached to

FIG. 1 shows only a configuration related to data communication between CPUs and is not shown. Each of the boards A and B is used for transmitting main transmission information such as an audio signal. Is also provided.

As shown in FIG. 1, a board A is provided with a CPU 10
1A, a control register / control circuit 102A, a transmission memory 103A, a parallel-serial conversion unit 104A, a reception memory 105A, and a serial-parallel conversion unit 106A.
And an intra-substrate CLK unit 107A.

When transmitting information to the board B, the CPU 101A writes the information to be transmitted to the transmission memory 103A, and outputs a transmission command to the control register / control circuit 102A. When receiving the information from the board B, the CPU 101A reads the received information from the reception memory 105A.

The control register / control circuit 102A includes a CP
When the transmission command is output from U101A, the transmission memory 1
By controlling the 03A and the parallel-serial conversion unit 104A, the information written in the transmission memory 103A is output to the parallel-serial conversion unit 104A, and the information that has been serial-converted by the parallel-serial conversion unit 104A is transmitted to the substrate B. Further, the control register / control circuit 102A outputs a frame signal for determining the head position of the data to the substrate B.

The control register / control circuit 102A
Receives information from the board B to the serial / parallel conversion unit 106A and controls the serial / parallel conversion unit 106A and the reception memory 105A to output the information parallel-converted by the serial / parallel conversion unit 106A to the reception memory 105A. Then, the information is written into the reception memory 105A, and an interrupt notifying the reception is output to the CPU 101A.

The transmission memory 103A stores the information written by the CPU 101A in the control register / control circuit 1
02A, the parallel-serial conversion unit 104
A is temporarily stored until output to A.

When information is input from the transmission memory 103A, the parallel-serial conversion unit 104A
Under the control of the control circuit 102A, the input information is converted from parallel to serial, and the converted information is
Send to

When the information is received from the board B, the serial / parallel conversion unit 106A
2A, the input information is converted from serial to parallel, and the converted information is stored in the receiving memory 105A.
Output to

The reception memory 105A stores information output from the serial / parallel conversion unit 106A in the CPU 101A.
Temporarily stored until read.

The in-board CLK unit 107A outputs a CLK signal which is a reference for the board A. All the processing of the substrate A is performed based on this CLK signal. This CLK signal is also output to the substrate B.

The CPU 101A includes a control register / control circuit 102A, a transmission memory 103A, and a reception memory 105A.
And connected to.

The control register / control circuit 102A is connected to the transmission memory 103A, the parallel / serial conversion unit 104A, the reception memory 105A, and the serial / parallel conversion unit 106A.

The transmission memory 103A is connected to a parallel / serial conversion unit 104A, and the reception memory 105A is connected to a serial / parallel conversion unit 106A.

The in-substrate CLK unit 107A is
A, the control register / control circuit 102A, the parallel / serial conversion unit 104A, and the serial / parallel conversion unit 106A.

As an output from the board A to the board B, the control register / control circuit 102A and the parallel / serial converter 1
04A and the in-board CLK 107A are connected to a serial / parallel conversion unit 106B.

As an input from the board B to the board A, the serial / parallel conversion unit 106A includes a control register / control circuit 102B, a parallel / serial conversion unit 104B, and an in-board C
LK107B.

Next, the operation of the first embodiment will be described with reference to an example in which information is transmitted from the substrate A to the substrate B.
This will be described with reference to FIG.

First, information to be transmitted is written in parallel to the transmission memory 103A by the CPU 101A. For example, when the CPU 101A is MC68030 (manufactured by Motorola), a maximum 32-bit parallel data signal is written to the transmission memory 103A by one memory access. The written information has a predetermined amount (as shown in FIG. 5, 101 in this first embodiment).
This write operation is continuously performed until the number of bits reaches 4 bits). When the written information reaches a specified amount, the CPU 101A further outputs a transmission command to the control register / control circuit 102A.

When the control register / control circuit 102A receives the transmission command, it outputs a control signal to the transmission memory 103A and the parallel-serial conversion unit 104A, whereby the information is transmitted from the transmission memory 103A to the parallel-serial conversion unit 104A. And serially converted by the parallel-serial conversion unit 104A, and the serial information is transmitted to the board B via the backboard.

In the board B, the information transmitted from the board A is received by the serial / parallel conversion unit 106B and converted from serial to parallel.

In the control register / control circuit 102B, when the received information is converted into parallel, a control signal is output to the serial / parallel conversion unit 106B and the reception memory 105B.
6B, the information is sequentially output in parallel to the receiving memory 105B, and the information is written to the receiving memory 105B. Further, in the control register / control circuit 102B, when all the controls are completed, an interrupt indicating that the information has been received is output to the CPU 101B.

In the CPU 101B, when an interrupt is output from the control register / control circuit 102B, the received information is read from the reception memory 105B.

The operation of transmitting information from the substrate B to the substrate A is performed in the same procedure.

As described above, C of substrate A and substrate B
Information can be exchanged between PUs. In addition, the method of transmitting information is transmitted in synchronization with the frame signal of the own board, asynchronously with the transmission of the other board.

Therefore, a method of transmitting information in accordance with the frame signal of the own substrate will be described in detail with reference to FIGS. 4 and 6, taking the case where information is transmitted from substrate A to substrate B as an example. I do.

In the output signal pattern as shown in FIG. 4, the substrates A and B are each
An LK signal, a frame signal, and a data signal are output one by one.

Here, the in-board CLK signal is a signal serving as a reference for the frame signal and the data signal, and the other board receives the frame signal and the data signal based on this signal. The frame signal is a signal indicating the head of the data signal.

The data signal is a signal for transmitting and receiving information, and includes a FLAG bit area, an ACK bit area, and an information field data area.
Information to be transmitted is set in the information field data area, a bit indicating whether information is set in the information field data area is set in the FLAG bit area, and an information field is set in the ACK bit area. A bit is set which indicates whether the information set in the data area has been received or not. Here, FL
When "1" is set in the AG bit area, "information is present", and when "1" is set in the ACK bit area, "received". Normally, when no information is exchanged, the FLAG bit and the ACK bit are not “1”, and no information is set in the information field data area.

As shown in FIG. 6, first, the CPU 101A
Depending on the information to be transmitted (step 20)
0), information to be transmitted is written into the transmission memory 103A (step 201), and when the written information reaches a specified amount, the FLAG in the control register / control circuit 102A
After confirming that the register is "0" (step 202), "1" is written to the FLAG register (step 203). Here, if the FLAG register is "1", it means that the previous information is being transmitted, and "1" is written after waiting until the FLAG register becomes "0".

When "1" is written in the FLAG register, the information written in the transmission memory 103A is output to the parallel / serial conversion unit 104A by the control register / control circuit 102A, and is converted into serial data. FLAG in the data signal output to
"1" is set in the bit area, the information converted to the information field data area is set, and the board B is set together with other signals.
Output to This output is repeated until the ACK bit in the data signal is output as “1” from the substrate B.

In the serial / parallel converter 106B, the signal from the board A is input, and when the frame signal is active (“0” in FIG. 4) with reference to the in-board CLK signal, the FLAG bit is “1”. When it detects something,
The information in the information field data area is converted into parallel, written into the reception memory 105B by the control register / control circuit 102B, and an interrupt signal is output to the CPU 101B.

When an interrupt signal is output (step 204), the CPU 101B reads out the received information from the receiving memory 105B (step 205), and when the reading is completed (step 206), the CPU 101B executes the operation of the control register / control circuit 102B. “1” is written into the ACK register in the middle (step 207). Then, “1” is set in the ACK bit area of the data signal output to the board A, and the data signal is output to the board A together with other signals. This output is repeated until the FLAG bit in the data signal is output as “0” from the substrate A.

In the parallel / serial conversion unit 104A, A
When detecting that the CK bit is "1" (step 208), the FLAG register is returned to "0" (step 209). Then, “0” is set in the FLAG bit area in the data signal output to the substrate B, and the data signal is output together with other signals.

In the serial / parallel converter 106B, F
When detecting that the LAG bit is "0" (step 210), the ACK register is returned to "0" (step 211). Then, “0” is set in the ACK bit area in the data signal output to the substrate A,
Output together with other signals.

Thus, one transmission of information is completed. To transmit information from the board A to the board B again, F
After confirming that the LAG register is "0", transmission is started. Even if the FLAG register is "1", it is possible to store information in advance in the transmission memory 103A, and the FLAG register is set to "0" after writing of the information is completed.
Then, the transmission may be started.

FIG. 5 shows an example of the format of a data signal to be transmitted. One frame is 128 OCT (octets).
Is shown. As in this example, FC
By checking data with C (frame check code: operation result), it is possible to perform high-quality data transfer. In this case, the control may be such that the ACK bit is not output until the FCC receives normal data.

As described above, according to the first embodiment, in data communication between CPUs, information to be transmitted is once written in a memory, and when the information written in the memory reaches a certain specified amount, the specified amount is set. Since the amount of information can be transmitted with a single transmission instruction by the CPU, the number of times the CPU outputs the transmission instruction can be reduced, and the CPU is overloaded even if the amount of information to be transmitted increases. Without this, serial communication can be realized. Also,
By changing from parallel communication to serial communication, it is possible to reduce the number of pins of the connector that connects the board and the backboard, so that the remaining pins of the connector can be effectively used for other signals (main transmission information). it can.

(B) Second Embodiment Hereinafter, a data communication apparatus according to the present invention will be described with reference to C in an exchange.
A second embodiment applied to data communication between PUs will be briefly described with reference to the drawings.

As shown in FIG. 7, this second embodiment also comprises a substrate A and a substrate B, as in the first embodiment, and the substrates A and B have the same configuration. . Therefore, the configuration of the substrate A will be described below.

As shown in FIG. 7, the substrate A is
1A, a control register / control circuit 102A, a transmission memory 103A, a parallel-serial conversion unit 104A, a reception memory 105A, and a serial-parallel conversion unit 106A.
, The in-board CLK unit 107A, and the transmission general-purpose register 1
08A and a receiving general-purpose register 109A.

Here, reference numerals 101A to 107A denote the first.
The same reference numerals as in FIG. 1 denote the same parts as those in the first embodiment, and a description thereof will not be repeated.

The transmission general-purpose register 108A is
01A is a register that can be read / written by the user and can be set by a jumper terminal or the like on the board. The transmission general-purpose register 108A is a CPU 101A
And a control register / control circuit 102A and a parallel-serial conversion unit 104A.

The general register for reception 109A is
01 can be read, and L on the substrate
This is a register that can output to ED and the like. The receiving general-purpose register includes the CPU 101A and the control register / control circuit 10.
2A and the serial / parallel converter 106A.

Next, the operation of the second embodiment will be briefly described with reference to FIG.

In the second embodiment, the operation of transmitting and receiving information between the substrate A and the substrate B is the same as that of the first embodiment.

Therefore, hereinafter, the operation of the substrate A and the substrate B for transmitting and receiving the value set in the general-purpose register will be described.
The case where a value is transmitted from the board A to the board B will be described as an example.

In the transmission general-purpose register 108A, the CPU
The value is set by 108A or by a jumper terminal on the substrate in advance.

When a value is set in the transmission general-purpose register 108A, the transmission general-purpose register 108A and the parallel-serial conversion unit 10 are controlled by the control register / control circuit 102A.
4A, the control signal is output from the general-purpose register for transmission 108A to the parallel / serial conversion unit 104A.
The value set to A is output, converted to serial by the parallel-serial conversion unit 104A, and the converted value is transmitted to the board B via the backboard.

In the board B, the value transmitted from the board A is
The data is received by the serial / parallel conversion unit 106B and converted from serial to parallel.

In the control register / control circuit 102B, when the received value is converted into parallel, a control signal is output to the serial / parallel conversion unit 106B and the general-purpose receiving register 109B, and the converted value is received. Is set in the general purpose register 109B.

When a value is set in the receiving general-purpose register 109B, the value is output to an LED or the like on the board.

The operation of transmitting a value from the board B to the board A is performed in the same procedure.

As described above, the set values can be exchanged between the general-purpose registers of the board A and the board B.
Also, the method of transmitting the set values is, as in the first embodiment, asynchronous with the transmission of the other board, respectively.
It is transmitted according to the frame signal of its own board.

Therefore, a method of transmitting a value set according to the frame signal of the own board will be described in detail, taking the case where a value is transmitted from board A to board B as an example.

FIG. 8 shows an output signal pattern in the second embodiment, and FIG. 9 shows an example of the format of the data signal. The transmission method of the second embodiment differs from the first embodiment in the format of the data signal.

As shown in FIGS. 8 and 9, the data signal has a general-purpose register area between the ACK bit area and the information field data area. In this general-purpose register area, the value set in the transmission general-purpose register is set.

First, the transmission general-purpose register 108A is operated by the CPU 101A or a jumper terminal on the board in advance.
Is set in the control register / control circuit 102A.
Thus, the value set in the transmission general-purpose register 108A is output to the parallel-to-serial conversion unit 104A, converted to serial, and further, the converted value is stored in the general-purpose register area in the data signal output to the board B. It is set and output to the board B together with other signals. This output is
Regardless of whether or not the FLAG bit is set, the serial / parallel conversion unit 106B that repeatedly transmits until the setting is released from the next frame cycle in which the value is set in the general-purpose register for transmission is used for the signal from the board A. Is input, the value of the general-purpose register area is detected based on the in-board CLK signal and the frame signal, the value is converted into parallel, and written to the general-purpose receiving register 109B by the control register / control circuit 102B. Thus, one value transmission is completed.

As described above, according to the second embodiment, in data communication between CPUs, information to be transmitted is once written in a memory, and when the information written in the memory reaches a certain specified amount, the specified amount is set. Since the amount of information can be transmitted with a single transmission instruction by the CPU, the number of times the CPU outputs the transmission instruction can be reduced, and the CPU is overloaded even if the amount of information to be transmitted increases. Without this, serial communication can be realized. Also,
By changing from the parallel communication to the serial communication, the number of pins of the connector for connecting the board and the backboard can be reduced, so that the surplus pins of the connector can be effectively used for other signals.

Further, according to the second embodiment, the level output signal between the preset registers is also performed by serial communication, thereby further reducing the number of pins of the connector for connecting the board and the backboard. Therefore, the remaining pins of the connector can be effectively used for other signals, and the reliability is improved by performing the FCC check.

(C) Third Embodiment A data communication apparatus according to the present invention will now be described with reference to FIG.
A third embodiment applied to data communication between PUs will be briefly described with reference to the drawings.

As shown in FIG. 10, the third embodiment includes a substrate A and substrates B0 to Bn-1, and the substrates B0 to Bn-1 have the same configuration. In the third embodiment, a master-slave relationship is established, and n boards B0 to Bn-1 as slave boards are connected to a board A as a master board.

First, the configuration of the substrate A will be briefly described.

As shown in FIG. 10, the substrate A is
01A, a control register / control circuit 102A, transmission memories 103A0 to 103A (n-1), a parallel-serial conversion unit 104A, and reception memories 105A0 to 105A.
A (n-1), a serial / parallel conversion unit 106A,
In-board CLK section 107A and transmission general-purpose register 108
A0-108A (n-1) and the general-purpose register 10 for reception
9A0-109A (n-1), selector 110A,
And a distribution unit 111A.

Here, reference numerals 101A, 102A, 103
A0 to 103A (n-1), 104A, 105A0 to 1
05A (n-1), 106A, 107A, 108A0
108A (n-1), 109A0-109A (n-1)
Is the same as the component of the first or second embodiment,
The same reference numerals as those in FIG. 1 or FIG. Reference numerals 103A, 105A, 108A, 109
As for A, the number of the corresponding substrate B is appended to the reference number.

The selector 110A controls the transmission memory 103A under the control of the control register / control circuit 102A.
(X) and the general-purpose register for transmission 108A (x) and the parallel-serial conversion unit 104A are connected in the order of the numbers of the respective boards B. However, the above “x” is used as a case of indicating any one or a specific one of n. Also,
Use the same. The selector 110A is connected to the transmission memory 1
03A0 to 103A (n-1), the general-purpose registers for transmission 108A0 to 108A (n-1), and the parallel / serial conversion unit 104A.

The distribution unit 111A reads the number of the board B from the data signal output from the serial / parallel conversion unit 106A, and receives the board number from the reception memory 105.
The data signal is output to A (x) or the general-purpose register for reception 109 (x). The distribution unit 111A is connected to the reception memories 105A0 to 105A (n-1), the general-purpose reception registers 109A0 to 109A (n-1), and the serial / parallel conversion unit 106A.

Next, the structure of the substrates B0 to Bn-1 will be briefly described.

Since the substrates B0 to Bn-1 have the same configuration, only the configuration of the substrate B0 will be described.

As shown in FIG. 10, the board B0 is a CPU
101B0, a control register / control circuit 102B0,
The transmission memory 103B0 and the parallel / serial conversion unit 1
04B0, the reception memory 105B0, the serial / parallel conversion unit 106B0, and the transmission general-purpose register 108B0
And a general-purpose receiving register 109B0 and a three-state buffer 112B0.

Further, the control register / control circuit 102B
0 is the output timing control circuit 113B0, and the serial / parallel converter 106B0 is the substrate address DEC11.
4B0 is additionally provided.

Here, reference numerals 101B0 to 109B0 (1
13B0 and 114B0) are the same as the components of the first or second embodiment, and are denoted by the same reference numerals as those in FIG. 1 or FIG. In addition, in order to distinguish a component part for every number of each board B, the number of each corresponding board B is attached after the code.

Three-state buffer 112B0 receives the data signal output from parallel-serial conversion unit 104B0, and outputs the data signal to substrate A by a three-state output.

The output timing control circuit 113B0 generates a timing for outputting a data signal to the substrate A based on the frame signal output from the substrate A.

The board address DEC114B0 is
Decodes the number of the board from the data signal output from the board. If the address is addressed to the own board, the reception of the information is permitted. .

Further, the operation of the third embodiment will be described with reference to FIG. 10 by taking as an example the operation of transmitting and receiving information or values between the substrate A and the substrate B0.

First, an operation of transmitting information or a value from the board A to the board B0 will be described.

When transmitting information to the board B0, the CPU 101A writes the information to be transmitted to the transmission memory 103A0 corresponding to the number "0" of the board B, and outputs a transmission command to the control register / control circuit 102A. You.

In the control register / control circuit 102A, the transmission memories 103A0 to 103A (n-1) and the transmission general-purpose registers 108A0 to 108A (n-1) are repeatedly searched in the order of the numbers of the corresponding boards B. At the same time, by controlling the selector 110A, the transmission memory 103A (x), the transmission general-purpose register 108A (x), and the parallel-to-serial
04A is connected. Here, when the transmission command from the CPU 101A to the board B0 is output or when the transmission general-purpose register of the board B0 is set, the transmission memory 103
The control signal is output to A0 or the general-purpose register for transmission 108A0 and the parallel-to-serial conversion unit 104A, and information or a value is output from the transmission memory 103A0 or the general-purpose register for transmission 108A0 to the parallel-to-serial conversion unit 104A. Serial conversion is performed, and the converted information or value is transmitted to the board B.
In the control register / control circuit 102A, a frame signal for determining the head position of the data is output to the board B0.

In the board B0, the information or value transmitted from the board A is received by the serial / parallel conversion unit 106B, and the board number detected from the information or value by the board address DEC 114B0 is "0". If allowed, the information or value is converted from serial to parallel.

In the control register / control circuit 102B0,
When the received information or value is converted to parallel, a control signal is output to the reception memory 105B0 or the general-purpose reception register 109B0 and the serial / parallel conversion unit 106B0, whereby the converted information is stored in the reception memory 105B0.
In B, the converted value is written in parallel to the general-purpose register for reception. The control register / control circuit 102B
Then, when the information is received at the time when all the controls are completed, an interrupt to that effect is output to the CPU 101B0.

In the CPU 101B0, when an interrupt is output from the control register / control circuit 102B0, the received information is read from the reception memory 105B0.

Next, an operation of transmitting information or a value from the board B0 to the board A will be described.

In transmitting information to the board A, the CPU 101B0 stores the information to be transmitted in the transmission memory 103B0.
And a transmission instruction is output to the control register / control circuit 102B0.

In the control register / control circuit 102B0,
When a transmission command is received or the transmission general-purpose register 108B
When 0 is set, the transmission memory 103B0 or the general-purpose register for transmission 108B0 and the parallel / serial conversion unit 10
4B0, the control signal is output to the parallel-serial conversion unit 104B0 from the transmission memory 103B0 or the general-purpose register for transmission 108B0 to the parallel-serial conversion unit 104B0.
And the converted information or value is output to the three-state buffer 112B0. Here, based on the frame signal output from the substrate A for the substrate B0, the output timing control circuit 113B0 generates a timing with a certain delay for this output,
It is performed according to the timing.

In the three-state buffer 112B0,
The input information or value is transmitted to the board A via the backboard as a three-state output. Here, the data signal transmitted from the board B0 to the board A is wired OR-connected with all the data signals transmitted from the boards B1 to Bn-1 other than the board B0, and the data signal is transmitted to the board A. You.

In the board A, the information or value transmitted from the board B0 is received by the serial / parallel conversion section 106A, and the information or value is converted from serial to parallel.

In the control register / control circuit 102A, when the information or value is converted by the serial / parallel conversion unit 106A, the number of the board B is detected from the converted information or value, and the reception memory 105A ( x) or by controlling the general register for reception 109A (x) and the serial / parallel converter 106A, the information is output to the reception memory 105A (x), and the value is output to the general register for reception 109A (x). When the information or the value is written and the information is received, an interrupt indicating that the information is received is output to the CPU 101A. Here, when the information or the value is received from the board B0, the number “0” of the board B is detected from the converted information, and the reception memory 105A0 or the general-purpose register for reception 10 is used.
By controlling the 9A0 and the serial / parallel conversion unit 106A, the information is output to the reception memory 105A0, the value is output to the general-purpose register 109A0, and the information or the value is written. An interrupt to notify that it has been received
1A.

In the CPU 101A, when an interrupt is output from the control register / control circuit 102A, the received information is read from the reception memory 105A0.

The substrates B1 to Bn− other than the substrate A and the substrate B0
The operation of transmitting / receiving information or a value to / from 1 is performed in a similar procedure.

As described above, the substrate A and the substrates B0 to B
Information or values can be exchanged with n-1. The method of transmitting the information or the value is transmitted in accordance with the frame signal output from the substrate A.

Therefore, as to a method of transmitting information or a value in accordance with a frame signal output from the substrate A, a case where information is transmitted from the substrate A to the substrate B0 will be described as an example.
This will be described in detail.

FIG. 11 shows an output signal pattern in the third embodiment, and FIG. 12 shows an example of the format of the data signal. The third embodiment differs from the first or second embodiment in the output signal and the format of the data signal.

As shown in FIG. 11, the substrates A to B0
To Bn−1, the reference CLK signal, the frame signal, and the data signal are branched and output.
From the n-1 to the substrate A, only the data signal is wired O
The data is output after being R-connected.

As shown in FIG. 11 or FIG. 12, in the format of the data signal, there is a substrate address area before the FLAG bit area. In this board address area, the number of the board B to be transmitted / received is set. In this format, since the board address is 5 bits, a maximum of 32 boards B can be connected.

First, when all the information to be transmitted is written into the transmission memory 103A0 by the CPU 101A, the FL for the board B0 in the control register / control circuit 102A is written.
"1" is written to the AG register. Here, in the control register / control circuit 102A, each board B0-Bn-
There is one FLAG register. Then, the information written in the transmission memory 103A0 is output to the parallel-serial conversion unit 104A by the control register / control circuit 102A, and is converted into serial data. Here, as shown in FIG. 11, the data signals output from the board A to the boards B0 to Bn-1 are the data signal of the board B0, the data signal of the board B1,..., The data signal of the board Bn-1. , Substrate B
Data areas of 0,... Are divided into areas by the number of the substrate B, and are repeatedly output in the order of the numbers.

Therefore, when transmitting information to the board B0,
In the data signal area to be transmitted to the board B0, that is, “1” is set in the FLAG bit area of the data signal area in which the board address is “0”, and the information converted to the information field data area is set. Then, it is output to the board B0 together with other signals. This output is repeated from the board B0 until the ACK bit in the data signal area for the board B0 is output as "1".

In the serial / parallel conversion section 106B, a signal from the board A is input, and the board address DEC 114B
At 0, the input is permitted when the board address is detected to be "0", and when the FLAG bit is detected to be "1", the information in the information field data area is converted into parallel, Control register
The control circuit 102B0 writes the data to the reception memory 105B0 and outputs an interrupt signal to the CPU 101B0.

When the CPU 101B0 outputs an interrupt signal, the CPU 101B0 reads the received data from the reception memory 105B0.
When "1" is written in the ACK register in the control circuit 102B0, "1" is set in the ACK bit area of the data signal output to the substrate A, and only this data signal is stored in the three-state buffer 112B0. Outputs three-state. This output is
Is repeated until the FLAG bit in the data signal area for substrate B0 is output as "0".

Here, this three-state output is shown in FIG.
As shown in FIG. 1, a signal is output only when a data signal is output, and high impedance is output when no data signal is output. This output is output by the output timing control circuit 113B0 based on the frame signal output from the substrate A for the substrate B0.
Timing with a certain delay is generated and performed in accordance with the timing. Therefore, the other substrate B
Can be prevented from colliding with the data signal output from the CPU.

In the parallel / serial conversion unit 104A, A
When detecting that the CK bit is "1", the FLAG
The register is returned to "0". Then, “0” is set in the FLAG bit area in the data signal transmitted to the substrate B, and is output together with other signals.

In serial-parallel conversion section 106B0,
When detecting that the FLAG bit is “0”, the AC
The K register is returned to "0". Then, “0” is set in the ACK bit area in the data signal area to be transmitted to the board A, and only this data signal is transmitted.

Thus, one transmission of information from the board A to the board B0 is completed. When transmitting information from the substrate B0 to the substrate A, the information may be transmitted in accordance with the frame signal for the substrate B output from the substrate A. The same method is used to transmit and receive the value set in the general-purpose register.

As described above, according to the third embodiment, in data communication between CPUs, information to be transmitted is once written in a memory, and when the information written in the memory reaches a certain specified amount, the specified amount is set. Since the amount of information can be transmitted with a single transmission instruction by the CPU, the number of times the CPU outputs the transmission instruction can be reduced, and the CPU is overloaded even if the amount of information to be transmitted increases. Without this, serial communication can be realized. Also,
By changing from the parallel communication to the serial communication, the number of pins of the connector for connecting the board and the backboard can be reduced, so that the surplus pins of the connector can be effectively used for other signals.

Further, according to the third embodiment, the level output signal between the registers set in advance is also performed by serial communication, thereby further reducing the number of pins of the connector for connecting the board and the backboard. Therefore, the remaining pins of the connector can be effectively used for other signals, and the reliability is improved by performing the FCC check.

Further, according to the third embodiment, 1
In data communication between one CPU block board and a plurality of CPU block boards, serial communication can be realized using a common data signal line.

(D) Other Embodiments In the above embodiments, the case where the CPU writes the information to be transmitted to the memory has been described. However, the information transmitted by other units connected to the CPU bus may be written to the memory. .

In the third embodiment, a general-purpose register is provided for each number of the board B. However, a general-purpose register is used in common for the boards B0 to Bn-1 and a value is set in the general-purpose register to thereby set the board B0 to the board B0. The same value may be transmitted to Bn-1 in a broadcast format.

Further, in the third embodiment, a board B having a certain number is used as a board to be transmitted in a broadcast format, there is no transmission from the board to the board A, and the board A does not check the ACK bit of the board. With the control, information written in the memory can be transmitted in a broadcast format.

[0121]

As described above, according to the present invention, the CPU
In the data communication between, temporarily store the information to be transmitted,
When the stored information reaches a certain specified amount, 1
Since the information stored by the transmission command can be transmitted at one time, the number of times the CPU outputs the transmission command can be reduced.
Serial communication can be realized without excessively increasing the load. Also, by changing from parallel communication to serial communication, the number of connections can be reduced, which is advantageous in terms of mounting.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional data communication between CPUs.

FIG. 3 shows a conventional method of mounting data communication between CPUs in an exchange.

FIG. 4 is an output signal pattern of the first embodiment.

FIG. 5 is an example of a data signal format according to the first embodiment;

FIG. 6 is an operation flowchart of the first embodiment.

FIG. 7 is a configuration diagram of a second embodiment of the present invention.

FIG. 8 is an output signal pattern of the second embodiment.

FIG. 9 is an example of a data signal format according to the second embodiment;

FIG. 10 is a configuration diagram of a third embodiment of the present invention.

FIG. 11 is an output signal pattern of the third embodiment.

FIG. 12 is an example of a data signal format according to the third embodiment;

[Explanation of symbols]

101A, 101B: CPU, 102A, 102B: control register / control circuit, 103A, 103B: transmission memory, 104A, 104B: parallel-serial conversion unit, 1
05A, 105B ... Reception memory, 106A, 106B ...
Serial-to-parallel converters 107A, 107B... CLK in the board.

Claims (4)

[Claims] 1. A first C mounted on a first substrate
In a data communication device for transmitting and receiving transfer information between a PU and a second CPU mounted on a second substrate, the first and second substrates are respectively opposed to each other. Second or first CPU on a substrate
Each time the transfer information to be transmitted to the PC is output in parallel from the first or second CPU on the own board, the transfer information is sequentially stored, and the stored transfer information reaches a predetermined specified amount. In this case, the first or second CP on the own substrate
Transmission information storage control means for outputting a specified amount of transfer information in response to a single transmission command from U; each time the transmission information storage control means outputs a specified amount of transfer information, the transfer information is serialized Convert to data,
Parallel-to-serial conversion transmitting means for transmitting to the opposing second or first substrate; receiving the transfer information transmitted from the parallel-to-serial conversion transmitting means on the opposing second or first substrate; And a serial-parallel conversion receiving means for converting the data into parallel data and outputting the data. Each time the serial-parallel conversion receiving means outputs the transfer information, the transfer information is stored, and the storage amount reaches a predetermined amount. Then, in response to a single reception instruction from the first or second CPU on the own board, the received information storage for outputting the stored transfer information in parallel to the first or second CPU on the own board. A data communication device, comprising: a control unit. 2. The method according to claim 1, wherein the first substrate is a master substrate, the second substrate is a slave substrate, and a plurality of the second substrates are provided. 2. The data communication device according to claim 1, wherein the first board, which is a master board, includes a plurality of slave boards in advance as the transmission information storage control means and the reception information storage control means. 3. Selecting means for selecting transfer information from a plurality of the transmission information storage control means, each of which has an address assigned to each of the two substrates, and storing the received transfer information in the reception information corresponding to the reception timing time. And a distributing unit provided to a control unit. The parallel-serial conversion transmitting unit on the first substrate transmits the signal to the second substrate output from the selecting unit. The transmission destination address is multiplexed with the transmission destination address and transmitted to all the second boards, and the serial / parallel conversion receiving means on each of the second boards is configured to transfer the data from the first board. Identifying the address multiplexed with the information, receiving the transfer information only when the address is the address assigned to the own board, the parallel-serial conversion transmitting means on each of the second boards, After receiving the transfer information for the own board from the first board, a transmission timing time of the own board for a predetermined fixed time is detected, and the transfer information of the own board is transmitted to the first board within the transmission timing time. The data communication apparatus according to claim 1, wherein said serial-parallel conversion receiving means on the first board transmits and outputs the received transfer information to the distribution means in parallel. 3. The opposing substrate element control information generating means for generating opposing substrate element control information for an opposing component on the second or first substrate, wherein the first and second substrates each include: Transmission control information holding and outputting means for holding and periodically outputting the opposing substrate element control information generated by the element control information generating means; and automatically transmitting the opposing substrate element control information given from the opposing second or first substrate. Further comprising: reception control information storage / supply means for outputting to a corresponding component on the board; wherein the parallel / serial conversion transmission means is provided each time counter board element control information is output from the transmission control information holding / output means. The information is converted into serial data, and the converted information is multiplexed with the transfer information, if there is a specified amount of transfer information output from the transmission information storage control means. If there is no transfer information, only the opposing substrate element control information is transmitted to the opposing second or first substrate, and the serial / parallel conversion receiving means transmits the reception information from the opposing second or first substrate. Is demultiplexed into transfer information and counter substrate element control information, and the separated transfer information is supplied to the reception information storage control means, and the separated counter substrate element control information is output to the reception control information storage supply means. The data communication device according to claim 1, wherein 4. A method according to claim 1, wherein said first substrate is a master substrate, said second substrate is a slave substrate, and said plurality of second substrates are provided. 4. The data communication device according to claim 3, wherein said first substrate, which is a master substrate, transmits and receives said transmission information storage control means, said reception information storage control means, and said transmission information setting. As the control means and the reception information setting control means, each having an address assigned to each of the plurality of second boards which are slave boards in advance, and transfer information from the plurality of transmission information storage control means and / or Selecting means for selecting counter-substrate element control information from the plurality of transmission information setting control means; The reception information storage control means or the reception information setting control means corresponding to time; and the parallel-serial conversion transmission means on the first substrate, The transmission destination address is multiplexed with the transfer information and / or the counter substrate element control information to be transmitted to the second substrate, and transmitted to all of the second substrates, and the serial / parallel conversion on the second substrate is performed. The receiving means identifies an address multiplexed in the transfer information from the first board and / or the counter board element control information, and receives the received information only when the address is an address assigned to the own board. The parallel-to-serial conversion transmitting means on each of the second substrates receives transfer information for the own substrate and / or counter substrate element control information from the first substrate. The transmission timing of the own board for a predetermined fixed time is detected, and the transfer information and / or the opposing board element control information of the own board are transmitted to the first board within the transmission timing. The data communication device, wherein the serial / parallel conversion receiving means outputs the received transfer information and / or counter substrate element control information in parallel to the distribution means.