JP6160822B2 - I / O expansion device group and I / O expansion device - Google Patents

Description

  The present invention relates to an I / O expansion device that is connected to a CPU and expands an external interface of the CPU.

  The number of I / O (input / output) signals that can be directly controlled by the CPU is limited, and an I / O expansion device is used to increase the number of signals that can be input and output.

  For example, Patent Document 1 discloses an I / O expansion device that can set whether to use an input function or an output function for each bit of a register. Further, in Patent Document 2, a plurality of shift registers are cascade-connected to a serial signal output port of a CPU and serial / parallel conversion is performed, whereby a plurality of output signals are output using one serial signal output port. A technique for enabling output in parallel is disclosed.

  By the way, when the number of I / Os to be controlled increases, it becomes difficult to cope with one I / O expansion device. In this case, it may be possible to change to an I / O expansion device with more input / output pins, but the cost increases.

  As a technique for coping with such a problem, Patent Document 3 discloses a signal that can be output by connecting a plurality of slave mode I / O expansion devices under a master mode I / O expansion device connected to a CPU. A technique for increasing the number is disclosed.

Japanese Patent Laid-Open No. 7-319592 JP 2011-197981 A JP 2009-123141 A

  In order to comply with recent energy saving standards, there is a state (power saving state) in which the power of the apparatus is turned on but the power of the CPU is turned off. Therefore, while the CPU power is off, the I / O expansion device performs I / O control without the intervention of the CPU, detects a change in the input signal, turns on the CPU power, and transitions to the normal state. It is necessary to perform control such as

  For example, when a predetermined trigger signal is input from an external device to the I / O expansion device in a power saving state in which the power of the CPU is off, the I / O expansion device displays the current state and the input trigger signal. Whether the transition to the normal state is determined from the type of the I / O, when the transition to the normal state is determined, the I / O expansion device outputs a start signal to another external device, or the power control unit A control signal is output to the CPU to turn on the CPU.

  When a plurality of I / O expansion devices are used in order to cope with an increase in the number of input / output signals, each I / O expansion device performs I / O control of a different external device. Even if it is determined that the device transitions to the normal state in response to the trigger signal from the external device, the other I / O expansion devices continue to operate in the original state, and a plurality of I / O There is a problem that it is impossible to perform a consistent operation (synchronized operation) corresponding to the same state in the O expansion device.

  For example, when a predetermined trigger signal changes while the power of the CPU is off, a start signal is output from the I / O expansion device to a predetermined external device other than the CPU, and the external device is started. Assume that it is necessary to perform sequence control such as turning on the power of the CPU. Then, for example, the process of determining the state transition based on the change of the input signal and the process of turning on the power of the CPU are performed by one I / O expansion device, and the other I / O expansion device performs a predetermined process other than the CPU. Assume that the function is shared so that a start signal is output to an external device.

  In this configuration, even if one I / O expansion device determines that the state transition is made to the normal state based on the change of the trigger signal and the CPU is activated, the other I / O expansion device performs the above state transition. The external device is not started because it is not recognized. For this reason, a situation occurs in which the CPU that is activated with the power turned on erroneously reads the output value of the external device that is not activated.

  The present invention is intended to solve the above problems, and provides an I / O expansion device group and an I / O expansion device that can synchronize the states of a plurality of I / O expansion devices without intervention of a CPU. The purpose is to do.

  The gist of the present invention for achieving the object lies in the inventions of the following items.

[1] A first I which is connected to a CPU for controlling the operation of a predetermined device and has an input function for setting an input signal value input from a predetermined component of the device in an input register readable by the CPU. A second I / O expansion device connected to the CPU and having an output function for outputting an output signal corresponding to a value set in an output register by the CPU to a predetermined component of the apparatus; An I / O expansion device group including:
When the value of the input signal changes, the first I / O expansion device determines whether to change the state of the device based on the change. Outputting a status notification signal indicating a status to the second I / O expansion device;
The second I / O expansion device that has received the state notification signal changes the value of the output signal according to the state of the transition destination notified by the state notification signal ,
The second I / O expansion device has a noise filter circuit that removes noise included in the state notification signal received from the first I / O expansion device;
The first I / O expansion device notifies the internal state of the device by the state notification signal when a delay time equal to the delay time generated in the noise filter circuit has elapsed since the output of the state notification signal. A group of I / O expansion devices , wherein a transition is made to the transition destination state .

In the above invention, when the first I / O expansion device responsible for the input function detects a change in the input signal, the first I / O expansion device determines whether the change causes a state transition. The second I / O expansion device responsible for the output function is notified of the state after the transition. Thereby, the states of the first I / O expansion device and the second I / O expansion device can be matched to match (synchronize) these operations.
Further, since the status notification signal is propagated through the wiring on the substrate, noise is removed by the receiving I / O expansion device to prevent malfunction. When the delay time equal to the delay time generated in the noise filter circuit of the I / O expansion device receiving the status notification signal has passed, the I / O expansion device on the side outputting the status notification signal changes the internal state. Transition to the state indicated by the state notification signal. Thereby, the timing of state transition based on the state notification signal can be matched between both I / O expansion devices.

[2] The status notification signal notifies the power status of the device,
The number of signal lines used for transmitting the status notification signal between the first I / O expansion device and the second I / O expansion device is determined when the CPU stops operating. The I / O expansion device group according to [1], wherein the number is set to a minimum number according to the number of types of power saving states that the apparatus can take.

In the above-described invention and the invention described in [ 6 ] below, the number of signal lines used for the status notification signal is set to the minimum necessary number.

[3] the second I / O expansion device, the destination state is wherein when the CPU is in the normal state of operation to recover from the stop state, from the first I / O expansion devices When changing the value of the output signal according to the received state notification signal, the output for restoring the CPU to the normal state after changing the output signal for a predetermined component other than the CPU to the value in the normal state The value of a signal is changed. The I / O expansion device group according to [1] or [2].

In the above onset bright, when to recover the CPU from the stopped state to the normal state, since by recovering the other components other than the CPU to the normal state, the change sequence of the output signal so CPU is restored to the normal state Be controlled.

[ 4 ] The first I / O expansion device and the second I / O expansion device have the same configuration of the output register and the input register, and connect the output register and the output terminal according to their roles. The I / O expansion device group according to any one of [1] to [ 3 ], wherein a connection circuit that connects the input terminal and the input register is configured.

In the above invention and the invention described in [ 7 ] below, the register configuration of each I / O expansion device is the same, and the configuration of each I / O expansion device depends on the configuration of the connection circuit that connects the register and the input / output terminal. Role differences are realized.

[ 5 ] To the CPU together with other I / O expansion devices having an output function for outputting an output signal corresponding to a value set in the output register by the CPU controlling the operation of the predetermined device to a predetermined component of the device. An I / O expansion device to be connected,
An input function for setting the value of an input signal input from a predetermined part of the device in an input register readable by the CPU;
When the value of the input signal changes, it is determined whether or not to change the state of the device based on the change, and when it is determined that the state is to be changed, a state notification signal indicating the state of the transition destination is sent to the other I A delay time generated in a noise filter circuit included in the other I / O expansion device in order to remove noise included in the state notification signal after outputting the state notification signal. When an equal delay time has elapsed, the internal state of the device is changed to the state of the transition destination notified by the state notification signal,
In the other I / O expansion device that has received the state notification signal, the value of the output signal is changed according to the state notified by the state notification signal.

  The above invention corresponds to the first I / O expansion device in the I / O expansion device group described in [1].

[ 6 ] The status notification signal notifies the power status of the device,
The number of signal lines used for transmission of the status notification signal between the I / O expansion device and the other I / O expansion device is determined by the apparatus when the CPU stops operating. The I / O expansion device according to [ 5] , wherein the minimum number is set according to the number of types of power saving states to be obtained.

[7] The I / O expansion device and the other I / O expansion device have the same configuration of the output register and the input register, and according to their roles, a connection circuit for connecting the output register and the output terminal, and The I / O expansion device according to [5] or [6] , wherein a connection circuit for connecting the input terminal and the input register is configured.

  According to the I / O expansion device group and the I / O expansion device according to the present invention, the states of the plurality of I / O expansion devices are matched by matching the states of the plurality of I / O expansion devices without intervention of the CPU. be able to.

1 is a block diagram illustrating a configuration example of an image forming apparatus using an I / O expansion device group according to an embodiment of the present invention. FIG. 3 is a diagram illustrating signal lines and the like when a CPU performs write access to an I / O expansion device. It is a figure which shows a signal line etc. in case a CPU performs read access to an I / O expansion device. FIG. 3 is a block diagram showing a schematic internal configuration of a first I / O expansion device and a second I / O expansion device. It is a figure which shows the input / output signal of a 1st I / O expansion device and a 2nd I / O expansion device. It is a figure which shows the register structure of an I / O expansion device. It is a flowchart which shows the operation | movement at the time of returning from a power saving state to a normal state. It is a sequence diagram which shows the operation | movement at the time of returning from a power saving state to a normal state.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a schematic configuration of an image forming apparatus 10 as an apparatus to which an I / O expansion device according to an embodiment of the present invention is applied. The image forming apparatus 10 includes a copy function that optically reads a document and prints a duplicate image on a recording sheet, a scan function that stores image data of the read document as a file, and transmits the file to an external terminal via a network, A multi-function peripheral (MFP) equipped with a printer function that forms an image of print data received over a network from a PC or the like on a recording paper and prints it out, and a facsimile function that transmits and receives image data according to a facsimile procedure. is there.

  The image forming apparatus 10 includes a CPU (Central Processing Unit) 11 as a control unit that comprehensively controls the operation of the image forming apparatus 10. The CPU 11 has a first nonvolatile memory 12, a second nonvolatile memory 13, a RAM (Random Access Memory) 14, a hard disk device 15, an automatic document feeder (ADF) 16, an image reading unit 17, and an operation through a bus. A panel 18, an image processing unit 19, a printer unit 21, a network communication unit 22, a facsimile communication unit 23, a first I / O expansion device 30, a second I / O expansion device 50, and the like are connected. Further, the image forming apparatus 10 includes a power control unit 24 that can individually turn on / off power supply to each unit. In FIG. 1, the CPU bus is described as one, but actually, it is configured by a plurality of buses via bridges.

  The CPU 11 is based on an OS (Operating System) program, and executes middleware, application programs, and the like.

  The first nonvolatile memory 12 and the second nonvolatile memory 13 are memories (flash memories) whose stored contents are not destroyed even when the power is turned off. The first nonvolatile memory 12 stores boot data, and the second nonvolatile memory 13 stores various types of firmware (programs) other than the boot data.

  The CPU 11 rises according to the boot data stored in the first nonvolatile memory 12, and thereafter executes various processes according to the firmware stored in the second nonvolatile memory 13. In addition, various application programs are stored in the hard disk device 15, and the CPU 11 loads the program into the RAM 14 and executes it. Various functions as the image forming apparatus 10 are realized by the CPU 11 executing various programs.

  The RAM 14 is used as a work memory that temporarily stores various data when the CPU 11 executes processing, an image memory that stores image data, and the like.

  The hard disk device 15 is a large-capacity nonvolatile storage device, and stores various data such as print data and image files and application programs.

  The image reading unit 17 performs a function of optically reading a document and acquiring image data. The image reading unit 17 sequentially, for example, a light source that irradiates light on the document, a line image sensor that receives the reflected light for one line in the width direction, and a line-by-line reading position in the length direction of the document. An optical path composed of a moving unit for moving, a lens, a mirror, and the like for guiding reflected light from the document to the line image sensor to form an image, and a conversion unit for converting an analog image signal output from the line image sensor into digital image data And so on.

  The automatic document feeder 16 feeds a document set on the platen one by one from the top one by one in order, passes the reading position of the image reading unit 17 and discharges it to a predetermined discharge position. Fulfill. The image reading unit 17 has a function of reading a document placed on the platen glass and a function of sequentially reading a document conveyed by the automatic document conveyance unit 16.

  The operation panel 18 has a function of displaying various operation screens, setting screens, and the like and a function of accepting various operations such as job submission from the user. The operation panel 18 includes a display unit such as a liquid crystal display (LCD), various hard keys such as a start button and a numeric keypad, and a touch panel provided on the display surface of the display unit.

  The image processing unit 19 performs rasterization processing for converting print data into image data, image data compression and expansion processing, in addition to processing such as image enlargement / reduction and rotation.

  The printer unit 21 has a function of forming an image corresponding to image data on a recording sheet. Here, the printer unit 21 includes a recording paper transport device, a photosensitive drum, a charging device, a laser unit, a developing device, a transfer separation device, a cleaning device, and a fixing device. It is configured as a so-called laser printer that forms an image by a process. Other methods may be used for image formation.

  The network communication unit 22 has a function of communicating with an external device (for example, a PC or a server). The network communication unit 22 may be configured to be capable of both wired communication and wireless communication, or may be configured to be capable of only one of them.

  The facsimile communication unit 23 performs a function of transmitting / receiving image data to / from an external apparatus having a facsimile function through a telephone line.

  The first I / O expansion device 30 and the second I / O expansion device 50 function to expand I / O that can be connected to the CPU 11. Here, the first I / O expansion device 30 has an input function of inputting an input signal from each unit (for example, a sensor) of the image forming apparatus 10 and setting the value in a register readable by the CPU. . The second I / O expansion device 50 has an output function of outputting an output signal corresponding to a value set in the register by the CPU 11 to each unit (for example, the power supply control unit 24) of the image forming apparatus 10. Details of the first I / O expansion device 30 and the second I / O expansion device 50 will be described later.

  The power control unit 24 controls power supply to each unit of the image forming apparatus 10. Here, a power source for the CPU 11, a power source for an application specific integrated circuit (ASIC) such as the image processing unit 19, a power source for the operation panel 18, a power source for the network communication unit 22, a power source for the facsimile communication unit 23, not shown. Control the power supply to the timer IC. The second I / O expansion device 50 outputs a control signal for instructing on / off of each power supply to the power supply control unit 24.

  2 and 3 show devices connected to channels for external interfaces of the CPU 11. FIG. 2 shows the time of writing, and FIG. 3 shows the time of reading.

  The CPU 11 is a SoC (System-on-a-Chip) type semiconductor chip having an external interface function. The CPU 11 includes ch1, ch2, and ch3 as external interface channels. A first nonvolatile memory 12 is connected to ch1, and a second nonvolatile memory 13 is connected to ch2.

  The first I / O expansion device 30 and the second I / O expansion device 50 are connected to ch3. A plurality of I / O expansion devices 30 and 50 are connected to one channel. However, since data is not output from a plurality of I / O expansion devices by read access, data collides. There is no problem. Here, the first I / O expansion device 30 is dedicated to the input function, and the second I / O expansion device 50 is dedicated to the output function. Therefore, the CPU 11 only needs to read the register of the first I / O expansion device 30, and the read signal is connected only to the first I / O expansion device 30.

  Specifically, the ch1 select signal, write signal, read signal, 8-bit data bus signal, and 3-bit address signal are connected to the first I / O expansion device 30 for connection to the device bus of the CPU 11. The The second I / O expansion device 50 is connected to a ch3 select signal, a write signal, an 8-bit data bus signal, and a 3-bit address signal. Since the second I / O expansion device 50 is dedicated to the output function, the read signal is not connected and there is no terminal for that purpose.

  When the address signal is 3 bits, the I / O expansion devices 30 and 50 can have a maximum of 8 registers corresponding to each address. In the ch3 write access, the same value is written to the register at the same address in the first I / O expansion device 30 and the second I / O expansion device 50, as shown in FIG. In the ch3 read access, the read signal is input only to the first I / O expansion device 30 and the read signal is not input to the second I / O expansion device 50, as shown in FIG. At each address, only the first I / O expansion device 30 outputs data to the CPU bus.

  The read signal is input to both the first I / O expansion device 30 and the second I / O expansion device 50, and the first I / O expansion device 30 side and the second I / O expansion device 50 are input. Which side outputs data to the CPU bus may be exclusively assigned by address. For example, when the 3-bit address at the time of read access is (000) or (001), the first I / O expansion device 30 outputs data, and the 3-bit address at the time of read access is (010), (011) In this case, the second I / O expansion device 50 may be configured to output data.

  In this embodiment, an 8-bit data bus signal is used, but the present invention is not limited to 8 bits. Although the address signal is 3 bits, it is not limited to 3 bits.

  FIG. 4 shows a schematic internal configuration of the first I / O expansion device 30 and the second I / O expansion device 50. The first I / O expansion device 30 is connected to the bus of the CPU 11 to input / output data, a bus interface unit 31, an input control register 32, an output control register 33, a return condition determination unit 34, A delay circuit 35 and a sequence control unit 36 are provided.

  The second I / O expansion device 50 includes a bus interface unit 51, an input control register 52, an output control register 53, a return condition determination unit 54, a noise filter circuit 55, and a sequence control unit 56. Yes.

  The input control registers 32 and 52 are registers that can be read by the CPU 11. An input signal from the outside is assigned to each bit, and the value of the input signal is reflected in each bit. The output control registers 33 and 53 are registers in which the CPU 11 can set the value of each bit, and an output signal corresponding to the set value is output to the outside.

  When the input signal value changes, the return condition determination units 34 and 54 determine the state from the changed input signal value and the current state (here, the state relating to power saving of the image forming apparatus 10). It determines whether or not a transition is necessary, and outputs a state notification signal indicating a transition destination state when it is determined that a state transition is to occur.

  The sequence controllers 36 and 56 control the output sequence (output order, delay time, etc.) when outputting the values set in the output control registers 33 and 53 as output signals.

  The noise filter circuit 55 is a circuit that removes noise from the state notification signal input from the first I / O expansion device 30. Since the status notification signal is propagated from the first I / O expansion device 30 to the second I / O expansion device 50 via the pattern on the board, the receiving side second I / O expansion device 50 is received. Receives a state notification signal via an internal noise filter circuit 55 for noise removal.

  The noise filter circuit 55 may be any known circuit, but here it has a multi-stage shift register configuration and operates to pass a status notification signal to the next-stage circuit when all bits are “1”. For this reason, in the second I / O expansion device 50, the timing at which the state of the transition destination notified by the state notification signal is reflected inside is delayed by the number of stages of the shift register constituting the noise filter circuit 55.

  The delay circuit 35 of the first I / O expansion device 30 outputs the state notification signal output from the return condition determination unit 34 for a time equal to the delay time of the noise filter circuit 55 included in the second I / O expansion device 50. This is a delay circuit. The status notification signal output from the return condition determination unit 34 is delayed by the delay circuit 35 and input to each unit (such as the output control register 33 and the sequence control unit 36) of the first I / O expansion device 30. As a result, the first I / O expansion device 30 and the second I / O expansion device 50 have the same timing for transition to the transition destination state indicated by the state notification signal.

  In addition, the first I / O expansion device 30 and the second I / O expansion device 50 include a control unit (not shown) that controls internal operations. The control unit functions to rewrite the set values of the output control registers 33 and 53 to values corresponding to the transition destination state indicated by the state notification signal.

  Here, the 1st I / O expansion device 30 and the 2nd I / O expansion device 50 are comprised by CPLD (Complex Programmable Logic Device). The first I / O expansion device 30 and the second I / O expansion device 50 are basically composed of a common circuit (a circuit described in RTL (Register Transfer Level)). Specifically, the bus interface unit 31, the input control register 32, the output control register 33, the return condition determination unit 34, and the sequence control unit 36 of the first I / O expansion device 30 are each a second I / O expansion device. 50 bus interface unit 51, input control register 52, output control register 53, return condition determination unit 54, and sequence control unit 56 are configured in the same circuit.

  However, depending on the function of each of the first I / O expansion device 30 and the second I / O expansion device 50, the connection between the circuits, the registers 32, 33, 52, 53 and the terminals of the chip The connection circuit is different. For example, in the second I / O expansion device 50 responsible for the output function, the read signal is internally fixed at an inactive logic level. As a result, the second I / O expansion device 50 does not respond to the read access. Since the second I / O expansion device 50 does not require an input function, the input value to the input control register 52 is fixed to an inactive logic level. On the other hand, in the first I / O expansion device 30 having the input function, the output of the output control register 33 is not connected to the terminal of the chip.

  The input control register 32 of the first I / O expansion device 30 that performs the input function is read by the CPU 11. In a general device bus, the host CPU performs read access to the input control register of the I / O expansion device at regular intervals, so that each input signal (from the sensor) is input to the I / O expansion device. Signal).

  This method is called polling. In the case of the polling method, since the CPU needs to perform read access at a constant cycle, the load on the CPU increases.

  There is an interrupt method as a method different from the polling method. In the interrupt method, the I / O expansion device detects a change in each input signal and outputs an interrupt signal to the CPU. When an interrupt signal is input, the CPU performs read access to the input control register of the I / O expansion device.

  Thus, since the CPU load is reduced in the interrupt method, the interrupt method is employed in the first I / O expansion device 30 according to the present embodiment. The first I / O expansion device 30 performs notification of interrupts related to a plurality of input signals with one interrupt signal. Such an interrupt is called a collective interrupt. The first I / O expansion device 30 includes an interrupt factor register for indicating which input signal has changed, and an interrupt factor clear register for clearing the interrupt factor register.

  When the CPU 11 receives the collective interrupt, it reads the interrupt factor register of the first I / O expansion device 30 and recognizes which input signal has changed. When the CPU 11 writes “1” to the corresponding bit of the interrupt factor clear register, the corresponding bit of the interrupt factor register is cleared to “0”.

  Next, terminal assignment of the first I / O expansion device 30 and the second I / O expansion device 50 will be described.

  The first I / O expansion device 30 and the second I / O expansion device 50 are CPDLs of the same package. Both the first I / O expansion device 30 and the second I / O expansion device 50 require inputs such as a power supply, a GND, and a clock, and the number of terminals that can be arbitrarily assigned by the user is 27 in any case. Suppose that

  FIG. 5 shows signals assigned to the 27 terminals in the first I / O expansion device 30 and the second I / O expansion device 50.

  In the first I / O expansion device 30, a total of 15 signals are selected for the ch3 select signal, write signal, read signal, 8-bit data bus signal, 3-bit address signal, and collective interrupt signal. / O Used as a status notification signal to the expansion device 50. The remaining 10 are used as input terminals for input signals related to the input function.

  In the second I / O expansion device 50, a total of 13 signals are selected from the ch3 select signal, the write signal, the 8-bit data bus signal, and the 3-bit address signal, and two of them are sent from the first I / O expansion device 30. Used for receiving status notification signals. The remaining 12 lines are used as output terminals for output signals related to the output function.

  The two status notification signals indicate power saving states that can be taken when the CPU 11 stops operating in the image forming apparatus 10. Specifically, a sleep notification signal indicating a sleep state and an ErP notification signal indicating an ErP state. The number of signal lines used for the state notification signal is set to the minimum number corresponding to the number of power saving states that can be taken when the CPU 11 stops the operation. Here, since the sleep state and the ErP state are power saving states, and it is necessary to notify the three states including the normal state, two signal lines are used.

  The sleep state is a state in which the CPU 11 and the ASIC are turned off, and only the sensor and the like are turned on. The ErP state is a state that consumes less power than the sleep state, and is a state in which only the power of only some of the sensors that have been turned on in the sleep state is turned on. For example, in both states, the CPU 11, the ASIC for image processing, and the control unit of the mechanical part (the image reading unit 17 and the printer unit 21) of the image forming apparatus 10 are turned off, but the operation panel 18 is in the sleep state. The facsimile communication unit 23, the front cover sensor, the scanner cover sensor, the document detection sensor, the wireless LAN device, and the timer IC are all turned on. In the ErP state, only the operation panel 18 and the timer are turned on.

  In normal times, the two status notification signals are both “0”. When the image forming apparatus 10 enters the sleep state, the sleep notification signal is “1” and the ErP notification signal is “0”. When the ErP state is entered, the sleep notification signal is “0” and the ErP notification signal is “1”. The normal state is a state in which power is supplied to the CPU 11 and other units, and the image forming apparatus 10 can execute a job.

  FIG. 6 shows a list of registers included in the first I / O expansion device 30 and the second I / O expansion device 50. The register configuration of the first I / O expansion device 30 and the second I / O expansion device 50 is the same, and each includes eight registers. In the list of FIG. 6, addresses, register names, and possible access types are associated with each other.

  Each of the first I / O expansion device 30 and the second I / O expansion device 50 includes a first output control register and a second output control register as the output control register 33, and the first control register 32 as the input control register 32. A 1-input control register and a second input control register are provided. Corresponding to the first input control register and the second input control register, a first interrupt factor register, a second interrupt factor register, a first interrupt factor clear register, and a second interrupt factor clear register are provided.

  The first output control register is an 8-bit readable / writable register assigned to the address (000). Each bit corresponds to the output signal of output 0 to output 7 of the second I / O expansion device 50, and the CPU 11 can control the corresponding output signal by rewriting each bit.

  The second output control register is an 8-bit readable / writable register assigned to the address (001). Each bit corresponds to the output signal from the output 8 to the output 11 of the second I / O expansion device 50, and the CPU 11 can control the corresponding output signal by rewriting each bit. The second output control register is 8 bits, but only the lower 4 bits are actually used due to the limitation of the number of output terminals.

  The objects controlled by the first output control register and the second output control register are the power source of the CPU 11, the power source of the ASIC such as the image processing unit 19, the power source of the operation panel 18, the power source of the network communication unit 22, and the power source of the facsimile communication unit 23. These are the power supply and reset signal of the timer IC (not shown).

  The first input control register is an 8-bit read-only register assigned to the address (010). Each bit corresponds to input 0 to input 7 of the first I / O expansion device 30, and the CPU 11 reads each bit and inputs to input 0 to input 7 of the first I / O expansion device 30. It is possible to know the value of the input signal.

  The second input control register is an 8-bit read-only register assigned to the address (011). The lower 2 bits correspond to the input 8 and the input 9 of the first I / O expansion device 30, and the CPU 11 reads the respective bits to input the input 8 and the input 9 of the first I / O expansion device 30. It is possible to know the value of the input signal input to the. Although the second output control register is 8 bits, only the lower 2 bits are actually used due to the limitation of the number of input terminals.

  The signals fetched into the first input control register and the second input control register are an operation panel switch signal, FAX incoming call signal, cover sensor signal, document sensor signal, wireless LAN reception signal, timer signal, and the like.

  The first interrupt factor register is an 8-bit read-only register assigned to the address (100). The corresponding bit is set to “1” when the state of any of the input signals 0 to 7 of the first I / O expansion device 30 reflected in the first input control register changes. . The first I / O expansion device 30 outputs a collective interrupt signal to the CPU 11 when any one of the first interrupt factor register and the second interrupt factor register described later is “1”. When the first I / O expansion device 30 receives a read request for the address (100) from the CPU 11, it returns the value of the first interrupt factor register.

  The second interrupt factor register is a register capable of only 8-bit reading assigned to the address (101). When the state of the input signal of either the input 8 or the input 9 of the first I / O expansion device 30 reflected in the second input control register is changed, the corresponding bit is set to “1”. The first I / O expansion device 30 outputs a collective interrupt signal to the CPU 11 when one of the bits of the first interrupt factor register and the second interrupt factor register described above is “1”. When the first I / O expansion device 30 receives a read request for the address (101) from the CPU 11, it returns the value of the second interrupt factor register.

  The first interrupt factor clear register is a register capable of only 8-bit writing assigned to the address (110). The first interrupt factor clear register corresponds to the first interrupt factor register, and when “1” is written to each bit of the first interrupt factor clear register, the corresponding bit of the first interrupt factor register is “0”. Cleared to "".

  The second interrupt factor clear register is a register capable of only 8-bit writing assigned to the address (111). The second interrupt factor clear register corresponds to the second interrupt factor register, and when “1” is written to each bit of the second interrupt factor clear register, the corresponding bit of the second interrupt factor register is “0”. Cleared to "".

  Next, operations of the first I / O expansion device 30 and the second I / O expansion device 50 will be described.

  First, the case where the image forming apparatus 10 shifts from the normal state to the sleep state or the ErP state will be described. In the normal state, the CPU 11 can write-access the first I / O expansion device 30 and the second I / O expansion device 50. Therefore, the CPU 11 sets the output control registers 33 and 53 in accordance with the power state of the sleep state / ErP state. Rewrite each bit. When the power control bit of the CPU 11 is set to “0”, the power of the CPU 11 is turned off. Therefore, the CPU 11 finally sets this bit to “0” to complete the state transition. The first I / O expansion device 30 and the second I / O expansion device 50 recognize the state of the device based on the values set by the CPU 11 in the output control registers 33 and 53.

  Next, the operation in the sleep state / ErP state and the operation in returning to the normal state will be described.

  FIG. 7 is a flowchart showing an operation when a state transition is made from the sleep state / ErP state to the normal state, and FIG. 8 shows an operation sequence at that time.

  When the value of any input signal input to the first I / O expansion device 30 changes in the sleep state or ErP state in which the CPU stops operating (FIG. 7; step S101, FIG. 8: P001) ), The return condition determination unit 34 of the first I / O expansion device 30 determines whether or not to change the image forming apparatus 10 to the normal state by the change of the input signal (FIG. 7; Steps S102 and FIG. 8). : P002).

  The return condition determination unit 34 checks whether or not the combination of the current state and the changed input signal corresponds to a preset combination, and determines that the state transitions to the normal state if applicable.

  For example, among the interrupt signals used in the image forming apparatus 10, the operation panel switch signal, FAX incoming call signal, front cover sensor, scanner cover sensor, document detection sensor, wireless LAN reception signal, timer interrupt signal, etc. are the first. The I / O expansion device 30 is input as an input signal. The value of each input signal is reflected in the input control register 32 of the first I / O expansion device 30.

  The return condition determination unit 34 has a determination table indicating which input signal is valid as a cause of the state transition in which state. The return condition determination unit 34 recognizes an input signal that is enabled in the current state from the determination table, and when the value of the input signal that is enabled changes to a predetermined value, state transition to the normal state is necessary. Is determined. The CPU 11 may set the determination table in the first I / O expansion device 30 before the power is turned off, or the first I / O expansion device 30 may hold the fixed value in advance.

  When the sensor power is turned off, the signal from the sensor becomes “0” (Low), and when it is a low active signal, it becomes active. Therefore, the return condition determination unit 34 refers to the determination table and selects an effective one. The determination table is different between the sleep state and the ErP state. For example, in the sleep state, the operation panel switch signal, FAX incoming call signal, front cover sensor, scanner cover sensor, document detection sensor, wireless LAN reception signal, and timer interrupt signal are enabled. In the ErP state, the operation panel 18, timer Only interrupt signals are enabled.

  When the determination result indicates that there is a state transition (FIG. 7; Step S102; Yes), the return condition determination unit 34 sets the bit corresponding to the input signal that caused the determination result in the interrupt factor register. Set to 1 ”(active value). As a result, a collective interrupt signal is output from the first I / O expansion device 30 to the CPU 11 (FIG. 7; step S103, FIG. 8; P003).

  At the same time, the return condition determination unit 34 of the first I / O expansion device 30 outputs a state notification signal indicating a state transition to the normal state (FIG. 7; step S104, FIG. 8; P004). The second I / O expansion device 50 receives the state notification signal arriving from the first I / O expansion device 30 by removing noise by the noise filter circuit 55 (FIG. 8; P101). The first I / O expansion device 30 causes the state notification signal output from the return condition determination unit 34 to be delayed by the delay circuit 35, and then reaches each internal location (the output control register 33 and the sequence control unit 36). (FIG. 8; P005).

  Thereby, the first I / O expansion device 30 and the second I / O expansion device 50 start the operation corresponding to the state after the transition (here, the normal state) at the same timing. Specifically, in each of the first I / O expansion device 30 and the second I / O expansion device 50, the values of the output control registers 33 and 53 are autonomously rewritten to values in the normal state (FIG. 7). Step S105, FIG. 8; P006, P102).

  Since the first I / O expansion device 30 has no output function, only the value of the output control register 33 is rewritten. On the other hand, when the value of the output control register 53 is rewritten to the value in the normal state, the second I / O expansion device 50 changes the value of the output signal accordingly. At this time, the sequence control unit 56 of the second I / O expansion device 50 controls the timing and order of changing the output signal (FIG. 7; step S106).

  Specifically, first, the value of the corresponding output signal is changed so as to turn on the power of devices other than the CPU 11 (FIG. 8; P103), and then after a predetermined time has elapsed and those devices have started up. Then, the value of the output signal for power control of the CPU 11 is changed so that the CPU 11 is turned on (FIG. 8; P104). Note that the CPU 11 may be controlled so that the power source of the CPU 11 is also started at the same time as another device, and the reset signal of the CPU 11 is canceled after the startup of the other device is completed. That is, the CPU 11 only needs to operate after the peripheral device has started up in the normal state.

  The CPU 11 that has started the operation detects the collective interrupt signal (FIG. 7; step S107, FIG. 8; P201). Then, the CPU 11 reads the interrupt factor register of the first I / O expansion device 30 (FIG. 7; step S108, FIG. 8; P202, P007).

  The CPU 11 determines whether any bit of the interrupt factor register is “1” (active) (FIG. 7; step S109). If any bit is “1” (step S109; Yes), the CPU 11 The interrupt factor is identified from the bit that is “1”.

  Next, the CPU 11 reads the value of the input control register 32 of the first I / O expansion device 30 (FIG. 7; step S110, FIG. 8; P203, P008). Then, after executing the processing corresponding to the read value of the input control register 32, “1” is written to the corresponding interrupt factor clear register and the interrupt factor register is cleared to “0” (FIG. 7; step S111, FIG. 8; P204, P205, P009).

  As described above, since the peripheral devices other than the CPU 11 have risen before the CPU 11, when the CPU 11 reads the value of the input control register 32, the peripheral device has risen and correctly inputs the values of the sensors and the like possessed by the peripheral device. can do. For example, if the CPU 11 reads the value of the input control register 32 before the sensor starts up, the input value becomes an incorrect value. However, such erroneous input is avoided by starting up with the sequence described above.

  In the register configuration shown in FIG. 6, since there are two interrupt factor registers, the first interrupt factor register and the second interrupt factor register, the processing of steps S109 to S111 in FIG. 7 (P202 to P205 in FIG. 8) is performed for each interrupt factor register. , P007 to P009).

  A specific example is shown. Assume that the state of the input signal at the input 4 of the first I / O expansion device 30 has changed in step S101 of FIG. 7 shown in FIG. Here, the input signal of input 4 is a detection signal from a sensor that detects opening and closing of the front cover of the image forming apparatus 10.

  When the state of the input signal of the input 4 changes, the bit 4 of the interrupt factor register 1 becomes “1”, and a collective interrupt is output to the CPU 11 (step S103). In addition, the state notification signal to the second I / O expansion device 50 is changed to a value indicating the normal state (sleep notification signal “0”, ErP notification signal “0”).

  The second I / O expansion device 50 receives the fact that the state notification signal indicates the normal state, rewrites the value of the output control register 53 to the value in the normal state, and controls the timing by the sequence control unit 56. An output signal corresponding to the value of the output control register 53 is output to turn on the power of each device. The sequence for rewriting values is performed so as to satisfy the order and waiting time defined for each device. Which device is turned on (the value of the output control register 33 corresponding to the normal state) may be stored in advance in the second I / O expansion device 50 as an initial value, or the CPU 11 A register value representing the power state of each device immediately before the power is turned off may be held.

  When the power source is turned on, the CPU 11, when detecting the collective interrupt, reads the first interrupt factor register and the second interrupt factor register to identify which input signal has changed. Here, the input signal of the input 4 is specified. After the specification, the first input control register corresponding to the input 4 is read to check whether the input signal of the input 4 is currently in the “0” or “1” state. After confirmation, the corresponding processing is performed, and finally the interrupt factor is cleared by writing “1” to bit 4 of the first interrupt factor clear register. In this example, since the front cover opening / closing sensor is an interrupt factor, the CPU 11 displays on the operation panel 18 “front cover is open”.

  As described above, since the change in state that occurs while the CPU 11 is stopped is notified from one I / O expansion device 30 to another I / O expansion device 50 by the state notification signal, each I / O expansion device 30, 50 is notified. The states managed in (1) can be matched without the intervention of the CPU 11, and the operations of the plurality of I / O expansion devices 30, 50 can be matched without the intervention of the CPU 11.

  In addition, since the number of signal lines used as the status notification signal is set to the minimum necessary number, a decrease in the number of terminals that can be used for actual I / O expansion can be minimized.

  When the CPU 11 is returned to the normal state, the peripheral device other than the CPU is returned to the normal state and then the CPU 11 is operated. Therefore, the CPU 11 immediately after starting up erroneously inputs the value of the non-energized sensor. The situation is avoided.

  Further, since the second I / O expansion device 50 removes the noise of the status notification signal through the noise filter circuit 55, it does not malfunction due to noise on the substrate. Further, the first I / O expansion device 30 sends the status notification signal to each part in the device through the delay circuit 35 having the same delay time as the delay time generated in the noise filter circuit 55 of the second I / O expansion device 50. Therefore, the first I / O expansion device 30 and the second I / O expansion device 50 can coincide with each other at the timing of starting the execution of the operation corresponding to the state after the transition.

  Further, the register configuration of the first I / O expansion device 30 and the second I / O expansion device 50 is made common, and the functions of the first I / O expansion device 30 and the second I / O expansion device 50 are used. Accordingly, since the connection circuit for connecting the register and the input / output terminal is made different, the design man-hours of the first I / O expansion device 30 and the second I / O expansion device 50 are reduced.

  Further, only the first I / O expansion device 30 to which the input function is assigned returns a response to the read access from the CPU 11, so that only one device apparently is connected from the CPU 11. This is equivalent to a state, and consistency of bus access can be maintained.

  The embodiment of the present invention has been described with reference to the drawings. However, the specific configuration is not limited to that shown in the embodiment, and there are changes and additions within the scope of the present invention. Are also included in the present invention.

  In the embodiment, the example in which the I / O expansion device group includes the first I / O expansion device 30 and the second I / O expansion device 50 has been described. However, three or more I / O expansion devices are included. It may be composed of

  Further, a plurality of I / O expansion devices may be configured to have an input function, or a plurality of I / O expansion devices may be configured to have an output function. Furthermore, one I / O expansion device in the I / O expansion device group may have both an input function and an output function. When the input function is distributed to a plurality of I / O expansion devices, it is sufficient to exclusively allocate which device outputs data to the CPU bus for each address.

  Furthermore, although the example which connects a some I / O expansion device to one channel of CPU11 was shown, this invention is applied also to the structure which uses a some channel for the connection of a some I / O expansion device. . That is, even when a plurality of channels are used, it is effective to match the states without intervention of the CPU by the state notification signal when using a plurality of I / O expansion devices.

  In the embodiment, the example in which the I / O expansion device is created by CPDL is shown, but the present invention is not limited to this. Further, the apparatus in which the I / O expansion device is used is not limited to the image forming apparatus 10. Further, the state is not limited to the power state of the apparatus.

  In the embodiment, the case where the state transition is performed from the sleep state and the ErP state to the normal state is illustrated, but the transition destination of the state transition determined by the return condition determination unit 34 is not limited to the normal state.

DESCRIPTION OF SYMBOLS 10 ... Image forming apparatus 11 ... CPU
DESCRIPTION OF SYMBOLS 12 ... 1st non-volatile memory 13 ... 2nd non-volatile memory 14 ... RAM
DESCRIPTION OF SYMBOLS 15 ... Hard disk apparatus 16 ... Automatic document conveyance part 17 ... Image reading part 18 ... Operation panel 19 ... Image processing part 21 ... Printer part 22 ... Network communication part 23 ... Facsimile communication part 24 ... Power supply control part 30 ... 1st I / O expansion device 31 ... bus interface unit 32 ... input control register 33 ... output control register 34 ... return condition determination unit 35 ... delay circuit 36 ... sequence control unit 50 ... second I / O expansion device 51 ... bus interface unit 52 ... Input control register 53 ... Output control register 54 ... Return condition determination unit 55 ... Noise filter circuit 56 ... Sequence control unit

Claims (7)

A first I / O extension connected to a CPU for controlling the operation of a predetermined device and having an input function for setting an input signal value input from a predetermined component of the device in an input register readable by the CPU An I / O expansion device including a device and a second I / O expansion device connected to the CPU and having an output function for outputting an output signal corresponding to a value set in an output register by the CPU to a predetermined component of the device; / O expansion device group,
When the value of the input signal changes, the first I / O expansion device determines whether to change the state of the device based on the change. Outputting a status notification signal indicating a status to the second I / O expansion device;
The second I / O expansion device that has received the state notification signal changes the value of the output signal according to the state of the transition destination notified by the state notification signal ,
The second I / O expansion device has a noise filter circuit that removes noise included in the state notification signal received from the first I / O expansion device;
The first I / O expansion device notifies the internal state of the device by the state notification signal when a delay time equal to the delay time generated in the noise filter circuit has elapsed since the output of the state notification signal. A group of I / O expansion devices , wherein a transition is made to the transition destination state . The status notification signal notifies the power status of the device,
The number of signal lines used for transmitting the status notification signal between the first I / O expansion device and the second I / O expansion device is determined when the CPU stops operating. The I / O expansion device group according to claim 1, wherein the number of I / O expansion devices is set to a minimum number corresponding to the number of types of power saving states that can be taken by the apparatus. The second I / O expansion device receives the first I / O expansion device received from the first I / O expansion device when the state of the transition destination is a normal state in which the CPU recovers from the stopped state and operates. When changing the value of the output signal in accordance with the state notification signal, the value of the output signal for restoring the CPU to the normal state after changing the output signal for a predetermined component other than the CPU to the value in the normal state The I / O expansion device group according to claim 1, wherein the I / O expansion device group is changed. The first I / O expansion device and the second I / O expansion device have the same configuration of the output register and the input register, and a connection circuit that connects the output register and the output terminal according to their roles The I / O expansion device group according to any one of claims 1 to 3 , wherein a connection circuit that connects the input terminal and the input register is configured. Connected to the CPU together with another I / O expansion device having an output function for outputting an output signal corresponding to a value set in an output register by a CPU that controls the operation of the predetermined device to a predetermined component of the device An I / O expansion device,
An input function for setting the value of an input signal input from a predetermined part of the device in an input register readable by the CPU;
When the value of the input signal changes, it is determined whether or not to change the state of the device based on the change, and when it is determined that the state is to be changed, a state notification signal indicating the state of the transition destination is sent to the other I A delay time generated in a noise filter circuit included in the other I / O expansion device in order to remove noise included in the state notification signal after outputting the state notification signal. When an equal delay time has elapsed, the internal state of the device is changed to the state of the transition destination notified by the state notification signal,
In the other I / O expansion device that has received the state notification signal, the value of the output signal is changed according to the state notified by the state notification signal. The status notification signal notifies the power status of the device,
The number of signal lines used for transmission of the status notification signal between the I / O expansion device and the other I / O expansion device is determined by the apparatus when the CPU stops operating. The I / O expansion device according to claim 5, wherein the I / O expansion device is set to a minimum number corresponding to the number of types of power saving states to be obtained. The I / O expansion device and the other I / O expansion device have the same configuration of the output register and the input register, and according to their roles, a connection circuit and an input terminal for connecting the output register and the output terminal, The I / O expansion device according to claim 5 or 6 , wherein a connection circuit for connecting the input register is configured.