JP2003188793A - System lsi and mobile communication terminal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable power saving setting to respective devices without interposing a CPU. <P>SOLUTION: Within a system LSI 10 packaged with a CPU 11, an automatic write control part 13 is provided as hardware for setting power saving to respective peripheral devices (internal circuit 12, analog front end part 4, channel CODEC part 8, audio CODEC part 9 and functional block 15) connected to the address bus and the data bus of the CPU 11. The automatic write control part 13 writes data for power control to the respective peripheral devices after the CPU is changed to a power saving operation mode when changing the CPU 11 from an ordinary operation mode to the power saving operation mode and before the CPU is changed to the ordinary operation mode when changing the CPU 11 from the power saving operation mode to the ordinary operation mode. Thus, power saving can be set to the respective devices without interposing the CPU 11 and the power saving operation term of the CPU 11 can be prolonged. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system LSI and a mobile communication terminal used for mobile communication terminals such as mobile phone terminals.

[0002]

2. Description of the Related Art Conventionally, a system LSI used in a mobile communication terminal is equipped with a CPU that controls the main control of the terminal, and power saving settings for each peripheral device inside and outside this system LSI are performed by the CPU. Is going.

That is, taking standby control of a mobile telephone terminal as an example, the CPU switches the operation mode of each peripheral device from the normal operation mode to the power saving operation mode in order to suppress unnecessary power consumption before and after receiving the paging channel. ing. In this case, the CPU is in the normal operation mode until the switching control for these peripheral devices is completed, and after the switching control is completed, the CPU itself enters the power saving operation mode.

[0004]

As described above, in the conventional configuration in which the CPU sets the power saving for each internal / external peripheral device, the CPU itself saves until the operation mode of each peripheral device is switched. There is a problem that the power operation mode cannot be entered and the power consumption during that time cannot be suppressed.

Further, in recent mobile communication terminals, the number of devices that require switching of operation modes is increasing, and along with this, the setting processing of the CPU is also increasing. Furthermore, mutual timing constraints are imposed in the operation mode setting between a plurality of devices. May be required, and the processing of the CPU relating to the power saving setting becomes complicated. For this reason, setting mistakes are likely to occur, which has also been a factor that deteriorates development efficiency.

The present invention has been made in view of the above points, and an object of the present invention is to provide a system LSI and a mobile communication terminal capable of setting power saving for each device without going through a CPU.

[0007]

System LSI of the present invention
Has a normal operation mode and a power saving operation mode
A system LSI equipped with U, which detects an operation mode of the CPU and which is connected to an address bus and a data bus of the CPU when the CPU is in a power saving operation mode, and internal and external peripheral devices. Write control means for writing data to the CPU, the write control means is configured such that when the CPU shifts from the normal operation mode to the power saving operation mode, the CPU shifts to the power saving operation mode, When the power saving operation mode is changed to the normal operation mode, the power control data is written to the peripheral devices in a predetermined order before the normal operation mode is changed.

According to the system LSI having such a configuration, the power saving setting for each peripheral device connected to the address bus and the data bus of the CPU is performed by the hardware other than the CPU while the CPU is in the power saving operation mode. Can be realized by the write control means provided as.

Further, by using the above system LSI in a mobile communication terminal such as a mobile phone terminal, the CPU can be used, for example, when shifting from a normal operation mode to a power saving operation mode during standby or a power saving operation mode. It is possible to realize power saving settings for each device without going through.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a mobile phone terminal equipped with a system LSI according to an embodiment of the present invention.

This mobile phone terminal 1 has a radio section 3 for performing radio communication with a base station 2, an analog front end section 4 for performing analog / digital conversion processing of data, and a transmission for inputting voice. A microphone 5 as a speaker, a speaker 6 as a receiver for outputting a voice, a modulator / demodulator 7 for modulating / demodulating digital wireless data, a channel / codec unit 8 for channel encoding / decoding, a voice encoding / decoding of digital voice data. It is provided with various devices such as an audio codec unit 9 for performing decoding, and a functional block 15 as a representative of the device for realizing the basic / extended functions of this terminal. Each of the above peripheral devices except the wireless unit 3 has a CP having a power saving operation mode and a normal operation mode.
It is connected to the bus 11a of U11. The bus 11a includes an address bus and a data bus.

Here, in this embodiment, a system LSI 10 is incorporated in the mobile phone terminal 1, and the system LSI 10 has a CPU 1 which controls the main control of the terminal.
1, an internal circuit 12 such as a ROM and a RAM, and an automatic writing control unit 13 and a timer control unit 1 which are features of the present invention.
4 are provided. The automatic write control unit 13 refers to a table 13a described later to control data write to each peripheral device bus-connected to the CPU 11. The timer control unit 14 controls the timing of data writing by the automatic writing control unit 13.

The portable telephone terminal 1 further includes a clock generator 16a for generating a high speed clock CK1 used in the normal operation mode and a clock generator 16b for generating a low speed clock CK2 used in the power saving operation mode. Equipped with. The system LSI 10 includes the high-speed clock CK1 of the clock generator 16a or the clock generator 1
It operates by receiving the low-speed clock CK2 of 6b.

Although not shown in particular, the portable telephone terminal 1 operates by using a battery as a drive source, and converts the voltage of the battery into a level required for the operation of each device and supplies it. A power supply circuit and the like are also provided.

Next, the power saving setting will be described by taking the control during standby in a general portable telephone terminal as an example.

In the standby mode, the paging channel signal sent from the base station 2 at a predetermined cycle is received, and it is checked whether or not the paging channel signal is contained in the paging channel signal. Is called a paging process), except for the reception of the paging channel, the normal operation mode is switched to the power saving operation mode in order to suppress unnecessary power consumption.

Here, as in the conventional system, the system LS
In the configuration in which the CPU 11 in I10 controls the setting of the power saving operation mode for each internal / external peripheral device, as shown in FIG. 4, after the peripheral devices are set to the power saving mode, the CPU 11 itself performs the power saving operation. It will shift to the mode. In the example of FIG. 4, power saving is set in the order of the modem unit 7, the channel codec unit 8, the voice codec unit 9, the function block 15, the analog front end unit 4, and the internal circuit 12, and finally the CPU 11 itself saves power. The state which changes to a power mode is shown. Further, when returning to the normal operation mode, the order is reversed, and the CPU 11 first starts up and then the peripheral devices are started up in order. In this way, the CPU 11 is last when power is saved, and the CPU 11 is first when returning,
There is a problem that the power saving operation period of the CPU 11 becomes short. Further, if the processing related to the power saving setting becomes complicated with the increase in the number of peripheral devices, there is a problem that the CPU 11 is burdened and the CPU function is required to be expanded, which lowers the development efficiency.

Therefore, in the present invention, the power saving setting for each peripheral device as described above is realized by hardware other than the CPU. The hardware is the automatic write control unit 13 and the timer control unit 14 shown in FIG. 1, which are mounted on the system LSI 10.

The operation of the mobile phone terminal according to this embodiment will be described below with reference to FIGS. 2 and 3.

FIG. 2 is a diagram showing an example of automatic write setting values. FIG. 2 (a) is a setting value used when shifting to the power saving operation mode, and FIG. 2 (b) is a setting value used when returning to the normal operation mode. Is shown. Further, FIG. 3 is a diagram showing an example of the power saving setting timing during the standby control.

The CPU 11 in the system LSI 10 performs two operations, for example, a transition from the normal operation mode to the power saving operation mode and a return from the power saving operation mode to the normal operation mode as initial setting processing immediately after power-on. The setting value for the mode is set in advance in the table 13a provided in the automatic writing control unit 13. This setting value includes
It includes "address", "setting data" and "setting timing". The “address” corresponds to each peripheral device bus-connected to the CPU 11 and indicates a data write destination. “Setting data” indicates power control data (power off / power on data) for shifting each peripheral device to the power saving operation mode or returning to the normal operation mode. The “setting timing” is information indicating the timing of writing data corresponding to each peripheral device, and when the power saving operation mode is changed or the normal operation mode is returned, the power for each peripheral device is set at a time interval according to this timing. The control data is written.

A set value including such an address / data / setting timing is treated as one set of three consecutive data, and these are set in the table 13a of the automatic write control unit 13 and are set. "0xFFF
By setting specific data (setting completion flag) such as “F”, it is possible to recognize that the setting value is the final setting value.

In the example of FIG. 2, address 0 of the peripheral device
5 to 5 correspond to the modem unit 7, the channel codec unit 8, the voice codec unit 9, the function block unit 15, the analog front end unit 4, and the system LSI internal circuit 12. These exist as one module, each of which has a register (not shown), and is switched to the power saving operation mode or the normal operation mode according to the content of the data for power control set in this register.

Further, the setting data A0 to 5 indicate data to be written in each peripheral device when shifting to the power saving operation mode, and the setting data B0 to 5 indicate data to be written in each peripheral device when returning to the normal operation mode. The setting timings A0 to 5 are data writing timings to each peripheral device when shifting to the power saving operation mode, and the setting timings B0 to 5 are data writing timings to each peripheral device when returning to the normal operation mode. For example,
The modulation / demodulation unit 7 is defined as an address 0, and the setting data A0 is written in the modulation / demodulation unit 7 at the setting timing A0 when the power saving operation mode is entered.

The order in which the peripheral devices are shifted to the power saving operation mode is in descending order of power consumption, and
It is a functionally consistent order. High power consumption order
Since the peripheral devices have different power consumption values, it is efficient to drop the power consumption in descending order. In addition, the functionally consistent order means that some peripheral devices are functionally linked, and if the device enters the power saving operation mode first, other devices may not be able to enter the power saving operation mode. Therefore, it is necessary to drop them in an order that does not interfere with other devices. The order of returning each peripheral device to the normal operation mode is basically the reverse order of the transition to the power saving operation mode.
It is assumed that the one with high power consumption will later become functionally consistent.

Next, the case where the normal operation mode is changed to the power saving operation mode in the actual standby control will be described.

In the standby mode, the mobile phone terminal 1 receives the paging channel sent from the base station 2 at a predetermined cycle to check whether or not it has its own telephone number. If it has its own phone number, it will respond as if there was a call.

Here, in the period when the paging channel is not sent, in order to prevent unnecessary power consumption, first, C
The PU 11 enters the power saving operation mode. When the automatic write control unit 13 detects this, the clock generation unit 16
Power saving is set for each peripheral device bus-connected to the CPU 11 in synchronization with a timing signal given from the timer control unit 14 based on the low-speed clock signal of b. That is, when the CPU 11 is in the power saving operation mode, the automatic write control unit 13 refers to the address / setting data / setting timing preset in the table 13a and refers to the power saving operation mode for each peripheral device. The data (power-off data) for shifting to (1) is written in a predetermined order at time intervals according to the timing information. By writing this data, each peripheral device is switched from the normal operation mode to the power saving operation mode.

As described above, when power is saved, first, the CPU
11 enters the power saving operation mode first, and then, under the control of the automatic write control unit 13, each peripheral device shifts to the power saving operation mode in a predetermined order. That is, as shown in the example of FIG.
Codec unit 8, audio codec unit 9, functional block 1
5, the analog front end unit 4, the internal circuit 12 and so on are sequentially shifted to the power saving operation mode.

On the other hand, when receiving the paging channel,
The CPU 11 shifts from the power saving operation mode to the normal operation mode. At that time, before the CPU 11 shifts to the normal operation mode, the timer control unit 14 and the automatic write control unit 13 operate, and the automatic write control unit 13 connects to the CPU 11 by a bus in synchronization with a timing signal given from the timer control unit 14. The recovery setting for each peripheral device is performed. That is, when the CPU 11 is in the power saving operation mode, the automatic write control unit 13 refers to the address / setting data / setting timing preset in the table 13a and sets the peripheral device to the normal operation mode. Data for restoring (power-on data) is sequentially written in a predetermined order at time intervals according to the timing information. By writing this data, each peripheral device is switched from the power saving operation mode to the normal operation mode.

Finally, a timer interrupt signal or the like is input to the CPU 11 to restore the normal operation mode.
Thereby, as in the example of FIG. 3, the internal circuit 12, the analog front end unit 4, the functional block 15, the voice codec unit 9, the channel codec unit 8, and the modem unit 7 are provided.
In this order, the normal operation mode is restored, and finally the CPU1
1 returns to the normal operation mode.

As described above, the power saving setting for each peripheral device connected to the address bus and the data bus of the CPU 11 is realized by hardware other than the CPU while the CPU 11 is in the power saving operation mode.
The processing load of U11 can be reduced and the power saving operation period of CPU11 can be extended. Further, since the power saving setting can be centrally managed as a set value of hardware, it is not necessary to expand the function of the CPU 11 as the number of peripheral devices increases, and the development efficiency can be improved.

There are several methods for operating the automatic write control section 13 for controlling data write without going through the CPU 11 as follows.

The first method is a method of operating the automatic write controller 13 by using the low-speed clock CK2 of the clock generator 16b used in the power saving operation mode. Usually, this type of terminal is provided with two types of clock signals for high speed and low speed, and these are used by appropriately switching according to the operation mode. By giving the low-speed clock CK2 among them to the automatic write control unit 13 to operate it, there is an advantage that the power consumption can be suppressed as much as possible. In this case, the timer control unit 14 is unnecessary. That is, the automatic write control unit 13 writes data to each peripheral device at predetermined time intervals according to the low speed clock CK2. Further, when the timing information corresponding to each peripheral device is set in the table 13a, the time interval at the time of writing data is changed by the timing information.

The second method is a method of operating the automatic write control unit 13 using the timer control unit 14 using the low speed clock CK2 as a reference clock. In this case, the data writing by the automatic writing control unit 13 is performed by the timer control unit 1
It is performed in synchronization with the timing signal given from the No. 4.
Further, when timing information corresponding to each peripheral device is set in the table 13a, the time interval at the time of writing data is changed by the timing information.

The third method is a method of operating the automatic write controller 13 by using the high speed clock CK1 of the clock generator 16a used in the normal operation mode. This is limited to terminals that do not have a low-speed clock signal, and is operationally similar to the first method.

The fourth method is a method of operating the automatic write control section 13 by using the timer control section 14 which uses the high speed clock CK1 as a reference clock, and the low speed clock signal is supplied in the same manner as the third method. The operation is the same as that of the third method described above since the operation is limited to the terminal not provided.

In the above embodiment, the configuration using the second method is shown. However, the present invention is not limited to this, and the automatic write control unit 13 can be implemented by using another method. Even when operated, the effect intended by the present invention can be obtained.

Although the above embodiment has been described by taking the portable telephone terminal as an example, the present invention is not limited to this, and for example, P
It is also applicable to other mobile communication terminals such as DA (Personal Digital Assistants).

[0041]

As described above, according to the present invention, C
The power saving setting for each peripheral device connected to the bus to the PU is realized by the hardware other than the CPU while the CPU is in the power saving operation mode, reducing the processing load of the CPU and the power saving operation of the CPU. The period can be extended and the power saving setting can be centrally managed as the setting value of the hardware, and there is an effect that the function expansion of the CPU is unnecessary and the development efficiency is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a mobile phone terminal equipped with a system LSI according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of automatic write setting values.
(A) is a set value used when shifting to the power saving operation mode,
FIG. 11B is a diagram showing set values used when returning to the normal operation mode.

FIG. 3 is a diagram showing an example of power saving setting timing during standby control when the present invention is used.

FIG. 4 is a diagram showing an example of a power saving setting timing during standby control according to a conventional method.

[Explanation of symbols]

1 ... Terminal device 2 ... Base station 3 ... Wireless section 4 ... Analog front end section 5 ... Mike 6 ... speaker 7. Modulator / demodulator 8 ... Channel codec section 9 ... Voice codec section 10 ... System LSI 11 ... CPU 12 ... System LSI internal circuit 13 ... Automatic writing control unit 14 ... Timer control unit 15 ... Functional block 16a ... Clock generator for high speed 16b ... Clock generator for low speed

Claims (6)

[Claims] 1. A system LSI equipped with a CPU having a normal operation mode and a power saving operation mode, wherein the CPU detects an operation mode of the CPU, and when the CPU is in the power saving operation mode, an address of the CPU. A write control means is provided for controlling data write to each of internal and external peripheral devices connected to the bus and the data bus, and the write control means causes the CPU to shift from a normal operation mode to a power saving operation mode. In this case, after the power saving operation mode is entered, when the CPU goes from the power saving operation mode to the normal operation mode, the data for power control is sent to each of the peripheral devices before going to the normal operation mode. A system LSI configured to write data in a predetermined order. 2. A table means holding an address corresponding to each of the peripheral devices and data for power control is provided, and the write control means refers to the table means when the CPU is in a power saving operation mode. The system LSI according to claim 1, wherein the power control data is written in a predetermined order in each of the peripheral devices. 3. A table means for holding an address corresponding to each of the peripheral devices and data for power control and holding timing information at the time of writing data is provided, and in the write control means, the CPU is in a power saving operation mode. 2. The system LSI according to claim 1, wherein the power control data is written to each of the peripheral devices in a predetermined order at time intervals in accordance with the timing information by referring to the table means during the time. . 4. A communication terminal device which operates using a system LSI equipped with a CPU having a normal operation mode and a power saving operation mode, wherein the system LSI detects the operation mode of the CPU, and the CPU The above C when in the power saving operation mode
A write control means for controlling data write to each device connected to the address bus and data bus of the PU is provided, and when the CPU shifts from the normal operation mode to the power saving operation mode, the power saving operation mode is set. After the shift, when the CPU shifts from the power saving operation mode to the normal operation mode, the write control means sends power control data to each device in a predetermined order before shifting to the normal operation mode. A mobile communication terminal characterized by writing. 5. The system LSI is provided with a table means holding an address corresponding to each of the peripheral devices and data for power control, and the write control means is provided when the CPU is in a power saving operation mode. 5. The mobile communication terminal according to claim 4, wherein the data for power control is written into each of the peripheral devices in a predetermined order by referring to the table means. 6. The system LSI is provided with table means for holding an address corresponding to each of the peripheral devices and data for power control and also holding timing information at the time of writing data, and the write control means includes: By referring to the table means when the CPU is in the power saving operation mode, the data for power control is written in each peripheral device in a predetermined order at time intervals according to the timing information. The mobile communication terminal according to claim 4.