JPH10178385A - Portable terminal - Google Patents
Portable terminalInfo
- Publication number
- JPH10178385A JPH10178385A JP8354097A JP35409796A JPH10178385A JP H10178385 A JPH10178385 A JP H10178385A JP 8354097 A JP8354097 A JP 8354097A JP 35409796 A JP35409796 A JP 35409796A JP H10178385 A JPH10178385 A JP H10178385A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- frequency
- oscillator
- data transmission
- clock oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は携帯電話機等が具備
する調歩同期式デ−タ伝送部の消費電流の低減を図った
携帯端末に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a portable terminal for reducing the current consumption of a start-stop synchronous data transmission unit provided in a portable telephone or the like.
【０００２】[0002]
【従来の技術】図４は従来の携帯端末の構成例を示す図
である。同図に示す携帯端末はアンテナ４、ＲＦ／ＩＦ
部（高周波／中間周波部）５、デジタル処理部６、操作
部７、音声処理部８、送受話器９等を具備する通話機能
部にＵＡＲＴ（調歩同期式デ−タ送受信部）１、それを
駆動する高周波クロック発振器２、外部インタフェ−ス
３等のデ−タ伝送機能を設けたものである。2. Description of the Related Art FIG. 4 is a diagram showing a configuration example of a conventional portable terminal. The mobile terminal shown in FIG.
Unit (high frequency / intermediate frequency unit) 5, a digital processing unit 6, an operation unit 7, a voice processing unit 8, a communication function unit including a handset 9, a UART (start-stop synchronous data transmission / reception unit) 1, It has a data transmission function such as a high-frequency clock oscillator 2 to be driven and an external interface 3.
【０００３】デジタル処理部６は高速のＣＰＵ（中央演
算処理装置）６−２、メモリ６−３、時計用クロック発
振器６−１を具備し、音声信号の符号化／復号化、プロ
トコル処理、クロック制御、制御信号等のデジタルデ−
タの処理及び端末全体の制御を行うようになっている。The digital processing unit 6 includes a high-speed CPU (Central Processing Unit) 6-2, a memory 6-3, and a clock oscillator 6-1 for encoding / decoding audio signals, protocol processing, and clock processing. Digital data such as control and control signals
Data processing and control of the entire terminal.
【０００４】ＰＨＳ方式携帯電話機やＰＤＣ（パーソナ
ル・デジタルセルラ）方式携帯電話機等の携帯端末では
通常ＴＤＭＡ（時分割多重接続）方式が採られ、制御チ
ャネルを使用して基地局と交信し、自分の所在を登録し
基地局からの呼出しに応答するようになっている。しか
し、常時、連続的に受信しているのではなく、例えば、
ＰＤＣ方式携帯電話機では基地局から間欠的に受信を行
い、その間欠受信状態では最大３６サブフレ−ム（１サ
ブフレ−ム＝２０ｍｓ）に１回６．６ｍｓの受信期間の
割合で受信を行い基地局と連絡している。[0004] Portable terminals such as PHS portable telephones and PDC (personal digital cellular) portable telephones usually employ a TDMA (Time Division Multiple Access) system, communicate with a base station using a control channel, and transmit their own data. It registers the location and responds to calls from the base station. However, it is not always receiving continuously, for example,
The PDC mobile phone receives intermittently from the base station, and in the intermittent reception state, performs reception once every 36 subframes (1 subframe = 20 ms) for a reception period of 6.6 ms. Has been contacted.
【０００５】携帯端末はバッテリを駆動電源とするもの
が多く、そのため極力消費電流が小さいことが望まれ
る。携帯端末における低消費電流化の一つとして、携帯
端末が待機状態で間欠受信状態にあるときはＣＰＵ６−
２をスリ−プモ−ドにして動作クロックの供給を停止、
又は動作クロックの周波数を下げる方法が採られてき
た。[0005] Many portable terminals use a battery as a driving power source, and therefore it is desired that the current consumption be as small as possible. As one of the reductions in the current consumption of the portable terminal, when the portable terminal is in the standby state and in the intermittent reception state, the CPU 6-
2 to sleep mode, stop supply of operation clock,
Alternatively, a method of reducing the frequency of the operation clock has been adopted.
【０００６】また、伝送方式が調歩同期式の場合、伝送
速度（ボ−レ−ト）は６００、１２００、２４００、４
８００、９６００、１９２００、３８４００ｂｐｓの内
から回線や使用機器の性能により適切な伝送速度が選ば
れるが、サンプリングクロック及びボ−レ−トクロック
の精度を±１％以内に収める必要があり、ＵＡＲＴ１は
１２．６ＭＨｚの高周波の高周波クロック発振器２の出
力信号で作動するようになっている。また、外部インタ
フェ−ス３は外部機器と接続するためのインタフェ−ス
である。When the transmission system is the start-stop synchronization system, the transmission speed (baud rate) is 600, 1200, 2400, 4
An appropriate transmission speed is selected from among 800, 9600, 19200, and 38400 bps depending on the performance of the line and the equipment used. However, the accuracy of the sampling clock and the ballet clock must be kept within ± 1%. It operates with an output signal of a high frequency clock oscillator 2 having a high frequency of 12.6 MHz. The external interface 3 is an interface for connecting to an external device.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、上述し
たように間欠受信中はＣＰＵ６−２をスリ−プモ−ドに
して動作クロックの供給を停止、又は動作クロックの周
波数を下げＣＰＵ６−２の消費電流を低減しているが、
ＵＡＲＴ１は伝送速度（ボ−レ−ト）の大小にかかわら
ず１２．６ＭＨｚの高周波クロック発振器２を使用する
のでデ−タ伝送時は消費電流が増大する（消費電流は使
用周波数に比例するから）と云う問題があった。However, as described above, during intermittent reception, the CPU 6-2 is put into the sleep mode to stop the supply of the operation clock or to reduce the frequency of the operation clock to reduce the current consumption of the CPU 6-2. Is reduced,
The UART 1 uses the 12.6 MHz high frequency clock oscillator 2 irrespective of the transmission speed (bolt), so the current consumption increases during data transmission (because the current consumption is proportional to the operating frequency). There was a problem.
【０００８】本発明は上述の点に鑑みてなされたもの
で、デ−タ伝送速度に応じてクロック信号発振器を低周
波クロック発振器または高周波クロック発振器に切り替
えることにより消費電流を低減した携帯端末を提供する
ことを目的とする。The present invention has been made in view of the above points, and provides a portable terminal in which current consumption is reduced by switching a clock signal oscillator to a low frequency clock oscillator or a high frequency clock oscillator in accordance with a data transmission speed. The purpose is to do.
【０００９】[0009]
【課題を解決するための手段】上記課題を解決するため
本発明は計時用の低周波クロック発振器及び伝送用の高
周波クロック発振器を具備し、規定された種々の伝送速
度に対応可能な調歩同期式のデータ伝送を行なうデ−タ
伝送手段を具備する携帯端末において、デ−タ伝送速度
に応じて低周波クロック発振器又は高周波クロック発振
器の出力信号を切り替えて使用する切替手段及び両クロ
ック発振器の出力周波数を分周する分周手段を設け、所
定のデ−タ伝送速度で伝送する際、高周波クロック発振
器を停止し、低周波クロック発振器の出力信号を分周手
段で適切に分周し所定の精度のサンプリングクロック及
びボ−レ−トクロックを発生させデ−タ伝送を行う手段
を設けたことを特徴とする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention comprises a low-frequency clock oscillator for clocking and a high-frequency clock oscillator for transmission, and a start-stop synchronous system capable of coping with various prescribed transmission speeds. A portable terminal equipped with data transmission means for performing the above data transmission, a switching means for switching and using an output signal of a low frequency clock oscillator or a high frequency clock oscillator according to a data transmission speed, and an output frequency of both clock oscillators When transmitting at a predetermined data transmission rate, the high-frequency clock oscillator is stopped, and the output signal of the low-frequency clock oscillator is appropriately divided by the frequency dividing means to achieve predetermined accuracy. A means for generating a sampling clock and a ballet clock for data transmission is provided.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態例を図
面に基づいて詳細に説明する。図１は本発明の携帯端末
の構成例を示す図である。ＵＡＲＴ１はＩ／Ｏコントロ
−ラ１−１、ボ−レ−トジェネレ−タ１−２、通信ブロ
ック１−３を具備し、高周波クロック発振器２又は時計
用クロック発振器（低周波クロック発振器）６−１の出
力で駆動する。その他の部分は図４と同じであり前述し
たのでここでの説明は省略する。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a mobile terminal of the present invention. The UART 1 includes an I / O controller 1-1, a ball generator 1-2, and a communication block 1-3, and includes a high-frequency clock oscillator 2 or a clock oscillator (low-frequency clock oscillator) 6-1. Drive with the output of The other parts are the same as those in FIG.
【００１１】Ｉ／Ｏコントロ−ラ１−１には、何れのク
ロック発振器の出力信号を使用するかを指定するクロッ
ク設定レジスタ１−１−１及びボ−レ−ト（伝送速度ｂ
ｐｓ）を設定するボ−レ−ト設定レジスタ１−１−２が
設けられている。The I / O controller 1-1 has a clock setting register 1-1-1 for designating which clock oscillator output signal is to be used, and a baud rate (transmission speed b).
There is provided a boat setting register 1-1-2 for setting ps).
【００１２】ボ−レ−トジェネレ−タ１−２は切替器１
−２−１、デコ−ダ１−２−２、カウンタ１−２−３を
有し、切替器１−２−１はクロック設定レジスタ１−１
−１の設定により使用周波数を切り替え、デコ−ダ１−
２−２でデコ−ドしカウンタ１−２−３で入力周波数を
分周し、所定のサンプリングクロック及びボ−レ−トク
ロックを出力する。The ball generator 1-2 is a switch 1
-2-1, a decoder 1-2-2, a counter 1-2-3, and a switch 1-2-1 is provided with a clock setting register 1-1.
The frequency to be used is switched by setting -1, and the
The data is decoded in 2-2, the input frequency is divided in the counter 1-2-3, and a predetermined sampling clock and a predetermined clock are output.
【００１３】通信ブロック１−３は受信モジュ−ル１−
３−１及び送信モジュ−ル１−３−２を具備し、入力さ
れたサンプリングクロックで受信デ−タをバッファ（図
では省略）に受け外部インタフェ−ス３へ出力すると共
に、送信デ−タを所定の伝送速度で送信する。The communication block 1-3 includes a receiving module 1-
3-1 and a transmission module 1-3-2, receive reception data in a buffer (omitted in the figure) with the input sampling clock, output the received data to an external interface 3, and transmit data. Is transmitted at a predetermined transmission rate.
【００１４】図２は送／受信デ−タのフォ−マットの例
を示す図である。図示するように調歩同期式は所定のデ
−タ（図ではＤ１〜Ｄ８の８ビット＋パリティビット
Ｐ）にスタ−トビット及びストップビットを付加し一文
字毎に同期をとって送／受信する方式である。ここで受
信信号がＬレベルになって２度のサンプリングクロック
でＬレベルを確認した時点をスタ−トビットとする。各
デ−タビットはサンプリングクロックにより中央付近で
サンプリングされる。FIG. 2 is a diagram showing an example of the format of transmission / reception data. As shown in the figure, the start-stop synchronization method is a method in which a start bit and a stop bit are added to predetermined data (8 bits of D1 to D8 + parity bit P in the figure), and transmission / reception is performed in synchronization with each character. is there. Here, a point in time when the received signal becomes L level and the L level is confirmed by two sampling clocks is defined as a start bit. Each data bit is sampled near the center by a sampling clock.
【００１５】図３はデュアルクロック信号併用によるボ
−レ−トの精度を表す図である。図示するように、ボ−
レ−トが６００ｂｐｓのときは切替器１−２−１で時計
用クロック発振器６−１の出力信号（３２．７６８ＫＨ
ｚ）に切り替えカウンタ１−２−３で５５分周し所定の
サンプリングクロック及びボ−レ−トクロックを出力す
る。また、ボ−レ−トが２４００ｂｐｓのときも同様に
切替器１−２−１で時計用クロック発振器６−１の出力
信号（３２．７６８ＫＨｚ）に切り替えカウンタ１−２
−３で１３．５分周し所定のサンプリングクロック及び
ボ−レ−トクロックを出力する。何れの場合も±１％以
内に収めることができる。その他のボ−レ−トでは高周
波クロック発振器２の出力信号に切替る。なお、時計用
クロック発振器６−１の出力信号（３２．７６８ＫＨ
ｚ）を使用するときは高周波クロック発振器２を停止す
るので消費電流は減少する。FIG. 3 is a diagram showing the accuracy of the baud rate when dual clock signals are used together. As shown,
When the rate is 600 bps, the output signal of the clock oscillator 6-1 (32.768 KH) is output by the switch 1-2-1.
In z), the frequency is divided by 55 by the switching counter 1-2-3, and a predetermined sampling clock and a baud rate clock are output. Similarly, when the baud rate is 2400 bps, the switch 1-2-1 switches to the output signal (32.768 kHz) of the clock oscillator 6-1 for the counter 1-2.
The frequency is divided by 13.5 at -3 to output a predetermined sampling clock and a baud rate clock. In any case, it can be kept within ± 1%. In other baud rates, the output signal is switched to the output signal of the high frequency clock oscillator 2. The output signal of the clock oscillator 6-1 (32.768 KH
When z) is used, the high frequency clock oscillator 2 is stopped, so that the current consumption is reduced.
【００１６】以上述べたように本実施例では調歩同期式
伝送方式において、１２．６ＭＨｚの高周波クロック発
振器２の出力信号と３２．７６８ＫＨｚの時計用クロッ
ク発振器６−１の出力信号を切り替えて使用する切替器
１−２−１を用意し、６００ｂｐｓのボ−レ−トで伝送
するときは３２．７６８ＫＨｚを５５分周し、２４００
ｂｐｓのボ−レ−トで伝送するときは１３．５分周して
所定の精度のサンプリングクロック及びボ−レ−トクロ
ックを発生させ、１２．６ＭＨｚの高周波クロック発振
器２を停止することにより消費電流を低減することがで
きる。As described above, in this embodiment, in the start-stop synchronous transmission system, the output signal of the 12.6 MHz high frequency clock oscillator 2 and the output signal of the 32.768 kHz clock clock oscillator 6-1 are switched and used. A switch 1-2-1 is prepared, and when transmitting at a 600 bps rate, 32.768 KHz is divided by 55 to 2400
When transmitting at a bps baud rate, the frequency is divided by 13.5 to generate a sampling clock and a baud rate clock with predetermined accuracy, and the 12.6 MHz high frequency clock oscillator 2 is stopped to consume. The current can be reduced.
【００１７】[0017]
【発明の効果】以上説明したように本発明によれば、下
記のような優れた効果が期待される。 （１）デ−タ伝送速度に応じて低周波クロック発振器
（３２．７６８ＫＨｚ）又は高周波クロック発振器（１
２．６ＭＨｚ）の出力信号を切り替えて使用する切替手
段、及び、前記両クロック発振器の出力周波数を分周す
る分周手段を設け、所定のデ−タ伝送速度（６００ｂｐ
ｓ及び２４００ｂｐｓ）で伝送する際、前記高周波クロ
ック発振器を停止し、前記低周波クロック発振器の出力
信号を前記分周手段で適切に分周し所定の精度（±１％
以内）のサンプリングクロック及びボ−レ−トクロック
を発生させデ−タ伝送するので消費電流を低減すること
ができる。高周波クロック発振器の消費電流は約１ｍＡ
に対し、低周波クロック発振器の消費電流は約１０μＡ
だから消費電流を１／１００程度に低減することができ
る。As described above, according to the present invention, the following excellent effects are expected. (1) A low-frequency clock oscillator (32.768 kHz) or a high-frequency clock oscillator (1) according to the data transmission speed
(2.6 MHz) and a frequency dividing means for dividing the output frequency of both clock oscillators, and a predetermined data transmission rate (600 bp) is provided.
s and 2400 bps), the high-frequency clock oscillator is stopped, and the output signal of the low-frequency clock oscillator is appropriately divided by the frequency dividing means to obtain a predetermined accuracy (± 1%
Since the sampling clock and the ballet clock described in (1) and (2) are generated and transmitted, the current consumption can be reduced. High frequency clock oscillator consumes about 1mA
On the other hand, the current consumption of the low-frequency clock oscillator is about 10 μA
Therefore, current consumption can be reduced to about 1/100.
【００１８】（２）低周波クロック発振器は時計用とし
て使用しているものであり、簡単な回路構成及び小さい
回路規模で実現できる。(2) The low-frequency clock oscillator is used for a clock, and can be realized with a simple circuit configuration and a small circuit scale.
【図１】本発明の携帯端末のブロック構成例を示す図で
ある。FIG. 1 is a diagram illustrating an example of a block configuration of a mobile terminal according to the present invention.
【図２】送／受信デ−タのフォ−マットの例を示す図で
ある。FIG. 2 is a diagram showing an example of a format of transmission / reception data.
【図３】デュアルクロック信号併用によるボ−レ−トの
精度を示す図である。FIG. 3 is a diagram showing the accuracy of a baud rate when dual clock signals are used together.
【図４】従来の携帯端末のブロック構成例を示す図であ
る。FIG. 4 is a diagram illustrating an example of a block configuration of a conventional mobile terminal.
１ ＵＡＲＴ（調歩同期式デ−タ送受信部） １−１ Ｉ／Ｏコントロ−ラ １−１−１ クロック設定レジスタ １−１−２ ボ−レ−ト設定レジスタ １−２ ボ−レ−トジェネレ−タ １−２−１ 切替器 １−２−２ デコ−ダ １−２−３ カウンタ １−３ 通信ブロック １−３−１ 受信モジュ−ル １−３−２ 送信モジュ−ル ２ 高周波クロック発振器 ３ 外部インタフェ−ス ４ アンテナ ５ ＲＦ／ＩＦ部（高周波／中間周波部） ６ デジタル処理部 ６−１ 時計用クロック発振器 ６−２ ＣＰＵ（中央演算処理装置） ６−３ メモリ ７ 操作部 ８ 音声処理部 ９ 送受話器 1 UART (start-stop synchronous data transmission / reception unit) 1-1 I / O controller 1-1-1 Clock setting register 1-1-2 Baud rate setting register 1-2 Baud rate generator 1-2-1 Switch 1-2-2 Decoder 1-2-3 Counter 1-3 Communication block 1-3-1 Reception module 1-3-2 Transmission module 2 High frequency clock oscillator 3 External interface 4 Antenna 5 RF / IF unit (high frequency / intermediate frequency unit) 6 Digital processing unit 6-1 Clock oscillator for clock 6-2 CPU (Central processing unit) 6-3 Memory 7 Operation unit 8 Voice processing unit 9 Handset
Claims (1)
用の高周波クロック発振器を具備し、規定された種々の
伝送速度に対応可能な調歩同期式のデータ伝送を行なう
デ−タ伝送手段を具備する携帯端末において、 デ−タ伝送速度に応じて前記低周波クロック発振器又は
前記高周波クロック発振器の出力信号を切り替えて使用
する切替手段及び前記両クロック発振器の出力周波数を
分周する分周手段を設け、 所定のデ−タ伝送速度で伝送する際、前記高周波クロッ
ク発振器を停止し、前記低周波クロック発振器の出力信
号を前記分周手段で適切に分周し所定の精度のサンプリ
ングクロック及びボ−レ−トクロックを発生させデ−タ
伝送を行うデータ伝送手段を設けたことを特徴とする携
帯端末。1. A data transmission means which includes a low-frequency clock oscillator for clocking and a high-frequency clock oscillator for transmission, and performs start-stop synchronous data transmission capable of supporting various specified transmission speeds. In the portable terminal, switching means for switching and using an output signal of the low-frequency clock oscillator or the high-frequency clock oscillator in accordance with a data transmission rate, and frequency dividing means for dividing the output frequency of both clock oscillators are provided. When transmitting at a predetermined data transmission speed, the high-frequency clock oscillator is stopped, and the output signal of the low-frequency clock oscillator is appropriately divided by the frequency dividing means to obtain a sampling clock and a ballet with predetermined accuracy. A portable terminal comprising a data transmission means for generating data clocks and performing data transmission.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35409796A JP3504451B2 (en) | 1996-12-18 | 1996-12-18 | Mobile terminal |
| US08/992,413 US6198820B1 (en) | 1996-12-18 | 1997-12-17 | Portable remote terminal apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35409796A JP3504451B2 (en) | 1996-12-18 | 1996-12-18 | Mobile terminal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10178385A true JPH10178385A (en) | 1998-06-30 |
| JP3504451B2 JP3504451B2 (en) | 2004-03-08 |
Family
ID=18435282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35409796A Expired - Lifetime JP3504451B2 (en) | 1996-12-18 | 1996-12-18 | Mobile terminal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3504451B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6842478B1 (en) | 1999-03-26 | 2005-01-11 | Nec Corporation | Radio communication device and method capable of reducing power consumption by controlling an A/D converter |
| JP2011103672A (en) * | 2004-05-07 | 2011-05-26 | Qualcomm Inc | Power-efficient multi-antenna wireless device |
-
1996
- 1996-12-18 JP JP35409796A patent/JP3504451B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6842478B1 (en) | 1999-03-26 | 2005-01-11 | Nec Corporation | Radio communication device and method capable of reducing power consumption by controlling an A/D converter |
| JP2011103672A (en) * | 2004-05-07 | 2011-05-26 | Qualcomm Inc | Power-efficient multi-antenna wireless device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3504451B2 (en) | 2004-03-08 |
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