JP2965566B2 - Selective call receiver and receiver - Google Patents

Description

The present invention relates to a selective call receiver with a message display function and a receiver.

(Prior Art) In recent years, as a new type of selective paging method, a method has been proposed in which a call notification is made and a message code is transmitted and displayed. FIG. 3 shows an example of a signal configuration to which this type of system is applied. This calling method is
One frame is time-divided into a plurality of groups (n groups in the figure) as shown in FIG. 5A, and these groups are further divided into a synchronization word and a plurality of call words (m words in the figure) as shown in FIG. And time-divided. Then, when the caller sends a call request and a message to an arbitrary selective call receiver, the base station selects the empty call word of the group to which the selective call receiver belongs as shown in FIG. A selective call signal including an individual number code for identifying a call receiver and a message code is inserted and transmitted.

On the other hand, FIG. 4 shows an example of the configuration of a selective call receiver. The selective call receiver first receives a selective call signal transmitted from the base station by using an antenna 1, a radio circuit 2, and a demodulation circuit which constitute a receiving circuit. After receiving and demodulating at 3, it is introduced into the control circuit 4. Then, the control circuit 4 compares the individual number code in the selective call signal with the own number code stored in the ROM 5 in advance, and when both codes match, a call to the own device occurs. Then, a ringing signal is supplied to the speaker 7 via the drive circuit 6, thereby generating a ringing tone to notify the subscriber of the occurrence of the ringing. At the same time, the received message code is subjected to error correction and decoded, and the decoded message is supplied to a display 8 composed of, for example, a liquid crystal display and displayed.

By the way, in general, the selective call receiver performs battery saving in order to reduce the power consumption and describe the life of the battery. In this battery saving, for example, after synchronizing, the receiving circuit is operated and the selective calling signal is received only during the receiving period of the group to which the terminal belongs in one frame, and power is supplied to the receiving circuit during the receiving period of another group. The receiving operation is not performed.
In this way, when one frame is composed of n groups, the power consumption can be reduced to about 1 / n as compared with the case where the normal reception operation is performed, and the consumption of the battery can be suppressed accordingly. it can.

(Problems to be Solved by the Invention) However, although this type of conventional receiver performs battery saving, it does not perform battery saving during reception of a group other than the group to which the receiver belongs. It is necessary to perform a control operation or the like, which consumes current. Also, during the reception period of the group to which the own device belongs, the current is consumed equally whether or not the individual number code for the own device is inserted in the selective calling signal. For this reason, wasteful current consumption is still large, which has been a major problem in extending the battery life.

The present invention focuses on this point, and further reduces the current consumption during the non-arrival period of the call signal and the current consumption when the call is not a call to the own device even when the call signal arrives, thereby further increasing the battery life. An object of the present invention is to provide a selective call receiver and a receiver that can be extended.

[Configuration of the Invention] (Means for Solving the Problems) The selective call receiver of the present invention requires a high-speed clock in the decoding operation of a message code requiring error correction, but does not perform special error correction. Focusing on the fact that a high-speed clock is not necessary and a low-speed clock can sufficiently cope with the individual number code collation operation, a control circuit for collating the individual number code and decoding a message code is provided by a plurality of clocks having different speeds. And a clock generation circuit that supplies a first clock of a predetermined speed and a second clock of a lower speed than the first clock to the control circuit, and the control circuit includes:
The second clock is used during a reception period other than the group to which the own device belongs, a check period of the individual number code in the group to which the own device belongs, and a remaining reception period of the own group when a call to the own device is not detected by the check. And operates in synchronization with the second clock, and selects the first clock during a message receiving period when a call to the own device is detected as a result of the collation of the individual number code. The decoding operation of the message code is performed in synchronization with the first clock.

Further, the receiver of the present invention is characterized in that the control circuit determines that the first signal is received during the subsequent message signal reception period only when the two signals match as a result of the comparison between the call signal transmitted from the base station and the call signal of the own device. A clock is selected to perform a message code decoding operation in synchronization with the first clock, and a second clock is selected in other periods to operate in synchronization with the second clock. Things.

(Operation) As a result, the control circuit operates by the high-speed first clock only when a call to the own device is detected during the reception period of the group to which the own device belongs, and otherwise operates by the low-speed second clock. Therefore, the control circuit operates at a low current by the low-speed clock unless a call to the own device occurs. As a result, the current consumption can be reduced as compared with the conventional case where the matching of the individual number code is performed using a high-speed clock in the same manner as the decoding of the message code, and the battery life can be further extended. Become.

Further, the control circuit operates at a low current by the low-speed clock in the period of a group other than the group to which the control circuit belongs, in addition to the reception period of the group to which the control device belongs. For this reason, the current consumption during the non-reception operation is further reduced as compared with the conventional case, whereby the life of the battery is further extended.

(Embodiment) FIG. 1 shows a configuration of a selective call receiver according to an embodiment of the present invention. 4, the same parts as those in FIG. 4 are denoted by the same reference numerals, and detailed description is omitted.

The selective calling receiver of this embodiment uses a two-clock type microcomputer as the control circuit 40.
Further, a clock generation circuit 9 for supplying an operation clock to the control circuit 40 is provided. The clock generation circuit 9 includes a first clock oscillator 91 that generates a high-speed clock necessary for performing a decoding process of a message code,
A second clock oscillator 92 that generates a low-speed clock that is necessary and sufficient for verifying the individual number code at a lower speed than the high-speed clock. Reference numeral 10 denotes a battery saving circuit for turning on and off power supply to the radio circuit 2 and the demodulation circuit 3 in accordance with an instruction from the control circuit 40.

Further, the control circuit 40 includes clock switching control means in addition to ordinary functions such as individual number code collating means, message code decoding means, call notification control means, message display control means, and battery saving control means. . This clock switching control means is generated from the second clock oscillator 92 as an operation clock when the individual number code is checked in the entire reception period of the group other than the group to which the own device belongs and the reception period of the group to which the own device belongs. The low-speed clock is selectively introduced to the control circuit 40. A high-speed clock generated from the first clock oscillator 91 is introduced for decoding a message code only when a call to the own device is detected during a reception period of the group to which the own device belongs.

Next, the operation of the selective call receiver configured as described above will be described. Assuming that the group to which the own device belongs is group 2, the control circuit 40 outputs an on / off control signal to the battery saving circuit 10 after the completion of the synchronization pull-in, and as a result, as shown in FIG. The so-called battery saving control for setting the radio circuit 2 and the demodulation circuit 3 to the reception operation state only during the reception period of the group 2 to which the group 2 belongs is performed. Further, the control circuit 40 introduces and uses a low-speed clock generated from the second clock oscillator 92 as an operation clock during the entire period of one frame unless a call to the control circuit is detected. Therefore, the control circuit 40 executes the battery saving control in the reception period of each group to which the own device does not belong and the collation operation of the individual number code in the reception period of the group 2 to which the own device belongs in synchronization with the low-speed clock. Will be. For this reason, the current consumption of the control circuit 40 is reduced as compared with the conventional selective calling receiver in which various controls are executed in synchronization with the high-speed clock for the entire period of one frame. Since the individual number code collation does not require error correction and does not require high-speed operation, no problem occurs even if a low-speed clock is used as described above.

On the other hand, when the call to the own device is detected as a result of the collation of the individual number code, the control circuit 40 at this point changes the operation clock from the low-speed clock generated from the second clock oscillator 92 as shown in FIG. The high-speed clock generated by the first clock oscillator 91 is switched. Thereafter, the message code is decoded in synchronization with the high-speed clock, and the operation clock is returned to the low-speed clock generated from the second clock oscillator 92 when the decoding is completed.

As described above, according to the present embodiment, the high-speed clock generated from the first clock oscillator 91 is used only when a message code requiring high-speed operation is decoded, and the high-speed clock generated from the second clock oscillator 92 is used during other periods. Since the control circuit 40 is operated using a low-speed clock, the control circuit 40 is compared with a conventional receiver that uses a high-speed clock for all periods.
, The power consumption of the receiver can be reduced, and the life of the battery can be prolonged accordingly.

The present invention is not limited to the above embodiment.
For example, in the above embodiment, the high-speed clock is used for decoding the message code, and the low-speed clock is used for other control. However, this low-speed clock is further divided into two.
The higher speed may be used for collating the individual number code, and the lower speed may be used for battery saving control. In the above embodiment, the high-speed clock oscillator and the low-speed clock oscillator are separately provided. However, a clock is switched by providing a reference oscillator and a variable frequency divider, and varying the frequency division ratio of the variable frequency divider. It may be performed. In addition, the control means and control contents of the control circuit, the configuration of the clock generation means and the clock switching means, and the like can be variously modified and implemented without departing from the gist of the present invention.

[Effects of the Invention] As described in detail above, the selective call receiver according to the present invention is configured such that a control circuit for checking an individual number code and decoding a message code can be operated by a plurality of clocks having different speeds. , A first speed of a predetermined speed
Clock and a second clock slower than the first clock.
A clock generation circuit that supplies a clock of each of the above-described devices. During the remaining reception period of the own group in the case where there is no call, the second clock is selected and operated in synchronization with the second clock, and a call to the own device is detected as a result of the verification of the individual number code. In the message receiving period in this case, the first clock is selected, and the decoding operation of the message code is performed in synchronization with the first clock.

Further, the receiver of the present invention is characterized in that the control circuit determines that the first signal is received during the subsequent message signal reception period only when the two signals match as a result of the comparison between the call signal transmitted from the base station and the call signal of the own device. A clock is selected to perform a message code decoding operation in synchronization with the first clock, and a second clock is selected in other periods to operate in synchronization with the second clock. Things.

Therefore, according to the present invention, the current consumption during the non-arrival time of the call signal and the current consumption when the call is not a call to the own device even when the call signal arrives are further reduced, thereby further extending the battery life. A selective call receiver and receiver can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing the configuration of a selective calling receiver in one embodiment of the present invention, FIG. 2 is a timing diagram used for explaining the operation of the receiver, and FIG. 3 is an example of the configuration of a selective calling signal. FIG. 4 is a circuit block diagram showing the configuration of a conventional selective call receiver. 1 ... antenna, 2 ... radio circuit, 3 ... demodulation circuit, 40
...... Control circuit, 5 ... ROM, 6 ... Drive circuit, 7 ... Speaker, 8 ... Display unit, 9 ... Clock generation circuit, 91 ...
... First clock oscillator for high-speed clock generation, 92 ...
Second clock oscillator for low-speed clock generation, 10... Battery saving circuit.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Tatsuaki Sekikawa 3-1-1 Asahigaoka, Hino-shi, Tokyo Inside the Toshiba Hino Plant (72) Inventor Shihoko Oyanagi 3-1-1 Asahigaoka, Hino-shi, Tokyo 1 share Toshiba Hino Factory (72) Inventor Mitsushi Shiono 3-1-1 Asahigaoka, Hino-shi, Tokyo Toshiba Communication Systems Engineering Co., Ltd. (56) References Shokai Sho56-53844 (JP, U) Shokai Sho58 −184945 (JP, U)

Claims (2)

(57) [Claims] A receiving circuit receives only a group to which the terminal belongs out of one frame transmitted from a base station, and an individual number code in a selective call signal inserted into the group is controlled by the control circuit. In a selective call receiver that compares with an individual number code, and notifies that a call has occurred when both codes match with a reporter, and decodes a message code in the selective call signal and displays it on a display, A clock generation circuit configured to operate the control circuit with a plurality of clocks having different speeds and supplying the control circuit with a first clock having a predetermined speed and a second clock having a lower speed than the first clock; The control circuit, the receiving period other than the group to which the own device belongs, the collation period of the individual number code in the group to which the own device belongs, and During the remaining reception period of the own group in the case where a call to the own device is not detected, the second clock is selected and operated in synchronization with the second clock, and verification of the individual number code is performed. As a result, during a message reception period when a call to the own device is detected, the first clock is selected and a message code decoding operation is performed in synchronization with the first clock. Machine. And a control circuit that operates in synchronization with a clock. The control circuit compares a call signal transmitted from a base station with a call signal of the own device, and when the two signals match, the call signal is generated. A receiver for decoding a message signal sent from a base station following the above, wherein the control circuit is configured to be operable by a plurality of clocks having different speeds, and the control circuit is provided with a first clock having a predetermined speed and the first clock. A clock generating circuit that supplies a second clock that is slower than the clock of the control unit. The control circuit compares the calling signal transmitted from the base station with the calling signal of the own device, and the two signals match. Only in this case, the first clock is selected during the subsequent message signal reception period, the message signal is decoded in synchronization with the first clock, and the other period is selected. Receiver, characterized by operating in synchronization by selecting the second clock to the second clock.