JPS58184945U

JPS58184945U - Wireless individual selective paging receiver with message information reception function

Info

Publication number: JPS58184945U
Application number: JP1982080396U
Authority: JP
Inventors: 森　泰啓
Original assignee: 日本電気株式会社
Priority date: 1982-05-31
Filing date: 1982-05-31
Publication date: 1983-12-08
Also published as: JPS6347102Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は１０−２のビット誤り率を得るのに必要な受信
入力対伝送速度の関係を表わすグラフ、第２図は本考案
による実施例として、個別選択呼出受信機の構成を示す
ブロック図、第３図ａ”ｍは、第２図における実施例の
特にデコーダの各部の動作を説明するためのタイムチャ
ート、第４図は、第２図に聴けるデコーダ２０の具体的
な構成例を示すブロック図、第５図は、第４図における
一プリアンプル信号検出回路の具体的な構成例を示５　
す図、第６図は、第４図における同期信号検出回路の具
体的な構成例を示す図、第７図は、第４図における終了
信号検出回路の具体的な構成例を示す図、第８図は、第
４図における呼出信号検出回路の具体的な構成例を示す
図、第９図は、第２図における制御部３０の具体的な構
成例を示すブロック図、第１０図は、第２図における表
示部４０の具体的な構成例を示すブロック図、第１１図
、第１２図および第１３図は、第４図におけるクロック
再生回路２７０および分周回路２０１に代って用いられ
るクロック再生方式の構成をそれぞれ示すブロック図、
第１４図は、第１２図の回路の動作を説明するためのタ
イムチャート、第１５図は、第１３図の回路の動作を説
明するためのタイムチヤードである。図において、１０はアンテナ、１１は受信部、１２は波
形整形部、１３はスイッチ回路、１４はＰ−ＲＯＭ、１
５はバッファアンプ、１６はスピーカ、１９はリセット
スイッチ、２０，６０１゜７０１．８０２はデコーダ、
３０は制御部、３０ａはＣＰＵ、３０ｂはＲＯＭ、３Ｑ
ｃはＲＡＭ。４０は表示部、４０ａはキャラクタ−ジェネレータ、４
０ｂはドライバー、４０ＣはＬＣＤ、２０１゜２０３．
８０１は分周回路、２１０はプリアンプル信号検出回路
、２２０は同期信号検出回路、２３０は終了信号検出回
路、２４０は呼出信号検出回路、２５５．２５８はタイ
マ、２７０゜６００〜−１〜ｎはクロック再生回路、２
７３は３１進カウンタ、２７５は３進カウンタ、２０４
゜２５２．２６１〜２６３．２７１はＤタイプのＦ／Ｆ
、３０１〜３０３は出力ポート、３０４〜３０６は入力
ポート、３０８は割り込みポート、３１０は入出力ポー
ト、３１２はプログラム力・ウンタ、３１３はＡＬｔＪ
、　３　ｌ　５はインストラクション・デコーダ、４０
１はシリアルインタフェース、４０２はコマンドデコー
ダ、４０３はキャラクタ発生回路、４０４はデータポイ
ンタ、４０５はデータメモリ、４０６はＬＯＷドライバ
、４０７はコラムドライバ、７００．８００はクロック
発生源である。 −１１２０ｈｔら　　２５７＃″ら第５図ｚｏｔ◆１．、　　　２５’ｌｆ”ｙ　　　　　　　　
’′ＩＰ−一　　　　　　　−− ４第１０図仮　　　　　第１１図１−　　　　　　　　　、　　ｆｗ’！Ｎ（ｔｒ〜ｆｎ
）ヨＵ　　−第１２図FIG. 1 is a graph showing the relationship between reception input and transmission speed necessary to obtain a bit error rate of 10-2, and FIG. 2 is a block diagram showing the configuration of an individual selective calling receiver as an embodiment of the present invention. , FIG. 3 a"m is a time chart for explaining the operation of each part of the decoder in the embodiment shown in FIG. 2, and FIG. 4 shows a specific example of the configuration of the decoder 20 that can be heard in FIG. The block diagram, FIG. 5, shows a specific example of the configuration of one preamble signal detection circuit in FIG. 4.
6 is a diagram showing a specific example of the configuration of the synchronization signal detection circuit in FIG. 4, and FIG. 7 is a diagram showing a specific example of the configuration of the termination signal detection circuit in FIG. 8 is a diagram showing a specific example of the configuration of the calling signal detection circuit in FIG. 4, FIG. 9 is a block diagram showing a specific example of the configuration of the control section 30 in FIG. 2, and FIG. The block diagrams, FIGS. 11, 12, and 13 showing specific configuration examples of the display section 40 in FIG. 2 are used in place of the clock regeneration circuit 270 and the frequency dividing circuit 201 in FIG. Block diagrams showing the configurations of each clock recovery method,
14 is a time chart for explaining the operation of the circuit of FIG. 12, and FIG. 15 is a time chart for explaining the operation of the circuit of FIG. 13. In the figure, 10 is an antenna, 11 is a receiving section, 12 is a waveform shaping section, 13 is a switch circuit, 14 is a P-ROM, 1
5 is a buffer amplifier, 16 is a speaker, 19 is a reset switch, 20,601゜701.802 is a decoder,
30 is a control unit, 30a is a CPU, 30b is a ROM, 3Q
c is RAM. 40 is a display unit, 40a is a character generator, 4
0b is the driver, 40C is the LCD, 201°203.
801 is a frequency dividing circuit, 210 is a preamble signal detection circuit, 220 is a synchronization signal detection circuit, 230 is an end signal detection circuit, 240 is a calling signal detection circuit, 255.258 is a timer, 270°600~-1~n are Clock regeneration circuit, 2
73 is a 31-decimal counter, 275 is a ternary counter, 204
゜252.261~263.271 is D type F/F
, 301 to 303 are output ports, 304 to 306 are input ports, 308 is an interrupt port, 310 is an input/output port, 312 is a program output/counter, and 313 is an ALtJ
, 3 l 5 is an instruction decoder, 40
1 is a serial interface, 402 is a command decoder, 403 is a character generation circuit, 404 is a data pointer, 405 is a data memory, 406 is a LOW driver, 407 is a column driver, and 700.800 is a clock generation source. -11 20ht et al. 257 #" et al. Figure 5 zot◆1., 25'lf"y
''IP-1 -- 4 Figure 10 Temporary Figure 11 1-, fw'! N(tr~fn
) Yo U - Figure 12

Claims

[Claims for Utility Model Registration] 1. The invention is characterized in that a clock regeneration means is provided for synchronizing bits corresponding to each data signal with respect to a received signal consisting of a plurality of data signals each having a different transmission speed. A wireless individual selective paging receiver equipped with a function to receive message information. 2 Utility Model Registration A message in the radio individual selective calling receiver set forth in claim 1, characterized in that the clock regeneration means is comprised of a plurality of pieces corresponding to the number of different transmission speeds. A wireless individual selective call receiver with an information receiving function. 3. Utility Model Registration In the wireless individual selective calling receiver according to claim 1, the clock regeneration means has a frequency N times the highest frequency (N is 2 When receiving data with different transmission speeds,
A wireless individual selective call receiver having a message information receiving function, characterized in that a majority vote is applied between the respective transmission speeds and the N times the clock signal. 4 Utility Model Registration In the radio individual selective calling receiver according to claim 1, the clock regeneration means is configured to have a frequency N times the highest frequency (N is 2 The circuit consists of a first circuit that generates a clock signal for the above rectification) and a second circuit that receives the output of the clock signal generation circuit and divides the output frequency, and receives data at different transmission speeds. In this case,
The message information receiving function is characterized in that the ratio between the frequency of the output frequency divided by the second circuit and the respective transmission speeds is always constant, and a means of majority voting is applied between them. Wireless individual selective call receiver.