JPS6347102Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention is applied to an individual selective paging communication system that selectively calls multiple receivers scattered over a wide area from a base station transmitter, and receives message information along with a selective paging signal. The present invention relates to a digital wireless individual selective call receiver capable of displaying.

In recent years, with the progress of integrated technology, the use of individual selective calling receivers has increased from the conventional calling only service to those capable of providing message information services. By the way, the ultimate challenge for individual selective calling receivers is to make effective use of channels and increase system capacity as much as possible. However, a service that adds message information inevitably requires a longer channel time per subscriber than a conventional call-only service, resulting in a reduction in system capacity. Therefore,
It is possible to increase the transmission speed, but as is clear from the graph in Figure 1, simply increasing the transmission speed will degrade the sensitivity, so it is necessary to increase the transmitter power or reduce the transmitter power. There was a problem in that unless the number of transmitters was left as is and the number of transmitters was increased, it would not be possible to secure the same service area as before.

The purpose of the present invention is to solve the problems caused by the above-mentioned prior art, and to dramatically increase the system capacity by providing different transmission speeds for the paging signal and the message information signal. An object of the present invention is to provide a wireless individual selective calling receiver having a receiving function.

The purpose of the present invention is not to simply increase the transmission speed, but to adopt a so-called hybrid system concept in which the transmission speed is changed between the calling number information signal and the message information signal. A range that does not cause significant deterioration in sensitivity by comparing the part with the calling signal,
For example, by increasing the transmission speed to about twice as high, the system capacity can be dramatically increased.

According to the present invention, message information is provided with clock regeneration means for bit synchronizing each data signal with respect to a received signal composed of a plurality of data signals each having a different transmission speed. Thus, a wireless individual selective calling receiver having a receiving function is obtained.

Next, the individual selective calling receiver according to the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an individual selective calling receiver as an embodiment of the present invention. According to this example, the receiver includes an antenna 10, a receiving section 11, a waveform shaping section 12, a switch circuit 13 for switching the supply of power, a P-ROM 14 in which a calling number etc. are written, and a buffer amplifier 15. , a speaker 16 , a battery 17 ,
A power switch 18, a reset switch 19,
receiving message information with the decoder 20;
CPU30a and ROM30b that control the display
A control unit 30 including a RAM 30c, a character generator 40a, and an LCD driver 40b.
The display unit 40 includes an LCD 40c and a battery 50. The operation of the receiver configured in this way will be explained with reference to the time chart of FIG. 3. Now, in this receiver, the power switch 18 is closed, and the switch circuit 13 intermittently turns the power ON (60ms) and OFF to the front section with the stroke shown in FIG. 3B.
(1005ms) is repeated. In this state, only when the power is on, the received signal as shown in FIG.
The signal is received by the receiving section 11 and provided to the decoder 20 via the waveform shaping section 12.

The decoder 20 includes frequency dividing circuits 201 and 203, as shown in FIG.
, an OSC 202, a preamble signal detection circuit 210, a synchronization signal detection circuit 220, an end signal detection circuit 230, a ringing signal detection circuit 240, and a 1.2 second timer 255 responsive to the detection of a preamble signal. A 12-second timer 258 responsive to detection of a synchronization signal, a clock regeneration circuit 270, a 31-ary counter 273, a 3-ary counter 275, and inverter gates 205, 206, 253, 259, 2
67 and 272 and AND gates 207, 20
8,250,251,256,260,266,
265, 268, 269 and 274, OR gates 254, 257, 264 and 276, and D
Type F/F204, 252, 261, 26
2,263 and 271.
Therefore, the signal given from the waveform shaping section 12 is bit synchronized by the clock regeneration circuit 270 of the decoder 20, and its output is sent to the frequency divider circuit 201.
is converted to the clock frequency necessary to receive the preamble signal, frame synchronization, and address signals. On the other hand, the data given to the synchronization circuit 204 composed of a D-type F/F is read here, and its output is sent to the preamble signal detection circuit 204.
0, is input to the synchronization signal detection circuit 220, end signal detection circuit 230, and calling signal detection circuit 240. When the preamble signal generation circuit 210 configured as shown in FIG. 5 detects the pattern "01010101", the gate 2
F/F252 by the output signal of 07 (Fig. 3 d)
(Fig. 3e), inhibits gate 207 via gate 206, and gate 20
8 is opened and a control signal (FIG. 3c) is sent to the switch circuit 13 via gates 253 and 254.
At the same time, a timer 255 is activated to produce 1.2 seconds in response to F/F 252, applying power to all receivers regardless of the battery save signal (Figure 3b). If the detection of the signal by the synchronization signal detection circuit 220 configured as shown in FIG.
is reset, and the output signal b of the frequency dividing circuit 203 is
With a stroke of , the signal shifts to intermittent reception due to battery saving.

However, within 1.2 seconds, the synchronization signal detection circuit 22
When the detection of the frame synchronization signal is confirmed at 0, the output signal of the gate 208 (FIG. 3 f) causes the F/
F261 is set, and the timer 258 is started to provide sufficient time (12 seconds in this example) to finish detecting the ringing signal.
9 to inhibit gate 256 and timer 255
Prevents the output of At the same time, gates 250, 25
1, 269 in preparation for receiving a ringing signal or an end signal to return to battery saving operation. If 12 seconds pass without receiving anything in this state and the timer 258 times out, the signal is sent to the preamble signal detection circuit 210 and the synchronization signal detection circuit 22 via the gate 257.
0, end signal detection circuit 230, F/Fs 252, 261 and timer 25, which are composed of the circuit shown in FIG.
5,258 is reset, and the process returns to intermittent reception using the output b of the frequency dividing circuit 203. However, if the calling signal of the machine is inputted before the timer 258 times out, 31 addresses are specified via the gate 269 in response to the clock inputted by the 31-decimal counter 273. The calling signal of the own machine is written by the 31-decimal counter 273,
For example, P.
The data in the ROM 14 is read out and inputted to the call signal detection circuit 240, which is constituted by the circuit shown in FIG. As a result, the ringing signals are compared bit by bit, and each time a match is confirmed, the counter 242 is
The second half of the pulse of the 31st bit is applied to the calling signal detection circuit 240 via the gate 268, and the result is read out. In this way, when it is confirmed that the calling signals match, a logic "1" signal passes through the gate 251 to set the F/F 262 to output the signal j, and further passes through the gate 260 to output the signal i. Send it to the sending CPU 30a. However, since the signal from the CPU 30a (FIG. 3k) is logic "0" here, it is blocked by the gate 265 and no sound is produced.

By the way, the function designation information of the receiver is sent to the ternary counter 2 via the gate 274 to the P-ROM 14 in which the presence/absence of the auto-reset function and the code structure information of the signal to be detected are written.
75 and read into the CPU via the input port 304 of FIG. 9 that constitutes the control section 30, the control section 30 is in a standby state according to the read function specification. In this way, the detected matching information of the calling number is sent to the interrupter 3 of the control unit 30 which receives the interrupt signal by the signal i.
When the signal is input to #1 of 08, program data is set via the data bus 311 in preparation for the detection of the message signal sent subsequently.

What should be noted in the circuit of FIG. 4 is the relationship between the clock cycle of the clock regeneration circuit 270 and the output cycle of the frequency divider circuit 201. That is, the output of the clock regeneration circuit 270 is used to detect and process signals with a high transmission rate, for example, 400 bit/s data, among the signals making up the received signal.
It is guided to the message information synchronization circuit 271 and the CPU 30a as a clock signal with a frequency of 800 Hz. On the other hand, the output of the divide-by-2 circuit 201 is a clock signal with a frequency of 400 Hz, which is divided to 1/2 of the output frequency of the clock regeneration circuit 270.
It is used to process low-speed data of 200 bit/s.

FIG. 9 is a block diagram showing a specific example of the control section 30. In this example, output ports 301~
303, input ports 304 to 306, interrupt port 308, and serial interface 30
9, input/output port 310, and data bus 311
and program counter 3 that specifies the contents of the address.
12, a program ROM 30b in which a sea case of an instruction to be executed is stored and reads out the contents of the address specified by the program counter 312;
An instruction decoder 315 decodes information from the ROM 30b and supplies control signals corresponding to the instructions to each part, and a ROM 3
An ALU 313 that performs various operations such as arithmetic operations and logical operations with a program counter 312 that is incremented by 1 every time information is passed from 0b to an instruction decoder 315 or changed in response to a branch instruction or jump instruction. RAM 30c is used to store various data, subroutines, program counts for interrupts, save program status, and the RAM 30c is used to store the calculation results of ALU 313.
Used for sending and receiving data between 307 and 310
It is composed of an ACC 314, a system clock generation circuit 316 that determines the execution instruction cycle time, and a count clock generation circuit 317 that is used as a clock source for various timings.

Now, referring to FIG. 9, message information synchronized with the clock by the synchronization circuit 271 of the decoder 20 is sent to the CPU 30 via the input port 305.
input to a. A clock signal is also read from the output of clock recovery circuit 270 via input port 306. And 31 with ALU313
Arithmetic processing is performed bit by bit according to the procedure written in the ROM 30b, and 21 bits of the 31 bits mentioned above are stored in the RAM 30c.
to be memorized. In this way, all information bits are sequentially detected. If more errors than the specified number of errors (2 in this embodiment) are detected in the 31-bit unit calculation process in the ALU 313,
It is assumed that the message information has not been received.
F/ from output port 302 through gate 276
Reset F262, 263. However, when all the message information is detected, the output port 30
Set the F/F 263 through 3 and open the gate 26.
4,266, the buffer amplifier 15 causes the speaker 16 to sound. This notifies the receiver holder that a call has been made, and at the same time, the RAM 3 in which the content of the received message is stored.
Data is read from 0c and sent to the display section 40 via the serial interface 309.

FIG. 10 is a block diagram showing a specific example of the display section 40. As shown in FIG. According to this example, the display section 40
A serial interface 401 serially connects data to and from the CPU 30a, and a command decoder 402 that takes in and decodes instructions input through the serial interface 409 and controls each part according to the contents of the instructions. , a character generation circuit 403 that generates a 7×5 dot matrix pattern in response to input data, and a character generation circuit 403 that writes data from the serial interface 401 or sets an address for reading data to the serial interface 401. The specified data pointer 404 and the output of the character generation circuit 403 or the serial interface 4
Data memory 4 for storing display data from 01
05 and the LOW driver 40 that controls the LCD rows.
6, and a column driver 4 that performs LCD column control.
07, an LCD voltage controller 408 that controls the supply voltage to the LCD, and an LCD timing controller 409 that controls the drive timing of the LCD.
and a system clock controller 410.

The operation of the display unit 40 will be explained with reference to FIG.
01, the command decoder 402 translates the message data, and the message data is sent to the character generating circuit 4.
03, is addressed by a data pointer 404, and input into a data memory 405. At the same time, the ROW driver 406 and the column driver 40 according to the LCD timing controller 409
7 to read the contents of the received message.
Display on LCD 40c. When you want to reset the sound, push the push switch 19. In response to the signal from the decoder 20 and #2 of the interrupter 308 of the external interrupt input terminal, the output is sent to the F/F 262 via the output port 302 and the gate 276. , 263. However, the display will be displayed again while the sound is stopped.
It switches on and off only when is pressed or when 8 seconds have elapsed since the start of the display.

In the above embodiment, the clock regeneration circuit 270 and the divide-by-2 circuit 2 in FIG. 4 are used as means for receiving input signals having different transmission speeds.
01 was used, but the circuits shown in FIGS. 11, 12, and 13 may be used instead.
Among these, the circuit shown in FIG. 11 is provided with clock regeneration circuits 600-1 to 600-n corresponding to different types of transmission speeds, and when receiving signals, the decoder 601 is controlled using the output of each clock regeneration circuit. be. According to this, the accuracy is improved, but the scale becomes larger.

The circuit shown in FIG. 12 has a clock generation source 700 whose frequency is N times the highest frequency (N is an integer of 2 or more) among the transmission speeds that constitute the signal, and applies the principle of majority voting when receiving signals. Controls decoder 701. For example, if the signal is 100bit/s and 300bit/s
Assuming that it is composed of NRZ (Non-Return-To-Zero) code and the frequency of the clock generation source 700 is 900Hz, when receiving a 100bit/s signal as shown in the time chart of FIG. Data is defined as data that matches one bit of the signal when read in 5 or more clocks in 9-clock units.
Further, when receiving a signal of 300 bit/s, it is possible to receive the signal by reading one bit of the signal in units of three clocks and using data that match two or more clocks as data. Note that this configuration is relatively simple in circuit configuration since it is sufficient to use a counter instead of the clock regeneration circuit.

The circuit of FIG. 13 includes a clock generation source 800 whose frequency is N times (N is an integer of 2 or more) the highest frequency among the transmission speeds constituting the signal, and a frequency dividing circuit 801.
The clock generation source 800 is frequency-divided by a frequency dividing circuit so that the ratio with the clock corresponding to each transmission speed is constant, and the decoder 802 is controlled by applying the principle of majority voting when receiving signals. For example, if the signal is composed of NRZ codes of 100 bit/s and 300 bit/s, and the frequency of the clock generation source 800 is 900 Hz, a 200 bit/s signal is received as shown in the time chart of Fig. 15. When receiving a 300 bit/s signal, the output of the clock generation source 800 is used as the clock as it is, whereas when receiving a 300 bit/s signal, the output of the clock generation source 800 is used as the clock. Then, the signal can be received by evaluating one bit of the input signal in units of three clocks, and assuming that the data read in two or more clocks agrees as data. This configuration has the advantage that it does not require a clock regeneration circuit, and that the majority circuit can be shared by using a frequency dividing circuit, thereby simplifying the circuit configuration.

As is clear from the above explanation, according to the present invention, the clock regenerating means is configured to perform bit synchronization corresponding to each data signal with respect to a received signal composed of a plurality of data signals having different transmission speeds. By providing this, the transmission speed can be set as before for calling signals to prevent deterioration of reception sensitivity, and the transmission speed for message signals can be set to a high enough level that it does not interfere with reception. The system capacity for receiving message information can be dramatically increased compared to the conventional system, which has great effects.

[Brief explanation of drawings]

Figure 1 is a graph showing the relationship between reception input and transmission rate necessary to obtain a bit error rate of 10 ^-2 , and Figure 2 is a block diagram showing the configuration of an individual selective calling receiver as an embodiment of the present invention. , Figure 3 a-m
2 is a time chart for explaining the operation of each part of the decoder in the embodiment shown in FIG. 2, FIG. 4 is a block diagram showing a specific example of the configuration of the decoder 20 in FIG. 2, and FIG. FIG. 6 is a diagram showing a specific configuration example of the preamble signal detection circuit in FIG. 4, FIG. 7 is a diagram showing a specific configuration example of the synchronization signal detection circuit in FIG. FIG. 8 is a diagram showing a specific configuration example of the end signal detection circuit, FIG. 8 is a diagram showing a specific configuration example of the calling signal detection circuit in FIG. 4, and FIG. 9 is a diagram showing a specific configuration example of the calling signal detection circuit in FIG. FIG. 10, a block diagram showing a specific example of the configuration, shows the display unit 40 in FIG.
A block diagram showing a specific example of the configuration, FIG.
12 and 13 are block diagrams showing the configuration of a clock recovery method used in place of the clock recovery circuit 270 and frequency dividing circuit 201 in FIG. 4, respectively, and FIG. 14 shows the operation of the circuit in FIG. 12. FIG. 15 is a time chart for explaining the operation of the circuit shown in FIG. 13. In the figure, 10 is an antenna, 11 is a receiving section,
12 is a waveform shaping section, 13 is a switch circuit, 14 is a P-ROM, 15 is a buffer amplifier, 16 is a speaker, 19 is a reset switch, 20, 601,
701 and 802 are decoders, 30 is a control unit, 30
a is CPU, 30b is ROM, 30c is RAM, 4
0 is a display unit, 40a is a character generator, 40b is a driver, 40c is an LCD, 20
1, 203, 801 is a frequency dividing circuit, 210 is a preamble signal detection circuit, 220 is a synchronization signal detection circuit, 230 is an end signal detection circuit, 240 is a calling signal detection circuit, 255, 258 is a timer, 270,
600-1 to n are clock regeneration circuits, 273 is 31
decimal counter, 275 is ternary counter, 204,2
52,261 to 263,271 are D type F/
F, 301-303 are output ports, 304-30
6 is an input port, 308 is an interrupt port, 31
0 is an input/output port, 312 is a program counter, 313 is an ALU, 315 is an instruction decoder, 401 is a serial interface, 402 is a command decoder, 403 is a character generation circuit, 404 is a data pointer, 405
is data memory, 406 is LOW driver, 40
7 is a column driver, and 700 and 800 are clock generation sources.

Claims (1)

[Claims for Utility Model Registration] 1. In response to a received signal consisting of a data signal having a predetermined first transmission rate and a data signal having a second transmission rate slower than the first transmission rate. A radio individual selective calling receiver having a function of receiving message information capable of transmitting a message, comprising: means for generating a main clock having a repetition frequency corresponding to a first transmission rate; and receiving the main clock and the received signal; Said first
and bit synchronization means for generating a first clock signal bit-synchronized with a data signal having a transmission rate of 0.05 and a second clock signal bit-synchronized with the data signal having a second transmission rate. What is claimed is: 1. A wireless individual selective calling receiver having a message information receiving function. 2 Utility Model Registration Scope of the Claims In the radio individual selective calling receiver as set forth in claim 1, the means for generating the clock is configured to generate a clock that is N times the first transmission rate (N is an integer of 2 or more) as the main clock. A radio individual selective paging receiver having a function of receiving message information, characterized in that means is provided for generating a main clock signal having a frequency of , and performing majority logic between the main clock and the received signal. Machine. 3. Utility Model Registration In the radio individual selective calling receiver as set forth in claim 1, the means for generating the main clock is configured to generate a first transmission rate N times the first transmission rate (N is an integer of 2 or more). generating a main clock signal having a frequency, and the bit synchronizing means generates the first and second clock signals whose frequencies are divided so that the ratio of the frequencies of the main clock and the received signal is constant. A wireless individual selective calling receiver equipped with a message information receiving function.