JPH0150147B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is applied to an individual selective paging communication system that selectively calls a plurality of receivers scattered over a wide area from a transmitter of a base station, and receives message information together with a selective paging signal. The present invention relates to a digital wireless individual selective call receiver capable of displaying.

In recent years, with advances in circuit integration technology, wireless individual selective calling receivers having a function for displaying received information are being developed.
Generally, the difference between a wireless selective call receiver and a mobile phone radio is that a wireless selective call receiver is capable of one-way communication, whereas a mobile telephone radio is capable of bidirectional communication. This means that the ultimate goal of the wireless selective paging service is to configure the system to minimize the amount of information necessary for message transmission, keep system capacity as large as possible, and increase channel efficiency. It means.

By the way, this kind of wireless selective calling receiver with an information display function currently in use handles only numerical information consisting of up to 10 digits as message information, and receives this following the individual selective calling number. There is. However, this method is inappropriate for transmitting and receiving the minimum amount of transmission information required for message information in one-way communication. Here, the minimum transmission information refers to information including contents such as "time", "place", "person", and "instruction". There is also another method that can transmit long message information consisting of up to 960 characters. However, this system has the disadvantage that the line occupation time per subscriber is long, the system capacity is reduced, and channels cannot be used effectively.

The object of the present invention is to eliminate the above-mentioned conventional drawbacks, and provide a message information receiving function that can receive the minimum amount of data without reducing system capacity, decode it into valid message information, and display it. An object of the present invention is to provide a wireless individual selective calling receiver having the following functions.

According to the present invention, an individually selected paging signal from a transmitting side, a signal specifying a decoding format determined in advance with the transmitting side, and one of the four elements of time, place, name, and instruction. a detecting means for receiving and detecting a message signal configured to include several elements of the above; and a notifying means for notifying that a calling signal has been received in response to the calling signal detected by the detecting means;
means for changing the arrangement of some elements of the detected message signal in accordance with the decoding format designation signal detected by the detection means; and display means for displaying the message with the arrangement of the elements changed by the means. A wireless individual selective calling receiver having a message information receiving function is obtained.

Further, according to the present invention, the wireless individual selective calling receiver described above has a message information receiving function characterized by including means for adding necessary adverbs to the message sentence in which the arrangement of the elements has been changed. A wireless individual selective calling receiver is obtained.

The intention of the present invention is to select the minimum amount of message information that can be received by a wireless selective call receiver so as not to impair the effective use of channels. Another method is to increase the transmission speed in order to shorten the channel occupation time per subscriber by adding message information, but as is clear from the graph in Figure 1, as the transmission speed increases, The required electric field level increases significantly. Therefore, rather than increasing the transmission speed, the best way to obtain an inexpensive system is to reduce the amount of message information to be transmitted to the minimum necessary for efficient channel operation. By the way, for example, when increasing the transmission speed from 300 bit/s to 900 bit/s, it takes 3 dB to obtain the required electric field level, as is clear from the graph in Figure 1.
also requires a transmitter that can produce a large output. If the transmitter output is not changed, the service area will be narrower, and in order to secure the same service area, several times as many transmitters as the base station equipment will be required, making the system expensive. .

In light of the above, the challenge faced by receivers was how to efficiently process, make use of, and decode the minimum amount of information sent from the sender into complete message information on the receiver side. Therefore, in order to achieve this problem, in the present invention, [first, the same coded table as shown in FIG. 2 is defined between the transmitting side (base) and the receiving side. FIG. 2 is a diagram showing an example of a message sentence composed of an arrangement corresponding to the "mode" or "key code" of the received signal applied to the present invention and added adverbs. ] The information sent from the sender is divided into the four elements necessary to compose the message: ``time,''``place,''``name,'' and ``instruction,'' and a signal that specifies the decoding format of the receiver. By adding "mode" or "key code", the receiver receives the specified signal "mode" or "key code" in this decoding format.
In response to the reception of the message, for example, as shown in FIG. 2, the arrangement of the four elements is changed and necessary adverbs are added to decode the complete message.

Next, the individual selective calling receiver according to the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a block diagram showing the configuration of an individual selective calling receiver as an embodiment of the present invention. According to this example, the receiver includes an antenna 10, a receiving section 11, a waveform shaping section 12, a switch circuit 13 for switching the supply of power, a P-ROM 14 in which a calling number etc. are written, and a buffer amplifier 15. , a speaker 16 , a battery 17 ,
A power switch 18, a reset switch 19,
receiving message information with the decoder 20;
CPU30a and ROM30b that control the display
A control unit 30 including a RAM 30c, a character generator 40a, and an LCD driver 40b.
The display unit 40 includes an LCD 40c and a battery 50. The operation of the receiver configured as described above will be explained with reference to the time chart of FIG. 4. Now, in this receiver, the power switch 18 is closed, and the switch circuit 13 intermittently turns the power ON (60 ms) and OFF to the front section with the stroke shown in Figure 4b.
(1500ms) is repeated. In this state, only when the power is on, the received signal as shown in FIG.
The signal is received by the receiving section 11 and provided to the decoder 20 via the waveform shaping section 12.

The decoder 20 includes frequency dividing circuits 201 and 203, as shown in FIG.
, an OSC 202, a preamble signal detection circuit 210, a synchronization signal detection circuit 220, an end signal detection circuit 230, a ringing signal detection circuit 240, and a 1.2 second timer 255 responsive to the detection of a preamble signal. A 12-second timer 258 responsive to detection of a synchronization signal, a clock regeneration circuit 270, a 31-ary counter 273, a 3-ary counter 275, and inverter gates 205, 206, 253, 259, 2
67 and 272 and AND gates 207, 20
8,250,251,256,260,266,
265, 268, 269 and 274, OR gates 254, 257, 264 and 276, and D
Type F/F204, 252, 261, 26
2,263 and 271.
Therefore, the signal given from the waveform shaping section 12 is bit synchronized by the clock regeneration circuit 270 of the decoder 20, and its output is sent to the frequency divider circuit 201.
to the clock frequency necessary to receive the preamble signal, frame synchronization, and address signals. On the other hand, data given to the synchronization circuit 240 composed of a D-type F/F is read here, and its output is sent to the preamble signal detection circuit 240.
0, is input to the synchronization signal detection circuit 220, end signal detection circuit 230, and calling signal detection circuit 240. When the preamble signal detection circuit 210 configured as shown in FIG. 6 detects the pattern "01010101", the gate 2
F/F252 by the output signal of 07 (Fig. 4d)
(FIG. 4e), inhibits gate 207 via gate 206, and gate 20
8 is opened and a control signal (FIG. 4c) is sent to the switch circuit 13 via gates 253 and 254.
At the same time, a timer 255 is activated to generate 1.2 seconds in response to F/F 252, applying power to all receivers regardless of the battery save signal (Figure 4b). If the detection of the signal by the synchronization signal detection circuit 220 configured as shown in FIG.
is reset, and the output signal b of the frequency dividing circuit 203 is
With a stroke of , the signal shifts to intermittent reception due to battery saving.

However, within a second or two, the synchronization signal detection circuit 2
When the detection of the frame synchronization signal is confirmed in step 20,
Set the F/F 261 by the output signal of the gate 208 (FIG. 4 f) and take the necessary and sufficient time (12 seconds in this example) to finish detecting the calling signal.
At the same time, the gate 256 is inhibited via the gate 259, and the timer 258 is started.
Block the output of 55. At the same time, gate 250,
251 and 269 are opened to prepare for receiving a ringing signal and an end signal for returning to battery saving operation. If 12 seconds pass without receiving anything in this state and the timer 258 times out, the signal is sent to the preamble signal detection circuit 210 and the synchronization signal detection circuit 22 via the gate 257.
0, end signal detection circuit 230, F/F 252, 261 and timer 25, which are constructed from the circuit shown in FIG.
5,258 is reset, and the process returns to intermittent reception using the output b of the frequency dividing circuit 203. However, if the calling signal of the machine is inputted before the timer 258 times out, 31 addresses are specified via the gate 269 in response to the clock inputted by the 31-decimal counter 273. The calling number of the own machine is written by the 31-decimal counter 273,
For example, P.
The data in the ROM 14 is read out and inputted to the call signal detection circuit 240, which is constructed from the circuit shown in FIG. As a result, the ringing signals are compared bit by bit, and each time a match is confirmed, the counter 242 is
The second half of the pulse of the 31st bit is applied to the calling signal detection circuit 240 via the gate 268, and the result is read out. In this way, when it is confirmed that the calling signals match, a logic "1" signal passes through the gate 251 to set the F/F 262 to output the signal j, and further passes through the gate 260 to output the signal i. Send it to the sending CPU 30a. However, since the signal from the CPU 30a (FIG. 4k) is logic "0" here, it is blocked by the gate 265 and no sound is produced.

By the way, the function designation information of the receiver is sent to the ternary counter 27 via the gate 274 to the P.ROM 14 in which the presence/absence of the auto-reset function and the code structure information of the signal to be detected are written.
5 and read into the CPU via the input port 304 of FIG. 10 that constitutes the control section 30, the control section 30 is in a standby state according to the read function specification. In this way, the information that the calling number has been detected is sent to the interrupter 308 of the control unit 30 that receives the interrupt signal by the signal i.
When the signal is input to #1, program data is set via the data bus 311 in preparation for the detection of the message signal sent subsequently.

Note that FIG. 10 is a block diagram showing a specific example of the control section 30. In this example, output ports 301-303 and input ports 304-306
, an interrupt port 308 , a serial interface 309 , an input/output port 310 , a data bus 311 , a program counter 312 that specifies the contents of the address, and a sequence of instructions to be executed is stored and specified by the program counter 312 ROM for the program that reads the contents of the specified address
30b, and an instruction decoder 315 that decodes information from the ROM 30b and supplies control signals corresponding to the instructions to each section.
In order to sequentially execute the procedures written in the ROM30b, instructions are sent from the ROM30b.
“+1” each time information is passed to the decoder 315
A program counter 312 that is changed in response to a branch instruction or jump instruction, and an ALU 31 that performs various operations such as arithmetic operations and logical operations.
3, RAM30c used for storing various data, subroutines, program counts for interrupts, and saving program status, and ALU
313 calculation results can be stored, RAM 30
c. ACC 314 used for sending and receiving data between each port 301 to 307, 310; system clock generation circuit 316 that determines execution command cycle time; and count clock generation circuit 317 used as a clock source for various timings. It is composed of:

Now, referring to FIG. 10, the message information (including the mode or key code for specifying the decoding format) synchronized with the clock by the synchronization circuit 271 of the decoder 20 is input to the CPU 30a via the input port 305. be done. A clock signal is also read from the output of clock recovery circuit 270 via input port 306. and,
The ALU 313 performs arithmetic processing according to the procedure written in the ROM 30b in units of 31 bits, and the above 31
Of the information bits in the bits, 21 bits are stored in RAM 30c. In this way, all information bits are sequentially detected. And if,
In the 31-bit unit calculation process in ALU313,
If a predetermined number of errors (2 in this embodiment) or more errors are detected, it is assumed that the message information has not been received, and the message information is sent from the output port 302 to the gate 276.
The F/Fs 262 and 263 are reset via the
However, when all the message information is detected, the F/F 263 is set through the output port 303, and the buffer amplifier 15 causes the speaker 16 to sound through the gates 264 and 266. This notifies the receiver owner that the call has been made, and at the same time, the CPU 30a reads data from the RAM 30c in which the received message information (including the mode or key code) is stored. Then, using the program ROM 30b in which a message structure corresponding to the key code specifying the decoding format is written, the arrangement of the received information is changed to the format shown in FIG. 2 in this case. In this way, the desired complete message information is displayed on the display section 4 via the serial interface 309.
Output to 0.

FIG. 11 is a block diagram showing a specific example of the display section 40. As shown in FIG. According to this example, the display section 40
A serial interface 401 serially connects data to and from the CPU 30a, and a command decoder 402 that takes in and decodes instructions input through the serial interface 409 and controls each part according to the contents of the instructions. , a character generation circuit 403 that generates a 7×5 dot matrix pattern in response to input data, and an address for writing data from the serial interface 401 or reading data to the serial interface 401. A data pointer 404 to be specified, a data memory 405 that stores the output of the character generation circuit 403 or display data from the serial interface 401, and a LOW driver 4 that controls the rows of the LCD.
06, a column driver 407 that controls the columns of the LCD, an LCD voltage controller 408 that controls the supply voltage to the LCD, and an LCD timing controller 40 that controls the drive timing of the LCD.
9 and system clock controller 410
It is composed of:

The operation of the display unit 40 will be explained with reference to FIG. 11. First, the command from the input/output port 310 of the CPU 30a is
01, the command decoder 402 translates the message data, and the message data is sent to the character generation circuit 4.
03, is addressed by a data pointer 404, and input into a data memory 405. At the same time, the ROW driver 406 and the column driver 40 according to the LCD timing controller 409
7 to read the contents of the received message.
Display on LCD 40c. When you want to reset the sound, push the push switch 19. In response to the signal from the decoder 20 and #2 of the interrupter 308 of the external interrupt input terminal, the output is sent to the F/F 262 via the output port 302 and the gate 276. , 263. However, the display will be displayed again while the sound is stopped.
It switches on or disappears only when is pressed or when 8 seconds have elapsed since the start of the display.

As is clear from the above description, according to the present invention, a specific code sent following a selective call signal is detected, and received message information is decoded in a predetermined format corresponding to the code. By doing so, it is possible to effectively display a message with richer content even though the minimum message information is received, and the effect obtained is to improve the service and prevent a decrease in system capacity. is big.

[Brief explanation of drawings]

FIG. 1 is a graph showing the relationship between reception input and transmission rate required to achieve a 10 ^-2 bit error rate, and FIG. 2 is a graph showing the received signal "mode" or "key code" applied to the present invention. 3 is a block diagram showing the configuration of an individual selective calling receiver as an embodiment of the present invention. 4a to 4m are time charts for explaining the operation of each part of the decoder in the embodiment shown in FIG. 3, and FIG.
6 is a block diagram showing a specific example of the configuration of the preamble signal detection circuit in FIG. 5, and FIG. 7 is a block diagram showing a specific example of the synchronization signal detection circuit in FIG. 8 is a diagram showing a specific configuration example of the end signal detection circuit in FIG. 5, and FIG. 9 is a diagram showing a specific configuration example of the calling signal detection circuit in FIG. 5. 10 is a block diagram showing a specific example of the configuration of the control unit 30 in FIG. 3, and FIG. 11 is a block diagram showing a specific example of the configuration of the display unit 40 in FIG. 3. be. In the figure, 10 is an antenna, 11 is a receiving section,
12 is a waveform shaping section, 13 is a switch circuit, 14 is a P-ROM, 15 is a buffer amplifier, 16 is a speaker, 19 is a reset switch, 20 is a decoder, 30 is a control section, 30a is a CPU, 30b is a
ROM, 30c is RAM, 40 is display section, 40a
is a character generator, 40b is a driver, 40c is an LCD, 201 and 203 are frequency dividing circuits,
210 is a preamble signal detection circuit, 220 is a synchronization signal detection circuit, 230 is an end signal detection circuit, 2
40 is a calling signal detection circuit, 255, 258 are timers, 270 is a clock regeneration circuit, 273 is a 31-ary counter, 275 is a 3-ary counter, 204, 25
2,261 to 263,271 are D type F/
F, 301-303 are output ports, 304-30
6 is an input port, 308 is an interrupt port, 31
0 is an input/output port, 312 is a program counter, 313 is an ALU, 315 is an instruction decoder, 401 is a serial interface, 402 is a command decoder, 403 is a character generation circuit, 404 is a data pointer, 405
is data memory, 406 is LOW driver, 40
7 is a column driver.

Claims (1)

[Claims] 1. An individually selected calling signal from a transmitting side, a signal specifying a decoding format determined in advance with the transmitting side, and 4.
a detecting means for receiving and detecting a message signal having a configuration including some of the two elements; a notifying means for notifying that a calling signal has been received in response to the calling signal detected by the detecting means; means for changing the arrangement of some elements of the detected message signal in accordance with the decoding format designation signal detected by the detection means; and display means for displaying the message sentence in which the arrangement of the elements has been changed by the means. What is claimed is: 1. A wireless individual selective calling receiver having a message information receiving function. 2. The radio individual selective calling receiver according to claim 1, characterized in that it includes means for adding necessary adverbs to the message sentence in which the arrangement of the elements has been changed, for receiving message information. Wireless individual selective call receiver with functions.