JPS6192047A - Radio selective call receiver with message receiving function - Google Patents

Abstract

PURPOSE:To give an electronic memory function without connecting an input terminal such as a keyboard or the like neither damaging the portability of a device by entering message data following a preliminarily determined code of a control signal in the receiver in accordance with the code and providing a means which displays data in a preliminarily determined form in case of data read. CONSTITUTION:When a desired radio frequency comes, a reception signal is detected through an antenna 10, a radio part 20, and a waveform shaping circuit 30. If the receiver has a corresponding individual selective call number ID, a voltage is applied continuously to the radio part. When a following frame synchronizing signal SC is detected (DT2), contents of a P-ROM50 where ID of the receiver itself is written and the reception signal are compared and collated with each other. If the coincidence between them is confirmed (DT3), a message signal following the ID signal is processed by a processing part 60 of message data MD. Contents of message data received through a buffer 70 are displayed in a preliminarily determined form on, for example, a liquid crystal display device (LCD)90.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a radio selective calling receiver with a display having a message receiving function.

[Conventional technology]

In recent years, with the development of integrated technology, there has been a remarkable improvement in the functionality of wireless selective calling receivers, from the traditional calling-only receiver to one that can even receive a series of messages consisting of nine numbers, symbols, etc. .

By the way, wireless selective calling receivers are unique in their nature.

It is something that is always carried close to you. Therefore, if you have a display receiver with a large amount of message memory, you can use the receiver's memory as a memo pad (so-called).

It is possible to use an electronic memo pad). However, when using the device in this way, it is not possible to reduce the size of the device by inputting data into the device using a keyboard or the like.

[Purpose of the invention]

The purpose of the present invention is to provide key ? - To provide a wireless selective calling receiver with a display function having a message receiving function equipped with an electronic memo function without connecting an input terminal such as a card to the receiver and without impairing the portability of the device. be.

[Structure of the invention]

According to the invention, at least a frame synchronization signal.

In a paging receiver that receives a paging signal consisting of a selective paging signal, a control signal, and a message signal in this order, subsequent message data is stored in a storage area of the receiver in response to reception of a predetermined pattern of the control signal. remember,
A wireless selective calling receiver with a message receiving function is obtained, which is equipped with means for displaying data in a predetermined format when reading data.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to two drawings.

FIGS. 1 and 3 are block diagrams of a receiver according to the present invention. An overview of the operation of this receiver will be explained using FIGS. 1, 4, and 5.

A state in which power is applied intermittently to ensure efficient operation of the power supply (this operation is generally referred to as battery saving, and hereinafter referred to as ``battery saving'').
When a desired radio frequency arrives while a voltage is being applied at the antenna 10, the radio section 20 . A received signal as shown in (a) of FIG. 5A(1) is detected via the waveform shaping circuit 30. Here, if the receiver has the individual selective calling number (hereinafter referred to as rIDJ) A1'', a preamble signal for BS cancellation (hereinafter referred to as ``rIDJ'') is sent.
P”) is detected by the decoder 40 (DT 1
), BS has been canceled, and! Pressure is continuously applied to the radio section (j). In this way, the subsequent frame synchronization signal (hereinafter referred to as rSCJ) is detected (D
T 2 ) and the programmable read-only memory [:P-ROM:
350 and the received signal, and when a match is confirmed (DT3), the message data (hereinafter referred to as "-") processing section 60 processes the message signal following the ID signal. ) to drive a transmission means (for example, an alarm horn) via the buffer 70,
The content of the message data received by the signal (c) is displayed on a liquid crystal display device [LCD] 90, or the content of the message data received by the signal (g) is
) to output to terminal 5. Here, since a central processing unit (CPU:1) that requires high-speed processing capacity and a dynamic drive type LCD drive usually requires a voltage of 2 or more, a booster circuit 7 that boosts the voltage of the battery 6 is used.
is used.

Now, each component element p, sc of the above-mentioned received signal (,)
.

The ID and criminal details are shown in Figure 4. In the figure,
The preamble signal P is a repeating pattern of logic "1" and "0#" as shown in FIG.
The structure of the individual selective calling number ID is shown in CI) in the same figure: The pattern is a BCH (31, 21) code with an inter-code distance of 5 in which the MSB (identification bit) is logic "0", and the message data offender is The configuration shown in the same figure [l11]
In the pattern, the MSB (identification bit) is given as a logic "1", and the first control signal "T", the second control signal" as shown in FIG.
In other words, the first control signal shown in [■] in FIG.
) Code zO as message information, which is 11 when there is a message addressed to own machine, and “0” when there is no message,
(ii) Information specifying the format of the following message (for example, "001" if the message is numeric information composed of BCD code, "010" if the message is compatible with ASCII code, "100" if it is compatible with JIS code)
, or if it is facsimile information, the code Z1 as "'111", etc.), and (iii) As shown in Figure 5A (1), specify the time from the first control signal to the next 5C1T or H is derived from the BCD code code -z5, which represents the number of words when 31 bits are one word, as duration information. The second control signal shown in [■] in FIG. 4 is a signal "MC3" for specifying the processing of the received message and a signal "TS" representing the time or date information. configured.

Item 1 means that no processing is performed on the received message. Items 2 and 3 indicate setting the ID corresponding to the received message as the ID of the device itself, or conversely changing the ID registered in the device itself.

Item 4 sets the built-in clock to the time corresponding to the received message and sounds a call alarm. Item 5 secures a memory area of the message memory area according to the ID and byte information corresponding to the received message. Item 6 is that the receiver receives the time from the start of the BS to the detection of the SC as a message signal, and if the SC cannot be detected within the said time, it must be sent by some means (for example, by sounding an alarm horn with a different sound than the normal ringing tone). (make a sound) to warn you.

Items 7 and 9 arrange and output the contents of the received message according to a predetermined format (see Table 51 and Table 6). Item 8 processes the TS in FIG. 4 [V] as month/day information. Nao T
S usually represents time information, and the code structure in each case is shown in Table 2. Next, Figure 4 [VDπ's turn is Figure 5 A C? ) corresponds to signal E in signal (,) and is used as an end signal.

Now, the decoder 40 in FIGS. 1 and 3 is.

As shown in FIG. 6, the SC detection circuit inputs the received signal into the shift register 500 in series with a clock, thereby determining whether or not the read 31 pins are a predetermined desired no-turn. That is, if it is a desired pattern, a match signal is output from the AND GO (AND GO) 540. In addition, as shown in FIG. 7, the ID detection circuit receives the received signal (a) and the signal (e) from the P-ROM 50 in which the calling number of the own device is written in advance.
The data is inputted to R610, checked bit by bit, and the matching output is inputted to counter 600. As a result, the own device is called by the detection nosorus that is output when the number of matching inputs reaches a preset value.

Next, the buffer 70 is provided with a circuit configuration using transistors, for example, as shown in FIG.

As seen in FIG. 2, the message processing section 60 includes 1
Chip CPU (message, -no decoder) 100° Random access memory (RA!vi) 300
, and an LCD driver 200. Among these, the RAM 300 can protect data even when the battery is replaced by a backup circuit composed of a diode 61 and a large-capacity capacitor 63. 1 in the message processing section 60 in FIGS. 1 and 3.
The structure of the chip CPU 100 is shown in FIGS. 9 and 11. The decoder 8 in FIG. 3 is provided by a one-chip CPU shown in FIG. 10, and the functions of each block are as follows.

In these figures, 102-106, 119-121
101, 110 to 118, 122 are output ports), 107 is an interrupt port.

108 is a serial interface, 120 is a data bus, 130 is a program counter that indicates the contents of an address, 1
40 is a program memory in which a sequence of instructions to be executed is stored and from which the contents of the address specified by the program counter 130 are read.

160 is an instruction decoder that decodes information from the program memory 140 and supplies control signals corresponding to the instructions to each section; 150 is an ALU (ALU) that performs various operations such as arithmetic operations and logical operations;
c and Logic Unit) + 180 is used to store various data, save program counts and program status in subroutines and interrupts, and store the calculation results of ALU 150, and save data between each point of RAM l 80. ACC (Accumulator) used for sending and receiving
Reference numeral 190 denotes a system clock generation circuit that determines the execution instruction cycle time.

Next, the LCD driver 200 is given in the block configuration shown in FIG. 290 is a character generation circuit that generates a 5×7 dot matrix pattern in response to input data; 28;
0 is a data pointer that specifies the address for writing data from the serial interface 295 or reading data to the serial interface 295; 2;
50 is a data memory that stores the output of the character generation circuit 290 or display data from the serial interface 295; 220 is a row driver that controls the rows of the LCD; 210 is a column driver that controls the LCD0 column; 230
240 is the LCD that controls the voltage to the LCD [pressure controller; 240 is the LCD that controls the drive timing of the LCD]
260 is a timing controller, and 260 is a system clock controller.

Furthermore, the RAM 300 is given in the block configuration shown in FIG.
20 is an address counter, 330 is address counter 3
20 is an X-Y decoder for specifying the address of the memory array 340 and writing or reading data in the memory, 340 is a memory array, and 350 is a control circuit.

FIG. 14 shows an example of the configuration of the switching circuit 1, and FIG. 15 shows the data configuration of the output signal (g>) to the external terminal 5.

There are 11 bits per character. FIG. 16 is an example of 30 level shift circuits. FIG. 17 is an example of the key arrangement of the data input section.

The operation of the receiver in each case will be explained below.

8) When the desired signal is received after the power is turned on.
Among the receivers in the BS state as shown in (I), I
When D corresponds to A1 and detects SC following reception of P, it decodes the subsequent signal T1.

At this time, since the message data Ml follows, ZO is logical Klj, and the period represented by "Set Z2 to Z5 (DBCD code)" (at least to the next SC%, usually further up to A2.I2), the BS is It is canceled (OFF).

Furthermore, when decoding 1, "MCS" is 1 as CS-ton.
When receiving 000111', it decodes Ml's message data with the code corresponding to 21.

Store in RAM 300 and LCD driver 20
0 on the LCD 90 and drive the transmission means 80 via the decoder 40° buffer 70.

Notify the device owner that you have been called. Also, calibrate the built-in calendar using the month and day information from the TS'A turn in Step 1.

Then, the primary SC, ID, T2, and I2 are detected and decoded. At this time, SC is detected, but ID
Since the signal is A2, it is not detected, so the detection pulse DT3 is not output. Therefore, Z2 to z5 of I2 and MC3' of Engineering 2
, Looking only at the ``TS'' nozo turn, after detecting the I2 signal, turn on the BS (until before the normal SC) for the period indicated by 22 to Z5, and set ``MC3'' to 100.
When the value is other than 0111, the built-in clock is calibrated to the time corresponding to the "TS" pattern, and the reception time is added to the received and stored message. In this way, at the second 800 hours, the BS is turned off again. This period is defined as the period up to I3 since the ID is different from A3 and the built-in clock has already been calibrated. Thereafter, such operations are repeated, and when the end signal E indicating the end of data is detected, 2 normal B
Return to S operation.

In addition, the receiver whose ID corresponds to A3 detects SC after receiving P, but since the ID does not match at A1, TI's 22 to z5 and "TS" of T1 are detected.
Just look at the pattern. Then, after detecting the signal of work 1, 22~Z
The BS is turned ON for the period indicated by 5, and the built-in calendar is calibrated on the month and day corresponding to the 4' turn of "TS". In this way, when the time for the next SC comes, the BS is turned off again for the period up to Step 2, and the SC is detected but the ID is not detected, so Z2 to Z5 of I2 and °' MCS of Step 2 are detected.
”, ”Watch only the glossy turn of TS.After detection of 2nd operation, turn on BS for a period of 22 to z5, and
When "MC3" is other than 1000111, "'TS" (calibrates the internal clock at the time corresponding to the turn.Of course, "MC3" is calibrated at the time corresponding to the turn.
3' When the turn is 1000111, calibrate the built-in calendar with the month and day information that corresponds to the TS pattern.In this way, when the time for the second SC comes, the BS is turned off again.
Therefore, the SC detection operation is performed.

Then, when SC and ID are detected, Z in I3
As the BS OFF state continues for periods 2 to Z5.

The time corresponding to M3 decoded with the code "MC3'highny>;10000114.cRubberZ11c"dresponse-j is stored. When the built-in clock reaches the predetermined time, the decoder 40. The transmitting means 80 is driven via the buffer 70, and a message indicating a set alarm is displayed on the LCD 90 (FIG. 18 is an example of this).

Also, the built-in clock is calibrated again using the time information corresponding to "TS" of I3. Thereafter, when there is no ID corresponding to A3 and the end signal E is received, normal BS operation is resumed.

By the way, in this embodiment, if the end signal E is not received (as long as 3c is received or not, the terminal goes to check the signal T, and if this signal cannot be received correctly, it waits for a predetermined period of time). (About 1 minute in this embodiment) The BS is forcibly turned off, the SC signal is received, and if it cannot be detected, the normal BS operation is resumed.

Furthermore, if SC is not detected two or more times in a row, it is determined that there is a field failure and the system returns to normal BS operation, thereby making effective use of the battery and increasing the reliability of reception.

The receiver whose ID is AN is turned on and the BS is turned off continuously for a predetermined period of time (approximately 1 minute in this embodiment) to detect the desired SC signal. When the SC signal is detected in this way, the ID is detected, but it is not received, so after I2 is detected, the built-in calendar or clock is set to "TS" according to the "MC8" pattern.
The information is calibrated and the BS is turned on during the period from 22 to Z5 of T2. Then, during the 1st SC, the BS is turned off again.
Repeat the action. In this way, I corresponding to AN
When D is received, the BS is turned off for the period of TN(7) Z2 to Z5, and the IN "MC3" pattern becomes 1000.
If it is 101, the Messeno data engraving is decoded with the code corresponding to 21 of TN and stored.

As a result, if the SC is not detected before returning to BS operation and checking the elapse of time corresponding to the received data using the built-in clock, a restart will be made by returning to a good service area BS. ), the BS is forcibly turned off for a predetermined period of time (approximately 1 minute in this example), and the SC is turned off.
If SC is not detected within the certain period of time, B
The operation of returning to the S operation will be repeated.

C) Registration/reading by manual input of fixed form information Select the desired key from the mode SW of the data input section 2 (However, if you select the "CAL" or "TIME" key, the LCD 90 will work with the CPU and start the computer. function or clock function). If the "Place" key is pressed here, an interrupt is applied from the terminal of the interrupt port 107 in FIG. 9, and a pattern corresponding to the "Place" key is input from the input port 102.

As a result, the CPU recognizes that the device is set to the 'position' mode, and from now on, data from the input port 103, such as 'DATA IN', 'AOKI', 'DA
TA IN”.

"NEC", 'DATAIN', "03-262-51
74” “DATAIN”, “KUDO”, 'D
ATA IN'', ``5ONY'', etc. are input. When the result of key input is confirmed in this way, it is read out according to the predetermined format (see Table 5), and the ``DATA OUT'' key is first pressed. When pressed, “AOKI” changes to L.
When it is displayed on the CD and press the ``→'' key, 'NEC''
However, if you press the “→” key again, the message will be 03-262-5174”
.

Furthermore, press the ``→'' key to select ``KUDO,'' press the ↓ key to select ENDO, and press the ``→'' key to select KDD', ``'
↑ You can check by pressing the ``5ONY'' key.

Similarly, pressing the "MEMO" key will cause an interrupt to be lost from the interrupt port 107 terminal in FIG.

Corresponding to the "MEMO" key from the input port 102/,
.

Turn “0010011” is input. This result CP
U determines that the device is set to MEMO'' mode, and the following data input from the input port 103
DATA IN”, 'FEB, l O, 1984
SCHEDULE', ``DATA IN''
, "9:00""DATAIN'
.

“' MEETING (NEW PRODUCT)
AT S-1”, “DATA IN”.

To read "10:30',..." DATA
When you press the ``OUT'' key, ``FEB, 10゜19845CHEDULE'' is displayed on the LCD 90 as shown in Table 6, and when you press the ``→'' key, the LCD display shows 9:00''.
If you press the ° “→” key again, the display will change to “MEET”.
ING (Ntsu PRODTjCT) AT 5-1”
, press the ``↓'' key again to select ``Place (NTT MRKU
DO)”, and you can check the necessary information at any time with a simple operation instead of taking notes.

In addition, this receiver has a built-in calendar and a built-in clock (so it is "9:00" on "FEB, 10").
.

At the date and time of "10 230", etc., the receiver's transmission device (for example, an alarm horn) is activated to arouse attention, and the LCD 90 displays the alarm at the time of the sound. For example, if it is 18:00, GINZA (
MORE)” is displayed on the LCD.

d) By radio. Registering information The operation of the receiver will be explained using FIGS. 1, 9, 12, and 13. A radio section 20 of a receiver performing BS operation with the switching circuit 1. When a preamble signal P is received while a voltage is being applied to the waveform shaping circuit 30, the BS is turned off for a period sufficient to detect a subsequent predetermined synchronization signal SC. If SC is detected during this period, the 1-chip CPU 100 is activated via the interrupt port 107 using the detection pulse DT2, and the decoder 40 shifts to the ID detection operation. That is, S
Starting from the detection of C, the data in the P-ROM 50 in which the ID number of the machine itself is written is compared bit by bit with the received data (FIG. 7), and when a match is confirmed.

The detection pulse DT3 is input to the 1-chip CPU 100 via the input port 121, and the clock CL corresponding to the transmission speed is input, t? -) 105. At this time, D
When T3 is input, it is determined that the ID has been detected, and if not, it is determined that the ID does not match, and preparations are made for reception of the subsequent signal. As a result, the 1-chip CPU 100 reads the message signal from the input port 106 using the clock CL, translates the predetermined contents of the program memory 140 using the instruction decoder 160, and processes the messages in accordance with each instruction. That is, the read signal is transmitted through the data bus 120 and the ACC 170.
Written to M 180. Thus BCH(31, 2
1) Each time the 31 bits forming the code are input, the ALU
A calculation is performed at 150 to decode the store reception signal.

The 1-step CPU 100 reads the decoded first BCH (
31, 21) Decode the 20 information bits of the code according to Fig. 4 [■], and from then on output port 1
12 to control the BS operation of the receiver. At this time,
If the 20 bits of information are the next number or turn, rl 10100000000000100000 J
The call is with a message, and the message data is 7.
This indicates that it is necessary to release the BS for at least 20 words (here, 1 word is 31 bits). Then, it waits for the input of the first 31 bits and performs signal decoding.

In this way, the 20-bit information area is shown in Figure 4 [■].

Analyze according to Tables 1 and 2. That is, if the information bit has the following pattern, r 1100011001
01000100000 J Indicates that the subsequent message data will be processed in the telephone directory mode, and indicates that the data transmission time is 7 AM 10:20 minutes. According to the control contents decoded in this way.

Subsequent messages will be processed.

Therefore, the information area (20 bits of data) decoded every 31 bits is decoded in units of 7 pits and sequentially stored in the external RAM 300. In other words, by setting the chip select to logic "0" level, the RAM 300
is set to the operation mode, and the corresponding address information is transferred via the 7 real interface 108 using the signal 11so to determine which address in the RAM 300 to write to. At this time, 1
The chip CPU 100 sets the system clock to R1u'v.
At the same time as sending with i300K SCK, the signal line φ is set to logic "1" level to indicate that it is an address.

At this time, in FIG. 13, the RAM 300 determines that the signal input from the signal line SO is an address signal in accordance with the input side-down signals (C3, A/D, -Q), and the address counter 320 , X-Y decoder 3
30, the address of memory array 340 to be written is designated.

Next, the 1-chip CPU 100 transfers the message data to be written to the signal line S of the serial interface 108.
At the same time, signal B A/D is set to logic "'0" level to indicate that the sent data is message data, and signal line R/W is set to logic "'0" level to instruct writing.
0” level. As a result, the RAM 300 in FIG.
corresponds to each input control signal, and converts the data input via the signal line So into message data X-Y
It is written to the address specified earlier in memory array 340 via decoder 330.

When message data is sequentially decoded in the above process, S
The 11-chip CPU 100 outputs a message when C or an end code is detected, or when two consecutive words cannot be received.

It is determined that the sage data has ended, and the output port 11
0 informs the decoder 40 through the signal line ME that the message has been completed, and also drives the sound generating circuit of the decoder 40 with the signal line AC through the output port 111. As a result, the alarm horn 80 sounds via the signal (d) via the buffer 70.

Here, in the case of SC detection, the 1-chip CPU 100 repeats the same operation as described above, but when the end code is received or when two consecutive words are not received, the receiver returns to the BS operation. As described above, a code corresponding to the desired content is input to the receiver as a normal message.

Next, to read out the data received and stored in this way, by pressing the read switch S1, the CPU 100 supplies the first address information of the corresponding message data to the RAM 300 from the signal line SO. At the same time, the chip enable signal line -■ is set to logic "0" level, and the chip select signal line C32 (this is a signal line for selecting the LCD driver 200) and the signal line φ
is set to the logic °'1" level. Next, the signal line ω is set to the logic "0" level.
``level'' and the signal lines 1 to 2 are set to the logic ``1'' level.

As a result, data corresponding to the above-mentioned first address is sequentially read out from the memory array 340 via the X-Y decoder 330 one byte at a time, and the data is transferred to one chip via the serial interface 310 on the signal line SI. It is supplied to the CPU 100.

When the data is thus read from the RAM 300 and supplied to the 1-chip CPU 100, the signal a and the signal line C are set to logic "1" level.

By setting the chip select signal line to logic "0" level to select the LCD driver 200, character conversion instructions and storage address information are supplied to the LCD driver 200 from the signal line SO.

The one-chip CPU 100 sets the signal line C/D to the logic "0" level and supplies the data read from the RAM 300 to the LCD driver 200 via the signal line So.

As a result, in the LCD driver 200 shown in FIG.
When the signal line C/I is at the logic "1#" level, the information serial-parallel-converted by the 7 real interface circuit 295 is decoded by the command decoder 270, and the command decoder 270 generates an internal control signal. Here, the command is a write command and a character conversion command.

Data pointer 280 to set the write address
is accessed, and when the signal line C/l) reaches a logic level of 1107, the data input via the digital interface 295 is converted into a 5x7 dot matrix pattern by the character generation circuit 290, and is stored in the data memory. 250 and the column driver 210 under the control of the LCD timing controller 240.
and LCD 90 with signal C via row driver 220
displayed above.

e) Registration/Change of Common ID The operation of the receiver will be explained using FIGS. 3, 10, and 11. FIG. 3 shows the decoder 40. The configuration between the message processing section 60 (1 chip, the configuration example of the CPU 100 is shown in FIG. 11) is partially changed, and especially the common 'I'
Decoder 8 (in this example, 1
It uses a chip CPU, the configuration of which is shown in FIG.

Now, the radio section 20 of the receiver that performs BS operation in the switching circuit 1. When a preamble signal P is received while a voltage is being applied to the waveform shaping circuit 30, a period f sufficient to detect a subsequent predetermined synchronization signal SC is generated.
Stop 3S operation. If an SC is detected during this period, the 1-chip CPU 100 and the decoder 8 are activated via the interrupt port 107 at the detection 7F pulse DT2, and the decoder 40 writes the individual selective call number of the own machine using the detection of the SC as a starting point. P-ROM 50
and the received data are compared bit by bit.

In this way, if the received data matches the individual calling number of the own machine in the P-ROM 50, the process shown in FIG.

The detection signal DT3 is input from the input port 121. As a result, the CPU activated by SC detection pulse DT2
determines that the input is from the input port 121 rather than the input port 119 at the time when the ID should be detected, recognizes that the detected ID is an individual selection call number, and prepares to receive the message signal sent subsequently. In other words, 1 chip CPU
100 reads the signal following the ID from the input port 106 using the clock CL and reads the signal from the data bus 120 . Write to RAM l 8Q via accumulator ACC170. 3 thus forming the BCH(31,21) code
Every time one bit of data is input, the ALU 150 performs an operation.

Decodes the received signal. Of the 31 decoded bits, 20 information bits are decoded according to FIG.
Controls S operation. At this time, if the 20 information bits are as follows: r 1101
00000000000110010J.

Indicates that the call is followed by a message signal consisting of a 7-bit code, and a 32-word BS
Indicates that it is necessary to cancel the operation.

That is, one chip CPU IQ decodes 32 word ties. The 20-bit information area thus obtained is analyzed according to Tables 1 and 2 in FIG. 4 [■]1. In other words, if the information pit is the following ノ or turn, r 110000011001000110110
J.

Some of the subsequent message data is registered as a common ID, which means that the current time is 2:36 PM.

Therefore, the built-in clock of the 1-chip CPU 100 is calibrated, and the subsequent message data is decoded every 31 bits, of which 20 bits are decoded into 7-bit units. Here, if the pattern of the information area of the received message 020 bits is as follows, use Table 1.

Jshi-EJ■--, (" SONY brand, IDrollol...0IIOIIJ
is registered, but 1 chip cpυ100 is RAM 3
A label of 5ONY is attached to the alternating box of the common ID area of 00, and the corresponding number and ID pattern of the ID area are transferred to the decoder 8.

That is, the chip select) C34 is set to logic "0" level, and the common ID area number (for example, 0110=6) and ■DA are output from the serial output SO along with the system clock SCK.
Turn r01101...0IIOIIJ is output.

At this time, the decoder 8 detects that the chip enable CE is logic “
0# What's going on? Prepare for reception, and register the data input with the subsequent system clock as the 6th ID in the RAM 180 from the 7 real input SI via the serial interface 108° data bus 120. .

fc, if the pattern of the received signalman's information pit is as follows, 1110000100101
000110000J, the common ID changed to the subsequent message data is missing, and the time of sending is AMll:
It means 30. If the JP pattern of the 20-bit information area of the received message is as follows, then the 1 chip f CPU 100 in FIG.
5 10 Is
20L-5-Yo Find the area corresponding to the label TDK in the common ID area of RAM 300, change it from TDK to NEC, and then.

Deselect plane 1- from 7 real output SO with logic °゛0''0'' level system clock SCK
IJ 7 number and 1D pattern "011010...all
l' is output. As a result, the input data is written in the area corresponding to the ID number in the RAM of the decoder 8.

In this way, when detection of the SC is confirmed with the common ID registered in the decoder 8, the decoder 8 is supplied with the clock CL corresponding to the transmission speed from the input port 105 in FIG. Data D following
is read from the input port 106, the predetermined contents of the program memory 140 are translated by the instruction decoder 160, and processed in accordance with each instruction. That is,
The above-mentioned read data is compared bit by bit with the common ID (if there is more than one) registered in advance in the RAM 180 in the ALU 150 via the data bus 120. Then, if a match with the common ID is confirmed, data detection information DI is sent from the output port 113 to one chip 76CPTJ 100 (11th
At the same time, the information DE indicating the number of the detected ID in the common ID area is transmitted from the output port 114 to
It is output to the chip CPU 100.

The l-step CPU 100 recognizes that the common ID has been received by a signal from the input port 119 during a certain period from the interrupt activation required by the SC detection pulse DT2 to the ID detection, and then outputs the subsequent common ID area information. is read from the input boat 120.

In order to store the message data received as a result in the RAM 300, the chip select C81 is set to a logic "0" label, and the address information corresponding to the data from the input port 120 is transferred from the signal aSO via the serial interface 108. At this time, 1 chip CPU I
OO sets the signal line φ to the logic "1" level in order to specify that the system clock is sent at 100 and at the same time, the address is set at 0.

In this way, address setting of RAM 300 is completed.

The received message data is written with the A/D set to the logic 60'' level from the signal line SO to the designated address area of the RAM 300.

Also, when outputting the received message data to the outside, set the chip select number to logic ``0''.

The configuration of one character is output from the output port 122 to the level shift circuit 3 in the format shown in FIG.

Here, by using a signal processing unit connectable to the external terminal 5 of the receiver, it is possible to apply desired processing to data received via wireless.

Here, the receiver has 1 individual selective calling number and common I as ID.
D, it is conceivable that each of the RAMs 3 Q and 3 has separate message storage areas. And if you want to change the distribution of that area.

It can be set arbitrarily using the signalman's MC3/4 turn and message data.

1 = As explained above, according to the present invention, at least a frame synchronization signal 2 is composed of a selection call signal, a control signal, and a message signal in this order. In the calling signal, the following message data is recorded in the receiver in response to reception of a predetermined code of the control signal, and by providing means for displaying the message data in a predetermined format when reading the data, the keyboard It is possible to provide an electronic memory function without connecting an input terminal such as a receiver to a receiver, and without impairing the portability of the device, which has a significant operational effect.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a wireless selective calling receiver with display;
FIG. 2 is a block diagram of the message data processing unit 60, FIG. 3 is a second block diagram of the wireless selective calling receiver with display, and FIG. 4 is a signal purchasing diagram, where [I] is the front Placement signal/P turn, [n] is the same (E'+ No." l-n, [
■] is address signal and mail. The configuration pattern of the control signal, [■] is the configuration pattern of the first control signal, [■] is the configuration pattern of the second control signal, [:Vl] is the P turn of the end signal. FIG. 5A(1) and FIG. 5A(It) together show a time chart in normal operation. FIG. 5B is a diagram showing a time chart of the operation when the power is turned on after the preamble signal, and FIG. 6 is a block diagram showing the synchronization signal and end signal detection circuit.
FIG. 7 is a block diagram showing the address detection circuit, FIG. 8 is a circuit configuration diagram of the buffer 70, and FIG. 9 is a block diagram showing the address detection circuit.
Block configuration diagram of U 100, Figure 10 is a 1-chip CP
Block configuration diagram of U8. FIG. 11 shows the l-tick 7 in the message processing section 60 of FIG.
'CPU IOO professional configuration diagram, Figure 12 is L
FIG. 13 is a block diagram of the CD driver 200, FIG. 13 is a block diagram of the external RAM 300, FIG. 14 is a block diagram of the switching circuit 1, and FIG. 15 is a diagram showing the output data format of the data input section 2. . FIG. 16 is a block diagram of the level shift circuit 3, FIG. 17 is a diagram showing the key arrangement of the data input section 2, FIG. 18 is a diagram showing an example of a display indicating a setting alarm, and FIG. 19 is a diagram showing the battery As an example of saving, it is a diagram showing that the battery is turned on in the time slot (G7) of the group to which the own aircraft belongs. Explanation of symbols: 1 is a switching circuit, 2 is a data input section, 3 is a level software, 6 is a battery, 7 is a booster circuit, 8 is a decoder, 10 is an antenna, 20 is a radio section, 30 is a waveform shaping circuit, 40 is a decoder. 50 is a P-ROM, and 60 is a messeno data processing section. 61 and 62 are diodes, 63 and 64 are capacitors, 70 is a buffer, 80 is an alarm horn (transmission means), 90 is an LCD, 100 is a 1-chip CPU (
message decoder), 101, 110-118 are output ports, 102-106, 119 are input ports 1-, 10
7 is an interrupt port, 108 is a serial interface,
120 is a data bus. 130 is a program counter, 140 is a program memory, 150 is an ALU, 160 is an instruction decoder, 170 is an ACC, and 180 is a code. 190 is a system clock generation circuit, 200 is an LCD
210 is a column driver, 22° is a row driver, 230 is an LCD pressure controller, 2
40 is an LCD timing controller. 250 is a data memory, 260 is a system clock controller, and 270 is a command decoder. 280 is a data pointer, 290 is a character generation circuit, 295 is a serial interface, 300 is an external R
AM, 310 is a serial interface. 320 is an address counter, 330 is an X-Y decoder,
340 is a memory array, 350i is a control circuit, 500 is
is a shift register, 510-530 are inverters, 54
0 is AND gate, 600 is counter, 610 is EX
NORF"-to, 710-720 are resistors, 730 is NP
N) Ranji nut, 74o is PNP) Ranjistor, 8
00 is alarm pawn, la is PNP) transistor,
lb and 3c are NPN transistors, respectively. (Figure 2, Figure 3, Figure 4 o)
-------1f Sekiyu Figure 5 A (I) Figure 5 A (II) Figure 13 Suburban Figure 14

Claims (1)

[Claims] 1. In a receiver that receives a calling signal consisting of at least a synchronization signal, a selective calling signal, a control signal, and a message signal, in response to reception of a predetermined pattern of the control signal. A wireless selective calling receiver with a message receiving function, characterized in that it has means for displaying the message signal in a predetermined format. 2. The receiver according to claim 1, characterized in that it has means for storing the received message in a predetermined format in response to reception of the pattern. Call receiver. 3. A radio selective calling receiver with a message receiving function, in which a message can be entered by inputting keys attached to the receiver body in the receiver according to claims 1 and 2. .