JP2928806B2 - Selective calling method - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a selective call system.

[Prior art and its problems] In a conventional selective paging communication system, for example, a selective paging communication system using a POCSAG code for a paging signal, a paging receiver is divided into eight groups and a paging signal transmitted from a radio base station is also reduced. The paging receiver is time-divisionally transmitted in eight frames in accordance with the grouping, and each paging receiver receives a call only at a timing related to a frame corresponding to the group to which the paging receiver belongs (ie, receives a call in time division), and Because of the battery life, the power is turned off at timings related to other frames in which the paging receiver is not likely to be called.

By the way, in recent years, information providing companies that provide stock price information, gold market information, and the like by using the selective call communication method have been being established one after another. In this case, as described above,
In the conventional POSAG call, since the paging receivers of the subscribers who receive the information are generally dispersed in each frame, the information provider calls at each of the eight frames and performs the call for each frame. In this case, the same information transmission must be performed, resulting in extremely low transmission efficiency.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and to improve transmission efficiency without processing a transmission signal format when calling a large number of receivers represented by a paging receiver. It is an object of the present invention to provide a selective calling system capable of performing the following.

[Summary of the Invention] According to the present invention, a base station transmits an individual call signal of each receiver in a frame corresponding to a group to which the receiver belongs,
A paging signal for simultaneously calling a plurality of receivers is transmitted in a frame adjacent to a signal for synchronizing, and the receiver substantially belongs to a group to which the own device belongs among a plurality of frames transmitted from the base station. The point is to perform reception for detecting a call signal only in a corresponding frame and / or a frame adjacent to the signal for achieving the synchronization.

EXAMPLES Hereinafter, the present invention will be specifically described based on an example shown in the drawings.

First, a transmission signal format of a POCSAG code signal used in the present embodiment will be described with reference to FIG. FIG. 1A shows the overall format, and the transmission signal is composed of a preamble signal A and a plurality of batches B, C,. The preamble signal A is for synchronizing bits between the transmission signal and the receiver, and is “1” of “1010101...”.
And 576 bits in a repeating pattern of "0". FIG. 4B shows the format of each batch, which is composed of a synchronization code SC and eight frames from first to eighth, and one frame is composed of two codewords. Each of the synchronization code SC and one code word has a 32-bit configuration, and the code word is divided into an address code word indicating a calling number and a message code word indicating a message. FIG. 3C shows an address code word, and FIG. 3D shows a message code word. The address code word is a message flag for distinguishing whether the first bit is an address code word or a message code word. In the case of an address code word, this bit is “0”. The 2nd to 19th bits are address bits representing address data, the 20th and 21st bits are function bits indicating a display form and a sound form, the 22nd to 31st bits are BCH parity bits, and the 32nd bit is an even parity bit. . In the message code word, the first bit is set to “1” indicating a message code word with a message flag, the 2nd to 21st bits are message bits representing message data, the 22nd to 31st bits are BCH parity bits, 32 bits are even parity bits. In the synchronization code word SC, 32 bits have a specific pattern.

The above-mentioned signal is a signal of a method of selectively calling the paging receiver according to the address data of the address code word and the order of the frame for transmitting the address code word. Therefore, each paging receiver has:
One address and one frame are allocated to receive an individual call. Note that two addresses may be assigned as needed. In this case, one address is used for a normal individual call and the other address is a simultaneous call for an emergency call or a group of several paging receivers, including the receiver to which the same frame is assigned. Used for calling. Further, an address and a frame for receiving the information providing service are further allocated to the paging receiver subscribed to the information providing service, separately from the address and the frame for receiving the individual call. It is desirable that the frames for receiving the information providing service be the same frame even if the types of information to be provided are many. More preferably, the frame for receiving the information providing service is a frame adjacent to the synchronization code transmission timing, that is, the first frame.
Or the eighth frame. In this selective call communication method, a large number of paging receivers subscribed to the information providing service can be called at a time to provide information. Also, in the paging receiver, even if a contract for receiving a large number of information providing services is made, the battery can be saved because only one frame is provided for receiving the information providing service. When sending a message, the address code word is prepended and then
Only the required length of the message code word is sent.
Transmission is performed at a transmission speed of 62.5 ms per word (hereinafter referred to as one word time). To reduce reception errors on the receiver side, the same contents (address and message) are transmitted for a predetermined time. Later, for example, after 60 seconds, it is retransmitted.

FIG. 2 is a block diagram showing a system configuration of a base station in the wireless paging system. Touch phone 1
The personal computer 2 with a communication function is an input terminal for a general individual to input a call number of the paging receiver and a message to the paging receiver. These are connected via a public telephone line 3 to a control center 4 of a base station. An information provider 5 that provides various information to the owner of the paging receiver is connected to the control center 4 via a dedicated line. The control center 4 includes an input / output circuit 6 having a built-in modem and response circuit at a connection portion between the public telephone line 3 and the dedicated line. The calling number of the paging receiver input by the general individual from the touch phone 1 or the personal computer 2 is input to the collating circuit 7 via the public telephone line 3 and the input / output circuit 6. The call number for information provision inputted from the information provider is inputted to the matching circuit 7 via the dedicated line and the input / output circuit 6. The collation circuit 7 collates the input call number with the call number stored in the subscriber memory 8. The call numbers stored in the subscriber memory 8 include a call number for individual call assigned to each paging receiver, and information provision assigned to each information provider or each information type provided by the information provider. There is a calling number for. When the call number for providing this information is expanded to address data and frame data,
A call number having the same frame data, for example, a call number having the frame data “8” is assigned. If the input call number does not match any of the call numbers stored in the subscriber memory 8 in the collation processing in the collation circuit 7, a command is given to the response circuit in the input / output circuit 6. Then, a message to the effect that the input call number is not registered is transmitted to the caller. On the other hand, when the input call number matches the call number stored in the subscriber memory 8, the collation circuit 7 sends the coincidence-detected call number to the signal processing circuit 9 and the coincidence is detected. Different commands are sent to the input / output circuit 6 and the signal processing circuit 9 based on the call number. For example, if the call number detected to be a match is the call number assigned to the tone-only type paging receiver, the call to the input / output circuit 6 is started, such as "Start calling. Hang up the phone and wait." An instruction to send a message to a caller is given, and an instruction to send a call signal is given to signal processing circuit 9. If the detected call number is the call number assigned to the display type paging receiver, a command to send a message such as "Please input a message" to the input / output circuit 6 to the caller. And the signal processing circuit 9
Gives an instruction to process message data input later from the caller. If the detected call number is a call number for providing information, a message or signal indicating that a message (information to be provided) may be input to the input / output circuit 6 is provided by the information providing company. To the signal processing circuit 9 and an instruction to process the message data input later from the information provider.

The signal processing circuit 9 expands the calling number from the matching circuit 7 into address data and frame data, and creates an address code word corresponding to the address data. Also, a message code word corresponding to the message data input from the information providing company or the like is created. If the message data cannot be stored in one message codeword, a plurality of message codewords are created. The address code word is transmitted to the transmitter 10 at any frame timing of the batch format shown in FIG. 1B based on the frame data, and the message code word is continuously transmitted to the transmitter 10 following the address code word. Sent to 10. The transmitter 10 sends the address code word and the message code word sent from the signal processing circuit 9 from the antenna 11 as a wireless signal.

FIG. 3 shows a circuit configuration of an embodiment of the paging receiver used in the selective call communication system. That is, other circuit sections are connected to the CPU 21 as a center. The CPU 21 controls each circuit unit according to a program in a built-in ROM. 22 is an antenna, 23
Is a receiving unit for demodulating the radio wave received by the antenna 22. The ID-ROM 25 stores the frame and address data assigned to the receiver, and sends the stored frame data and the like to the decoder unit 24 under the control of the decoder unit 24. The decoder unit 24 the received signal demodulated by the receiver 23 decodes based on data from the ID-ROM 25, a circuit section which rule the switch SW ₂ on and off and sends it to the CPU 21. The switch SW ₂ is turned on / off by the decoder unit 24, and is supplied from the power supply 26 via the switch SW ₁ to the receiving unit 2.
Intermittent power supply provided to 3. Switch SW ₁ is a manual switch which is turned on and off by the user's operation, intermittently supplying power to the decoder unit 24 or the like from the power source 26. The message memory 27 is a memory in which a memory area is divided into a plurality of sections, and stores received messages in different memory areas according to the type of the message. The switch circuit 28 is a circuit unit having a large number of switches and transmitting a switch input signal corresponding to the operated switch to the CPU 21. The LED driver 29 is controlled by the CPU 21
Flashes D30 to indicate that a call has been made. The buzzer driver 31 drives the buzzer 32 under the control of the CPU 21,
Various notifications such as call notification are performed. The display unit 33 includes the CPU 21
And displays a received message or the like stored in the message memory 27.

FIG. 4 shows the configuration of the decoder section 24 in detail. The bit synchronization circuit 40 receives a reception signal consisting of a bit string of “1” and “0” demodulated by the reception unit 23 and synchronizes this bit string with an internal clock generated by a timing control circuit 41 described later. The preamble detection circuit 42 converts the received signal as a synchronized bit string into a
The signal is sent to the synchronization signal detection circuit 43 and the BCH correction circuit 44.
The timing control circuit 41 has an oscillation circuit, a 32 bit counter, a 17 word word counter, etc., generates a clock having the same frequency as the frequency of the received signal, and detects the preamble detection circuit 42 and the synchronization signal detection circuit 43. A signal and frame data set in frame registers 49 and 50, which will be described later, are obtained, timing control of the entire decoder unit 24 is performed, and a signal read timing and an operation order of each circuit unit are determined. The preamble detection circuit 42 is a circuit for detecting the received signal, that is, the preamble signal A in the bit string from the bit synchronization circuit 40. For example, when the repetition of 8 bits “0” and “1” is continuously detected, the preamble is detected. The detection signal is sent to the timing control circuit 41 assuming that the signal A has been detected. The synchronization signal detection circuit 43 is a circuit that detects the synchronization code SC in the reception signal and sends the detection signal to the timing control circuit 41 and an SC mismatch counter 45 described later. The BCH correction circuit 44 performs a BCH error correction process on the received signal to which the BCH parity code is added as shown in FIGS. 1C and 1D, and outputs the corrected data to the data processing circuit 66 and the address comparison circuit 57. When there is an error that cannot be corrected and there is an error that cannot be corrected, a signal for an error flag is transmitted. The SC mismatch counter 45 has a counter that counts up by one with the carry output of the word counter in the timing control circuit 41 and is reset by a detection signal from the synchronization signal detection circuit 43, and the count value of the counter is SC retry. This is a circuit that sends a signal to the battery save signal decoder 46 when the number of times of the synchronization deviation set in the register 48 is reached. Battery save signal decoder 46, the switch SW ₂ receives a signal from the timing control circuit 41, SC mismatch counter 45 or CPU21
Is a circuit for controlling ON / OFF of the circuit.

The ID-ROM control decoder 47 receives a signal sent from the CPU21 when the switch SW ₁ is turned on ID-R
This is a circuit that sends a signal to the OM25 and controls it. The SC retry register 48, the frame registers 49 and 50, and the address registers 51 to 56 are registers for setting data sequentially transmitted from the ID-ROM 25 under the control of the ID-ROM control decoder 47. That is, the SC retry register 48 is the allowable number of times of synchronization deviation, the frame register 49 is the frame number related to the individual paging of the paging receiver, for example, 2 (second frame), and the frame register 50 is for receiving the information providing service. A frame number related to the general call, for example, 8 (eighth frame) is set, and an address register 5
Reference numerals 1 and 52 denote registers in which addresses in a frame corresponding to the frame number set in the frame register 49 are respectively set.For example, the address register 51 sets an address used when individually calling only the receiver. The address register 52 is set with an address used when calling a group of several receivers including the receiver at once. The address registers 51 and 52 are controlled by the frame register 49 under the control of the timing control circuit 41, and send the set addresses to the address comparison circuits 57 and 58, respectively. Address registers 53 to 56 are frame registers 50
The register in which the address in the frame related to the frame number set in is set,
For example, the address register 53 is set with gold market information, the address register 54 is set with the company A's stock price information, the address register 55 is set with the weather forecast of a specific region, and the address register 56 is set with the address when receiving each contract information such as horse race information. You. The address registers 53 to 56 are controlled by the frame register 50 under the control of the timing control circuit 41, and transmit the set addresses to the address comparison circuits 59 to 62, respectively. Address comparison circuits 57 to 62
Is controlled by the timing control circuit 41, and the BCH correction circuit 44
The address sent from the address register 51 to the address sent from the address registers 51 to 56 are compared, and when they match, a match detection signal is sent to the address message decoder 64 via the OR gate 63 and matches with the match detection signal. An address processing circuit for combining the function address data of 2 bits added to the detected address data with the address processing circuit
It is a circuit to send to 65. The output of the OR gate 63 is used as a reception continuation command signal as a battery save signal decoder.
Also sent to 46. The address message decoder 64 receives the signal sent through the OR gate 63, first sends an operation command signal to the address processing circuit 65, and then sends an operation command signal to the data processing circuit 66 after a certain period of time. is there. The address processing circuit 65 operates in response to the operation command signal from the address message decoder 64, and the address type related to the address comparison circuit (any of the address comparison circuits 57 to 62) which is sending the coincidence detection signal at that time. This is a circuit that converts data and function data into parallel bit signals used by the CPU 21 and sends them to the CPU 21. For example, a parallel signal of 8 bits consisting of 6 bits output from each address comparison circuit and 2 function bits of the detected address Is output. Data processing circuit 66
Receives the operation command signal from the address message decoder 64 and starts the operation, under the control of the timing control circuit 41, converts the message given as a serial signal from the BCH correction circuit 44 into a parallel bit signal used by the CPU 21 and sends it to the CPU 21. This is the circuit that sends out.

FIG. 5 shows the appearance of the paging receiver of this embodiment. The display unit 33 on the upper surface of the main unit 34 includes a first sub display unit 33a, a second sub display unit 33b, a first main display unit 33c, and a second main display unit 33d.
The first sub-display unit 33a sets whether the buzzer 32 is set to sound or not to be sounded upon reception (to be used during a meeting or the like), that is, set to any of sounding and silence. The second sub-display unit 33b receives a message from the address set in any of the address registers 51 to 56 when a message is displayed on the second sub-display unit 33b. Is displayed and an indication of which of the message memories 27 the message is stored in is displayed. The received message and the like are displayed on the first main display section 33c and the second main display section 33d, and the reception time of the message is displayed on the right end of the first main display section 33c while the message is displayed. Displayed during normal operation (received contents are displayed on the first main display 33
c, the time is displayed on the second main display section 33d, except when these are being checked), the current time is displayed. The mode switch SW ₃ , readout switch SW ₄ ,
A page switch SW ₅ is provided. Mode switch SW ₃
Is a switch used for mode switching, a normal mode for displaying a message stored in the message memory 27 by receiving each time of operation or receiving by the address of the address registers 51 and 52 and displaying the message on the display unit 33, Main display
The mode is sequentially and cyclically switched between a correction mode for correcting the current time displayed in 33c and various display modes for displaying various types of provided information received and stored. Incoming messages across the readout switch SW ₄ is several times that has been stored in the message memory 27 and received in the past, a switch sequentially operated to continue to display on the display unit 33. Page switches SW _5, when the received message specified by the readout switch SW ₄ can not be displayed on one screen, is a switch for displaying the subsequent message data portion.

Next, the operation of the paging receiver configured as described above will be described.

When the switch SW ₁ shown in FIG. 3 by the user is turned on, CPU 21 detects this, I of the decoder unit 24
A start signal is output to the D-ROM control decoder 47 (see FIG. 4). As a result, the ID-ROM control decoder 47
To output the stored data. Various data stored in the ID-ROM 25, that is, address data assigned to the paging receiver, frame data related to the address data, and SC retry data are respectively stored in the address register.
51-56, frame register 49, 50, SC retry register
Set to 48. After the CPU 21 outputs a start signal to the ID-ROM control decoder 47, a control signal is sent to the battery save signal decoder 46, whereby the battery save signal decoder 46 starts a preamble search operation. That the switch SW _2, as illustrated in Figure 6, 1
The ON state is set for one word time (time required for receiving one word of transmission data) with a period of seven word times. On the other hand, since the preamble signal A is transmitted continuously by 18 word time at a time, between which the preamble signal A is transmitted twice, inevitably preamble signal when the switch SW ₂ is turned on There is a timing at which A is sent. When the preamble signal A is transmitted when the switch SW ₂ is turned on, the receiver 23 from the power source 26 via the switch SW _1, SW ₂ and power supply is performed (second The preamble signal A is input to the bit synchronization circuit 40 of the decoder unit 24 as a bit string via the antenna 22 and the receiving unit 23. The preamble signal A is synchronized with the circuit operation timing by the bit synchronization circuit 40, and then sent out to the preamble detection circuit 42. At this time, the preamble detection circuit 42 detects that the transmitted signal is the preamble signal A, that is, that the repetition of “0” and “1” continues for 8 bits or more, and sends the detection signal to the timing control circuit 41. The timing control circuit 41 which has received the detection signal sends a control signal to the battery save signal decoder 46, and stops the preamble search operation, occupies perform synchronization code search operation to continuously turn on the switch SW ₂ (6 See figure). That is, the bit string from the bit synchronization circuit 40 is sequentially input to the synchronization signal detection circuit 43. Each time one bit is input, this is added to the 32 bits (1 word) including the 31 bits sent before. That is, it is checked whether a predetermined synchronization code pattern is obtained in units of the number of bits of the synchronization code SC). When the synchronization signal detection circuit 43 detects the synchronization code SC, the detection signal from the synchronization signal detection circuit 43 resets the bit counter and the word counter in the timing control circuit 41. Thereby, word synchronization is established. Thus, the timing control circuit 41 sends a control signal to the battery save signal decoder 46,
As shown in the figure, the switch SW ₂ is turned on only at the timing at which the synchronization code is sent and at the timing of the frame to which the paging receiver is assigned, that is, at the timing of frame numbers 2 and 8, and the reception is performed only at those timings. The power is supplied to the unit 23 (actually, the power is supplied about eight bits before), and reception is performed. That is, reception is performed only when there is a possibility that the paging receiver is called. After entering the synchronous code search operation
If the synchronization code SC is not detected within the 64 word time, the process returns to the preamble search operation.

At the timing of the frame number 2, the address code word is received, and the address is sent from the bit synchronization circuit 40 to the BCH correction circuit 44, where the BCH error correction processing is performed, and then the address comparison circuits 57 to Given to 62. At this timing, a control signal is sent from the timing control circuit 41 to the frame register 49 irrespective of whether or not the address is received, whereby the control signal is given from the frame register 49 to the address registers 51 and 52 managed by the frame register 49. The address data set in these address comparison circuits 57,
Sent to 58.

Thus, the address comparison circuits 57 and 58 are
When an address is sent from the Paging Receiver, the address is compared with the address assigned to the paging receiver (that is, the address set in the address registers 51 and 52 and sent from it). Is determined, that is, whether the paging receiver is being called. At this time, when either of the address comparison circuits 57 and 58 detects an address match, the detection signal from the address comparison circuit is sent via the OR gate 63 to the battery save signal decoder 46 and the address message decoder 64.
Sent to Battery save signal decoder 46 maintains the ON state to continue the switch SW ₂ receives this detection signal, performs continuous reception. Upon receiving the detection signal, the address message decoder 64 sends an operation command signal to the address processing circuit 65 first. As a result, the address processing circuit 65 transmits the detection signal as described above to the address type data relating to the address comparison circuit (either one of the address comparison circuits 57 and 58), that is, the output signals of all the address comparison circuits 57 to 62 and the transmission. The function bit data added to the received address and the parallel bit signal used by the CPU 21 are sent to the CPU 21. This allows the CPU 21
Later, it sends an operation command signal to the buzzer driver 31, drives the buzzer 32 to emit sound, sends an operation command signal to the LED driver 29, and allows the LED 30 to blink, and the user confirms that there was a call. It will be easily recognizable.

After the above operation, the address message decoder 64
An operation command signal is sent to the data processing circuit 66. Thereby, the data processing circuit 66 sequentially takes in the bit string related to the message of the message code word transmitted following the address code word related to the address from the BCH correction circuit 44 and converts it into a parallel bit signal used by the CPU 21. And sends it to the CPU 21.

The CPU 21 stores the message sent as described above in the message memory 27, confirms that the data is message data, checks for incorrect reception, and the like, and displays the message on the display unit 33.

When no address is received at the timing of the frame number 2 and an address is received at the timing of the frame number 8, the address is sent from the bit synchronization circuit 40 to the BCH correction circuit 44, Where B
CH error correction processing is performed, and then the address comparison circuit
57-62. On the other hand, at the timing, a control signal is sent from the timing control circuit 41 to the frame register 50 irrespective of whether or not the address has been received, whereby the control signal is sent from the frame register 50 to the address registers 53 to 56 managed by the frame register 50. And the addresses set therein are sent to the address comparison circuits 59 to 62, respectively.

Thus, the address comparison circuits 59 to 62
When the address is sent via, and
The addresses assigned to the receiver (that is, the addresses set in the address registers 53 to 56 and sent from them) are compared. At this time, when any of the address comparison circuits 59 to 62 detects an address match (that is, when there is a call to the paging receiver), a detection signal from the address comparison circuit is output via the OR gate 63 to the battery saving circuit. Signal decoder
46 and sent to the address message decoder 64. In response to the detection signal, the battery save signal decoder 46 causes the continuation of the reception, and the address message decoder 64
Sends an operation command signal to the address processing circuit 65. As a result, the address processing circuit 65 converts the address type data related to the address comparison circuit that sent the detection signal and the function bit data added to the received address into a parallel bit signal used by the CPU 21 as described above.
Send to PU21. In this case, since the message subsequently received is the contract information, the CPU 21 does not need to perform the call notification by the LED 30 or the buzzer 32 as in the individual call or the group call described above. May be set to turn on / off the call notification), and selects the corresponding contract information storage area in the message memory 27 according to the contents of the parallel bit signal from the address comparison circuit 65.

After the above operation, the address message decoder 64 sends an operation command signal to the data processing circuit 66. Thereby, the data processing circuit 66 sequentially takes in the bit sequence related to the message of the message code word transmitted following the address code word related to the address from the BCH correction circuit 44, and converts it into a parallel bit signal used in the CPU 21. CPU
Send to 21.

The CPU 21 stores the sent message in the selected contract information storage area in the message memory 27, performs a predetermined check, and then sends the message (ie, the gold market price, the company A's stock price information). , Etc.) are displayed on the display unit 33.

As described above, the CPU 21 sequentially displays the transmitted data on the display unit 33, but the first bit (message bit) of the transmitted word becomes 0, and the other address code word is displayed. when it solves the continuous oN state of the switch SW ₂ sends a signal to the battery save signal decoder 46, return to the normal intermittent reception operation.

The received message and its address stored in the message memory 27 as described above can be displayed and confirmed on the display unit 33 as follows. Ie received at the address of the address register 51 and 52, to select the normal mode by the mode switch SW _3, thereon, and sequentially displayed on the display unit 33 by operating the readout switch SW _4, the address register 53 to 56 sequentially in the mode switch SW ₃ is one received by the address, will specify the mode for displaying the information received at each address, after becoming a mode for displaying information desired type, by operating the readout switch SW ₄ And sequentially displays the information sent at that address on the display 33
To be displayed.

In the present embodiment, a number of paging receivers are simultaneously called, and a call for providing predetermined information is made in the eighth frame adjacent to the synchronization code word (see FIG. 7). Thus eighth frame or adjacent to the synchronization codeword to paging, when performed in the first frame, in their paging receiver you can omit the intermittent switch SW ₂ between the frame and the synchronization codeword, information Power savings can be achieved in many paging receivers provided.

The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the present invention.

[Effects of the Invention] In the present invention, as described in detail above, the base station transmits an individual call signal of each receiver in a frame corresponding to a group to which the receiver belongs, and simultaneously calls a plurality of receivers. The paging signal is transmitted in a frame adjacent to a signal for synchronizing, and the receiver, among a plurality of frames transmitted from the base station, a frame substantially corresponding to a group to which the receiver belongs, and / or the synchronization Therefore, it is necessary to process the transmission signal format when calling a large number of receivers, such as a paging receiver, because the reception for the paging signal detection is performed only in the frame adjacent to the signal for taking the paging signal. Also, it is possible to provide a selective paging method that can increase transmission efficiency without increasing information required for paging and reception control.

[Brief description of the drawings]

FIG. 1 is a diagram showing a transmission format in a selective call communication system according to one embodiment of the present invention, FIG. 2 is a diagram showing a system configuration of a radio paging system base station according to one embodiment of the present invention, FIG. FIG. 4 is a diagram showing a circuit configuration of the paging receiver, FIG. 4 is a diagram showing the configuration of the decoder unit in FIG. 3 in detail, FIG. 5 is a diagram showing an external appearance of the paging receiver,
FIG. 6 is a diagram for explaining a preamble search operation and a synchronization code search operation of the paging receiver, and FIG. 7 is a diagram showing a reception state of the paging receiver. 4 Control center 6 Input / output circuit 7
... verification circuit, 8 ... subscriber memory, 9 ... signal processing circuit, 10 ... transmitter, 11 ... antenna, 21 ... CPU, 22 ...
... Antenna, 23 ... Receiver, 24 ... Decoder, 25 ...
ID-ROM, 26 Power supply 27 Message memory 28
… Switch circuit, 29 …… LED driver, 30 …… LED, 31
…… Buzzer driver, 32 …… Buzzer, 33 …… Display unit, 40
…… Bit synchronization circuit, 41… Timing control circuit, 42…
... Preamble detection circuit, 43 ... Sync signal detection circuit, 44
… BCH correction circuit, 45… SC mismatch counter, 46… battery save signal decoder, 47… ID-ROM control decoder, 48… SC retry register, 49… frame register, 50… frame register, 51 ... 56 address registers, 57-62 address comparison circuits, 64 address message decoders, 65 address processing circuits, 66
Data processing circuit.

Claims (1)

(57) [Claims] 1. A base station transmits an individual call signal of each receiver in a frame corresponding to a group to which the receiver belongs,
A paging signal for simultaneously calling a plurality of receivers is transmitted in a frame adjacent to a signal for synchronizing, and the receiver transmits, from among the plurality of frames transmitted from the base station,
A frame substantially corresponding to the group to which the aircraft belongs and / or
A selective paging method, wherein reception for paging signal detection is performed only in a frame adjacent to the signal for synchronization.