JP2508585B2 - Information receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates relates to the information receiving apparatus, in particular information, information service company of the preferred information receiving apparatus for receiving the information provided for a fee.

[0002]

BACKGROUND OF THE INVENTION In current paging systems, it is possible to send message information to a paging receiver that has called, as well as to call the paging receiver. On the other hand, using the paging system as described above, a service for providing a large number of subscribers with information such as stocks and precious metal quotes for a fee has begun to be implemented. By the way, when attention is paid to a specific paging receiver, all paging that receives the service for each of the above services is independent of the unique reception control data such as an address (call number) when only the paging receiver receives a call. It is necessary to receive the setting of common reception control data given to the receiver. Conventionally,
The reception control data for receiving the service was stored in the built-in ID-ROM in the same manner as the reception control data when calling only the paging receiver. However, in this case, as the number of services increases or changes, a paging system providing company is requested each time and a built-in ID is sent.
-It was extremely troublesome to rewrite the stored contents of the ROM (that is, the reception control data for receiving the service). Further, there is also a disadvantage that a normal individual call cannot be received while a request for rewriting the stored contents of the ID-ROM.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above background, and relates to reception control data that does not need to be changed.
The possibility of changes without affecting the receipt of the information
Information reception that can easily change only certain reception control data
The purpose is to provide a communication device .

[0004]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is modified.
Receiving control data that does not need to be changed is stored in the device storage means
The reception system that can be changed and
The gist of the present invention is that the control data is stored in a storage medium that can be attached to and detached from the main body of the apparatus, and input from this storage medium .

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to an embodiment shown in the drawings.

Transmission Signal Format First, a transmission signal format in a paging system using the paging receiver according to the embodiment will be described with reference to FIG. FIG. 1A shows the overall format, and the transmission signal is composed of a preamble signal A and a plurality of batches B, C ... Preamble signal A
Is for achieving bit synchronization between the transmission signal and the receiver and is a continuous pattern of "1" and "0" of "1010101 ..." Continued for 576 bits. Further, FIG. 3B shows the format of each of the above batches, and the synchronization code SC
And 8 frames from 1st to 8th
The frame consists of 2 codewords. Both the synchronization code SC and one codeword have a 32-bit structure, and the codeword is divided into an address codeword indicating a calling number and a message codeword indicating a message. An address codeword is shown in FIG. 7C, and a message codeword is shown in FIG. The address codeword is
The first bit is a message flag that distinguishes between an address codeword and a message codeword. In the case of an address codeword, this bit is "0". Second
.About.19 bits are address bits representing address data, 20th and 21st bits are function bits indicating a display form and a sounding form, 22nd to 31st bits are BCH parity bits, and 32nd bits are even parity bits. In the message code word, the first bit is a message flag and "1" indicating the message code word is set, the 2nd to 21st bits are the message bits representing the message data, and the 22nd to 31st bits are the BCH.
The parity bit and the 32nd bit are the even parity bit. Further, in the sync code word SC, 32 bits have a specific pattern. The above-mentioned signal is a signal of a system for selectively calling the paging receiver according to the address data of the address codeword and the order of the frame for transmitting the address codeword. Therefore, one address and one frame (for example, the second frame) are assigned to each paging receiver in order to receive an individual call. Two addresses may be assigned if necessary. In this case, one address is used for normal individual calls and the other address is used for an emergency call or for a group of several paging receivers including the receiver to which the same frame as the receiver is assigned. Used for calling. In addition to the address and frame for receiving the individual call, the paging receiver that has a contract to receive the information providing service has an address and a frame for receiving the information providing service (for example, the fifth frame). ) Is further allocated. When sending a message, an address codeword is added at the beginning, and then a message codeword of the required length is sent. Note that transmission is 62.5 ms per word (hereinafter referred to as 1 word time)
The same content (address and message) is retransmitted after a predetermined time, for example, 60 seconds, in order to reduce reception errors on the receiver side.

Configuration FIG. 2 shows a circuit configuration of the paging receiver according to the present embodiment. In other words, the CPU 1 is the main component, and the other circuit units are connected thereto. CPU1 has built-in RO
Each circuit unit is controlled according to the program of M. Receiver 3
Is a receiver that demodulates the radio waves received by the antenna 2. The ID-ROM 5 stores data such as frames and addresses individually assigned to the paging receiver, and sends the stored data such as frames and addresses under the control of the decoder unit 4 to the decoder unit 4. To do. The decoder unit 4 applies the ID-R to the received signal demodulated by the receiving unit 3.
Decodes based on data from OM5, it is time in which has been transmitted to the self, call detection signal and subsequently on-off control of the switch SW ₂ and sends the message data to the CPU1 received It is a circuit unit that does. The switch SW ₂ is on / off controlled by the decoder unit 4, and disconnects the power supply supplied from the power source 6 to the receiving unit 3 via the switch SW ₁ . The switch SW ₁ is a manual switch that is turned on / off by a user's operation, and disconnects the power supply from the power supply 6 to the decoder unit 4 and the like. The ROM card 7 is detachably attached and fixedly stores reception control data (for example, frame data and address data) for receiving the information providing service. The message memory 8 is a memory in which the memory area is divided into a plurality of areas and the received message is stored in different memory areas depending on the type of the message. The switch circuit 9 is a circuit unit that includes a large number of switches and sends a switch input signal corresponding to the operated switch to the CPU 1. Under the control of the CPU 1, the LED driver 10 blinks the LED 11 to notify that the paging receiver has been called. The buzzer driver 12 drives the buzzer 13 under the control of the CPU 1,
Various notifications such as call notifications are made. The display unit 14 is a CP
It is a circuit unit that receives the control of U1 and displays the received message and the like stored in the message memory 8.

FIG. 3 shows the structure of the decoder section 4 in detail. The bit synchronization circuit 20 inputs the reception signal composed of the bit string of "1" and "0" demodulated by the receiving unit 3, and the bit string and a timing control circuit 21 described later.
Is a circuit for synchronizing with an internal clock generated by the preamble detection circuit 22, the synchronization signal detection circuit 23 and the BCH.
It is sent to the correction circuit 24. The timing control circuit 21 has an oscillating circuit, a 32-bit bit counter, a 17-bit word counter, and the like, generates a clock having the same frequency as the frequency of the received signal, and preamble detection circuit 22,
By obtaining the detection signal of the synchronization signal detection circuit 23 and the frame data set in the frame registers 29 and 30 described later, the timing control of the entire decoder unit 4 is performed,
The signal reading timing and the operation sequence of each circuit unit are determined. The preamble detection circuit 22 is a circuit for detecting the received signal, that is, the preamble signal A in the bit string from the bit synchronization circuit 20, and for example, when the repetition of “0” and “1” is continuously detected for 8 bits. Assuming that the preamble signal A has been detected, the detection signal is sent to the timing control circuit 21. Sync signal detection circuit 23
Is a circuit that detects the synchronization code SC in the received signal and sends the detected signal to the timing control circuit 21 and the SC mismatch counter 25 described later. As shown in FIGS. 1C and 1D, the BCH correction circuit 24 performs BCH error correction processing on the received signal to which the BCH parity code is added, and outputs the corrected data to the data processing circuit 46 and the address comparison circuit 37. If there is an error that cannot be corrected, the error flag signal is sent. The SC mismatch counter 25 is used by the timing control circuit 2
It has a counter that counts up by 1 by the carry output of the word counter in 1 and is reset by the detection signal from the synchronization signal detection circuit 23, and the count value of the counter is set in the SC retry register 28. This is a circuit that sends a signal to the battery save signal decoder 26 when the allowable number of deviations is reached. The battery save signal decoder 26 includes the timing control circuit 2
1, a circuit that receives a signal from the SC mismatch counter 25 or the CPU 1 and controls the switch SW ₂ to turn on / off.

The ID-ROM control decoder 27 is a circuit which receives a signal sent from the CPU 1 when the switch SW ₁ is turned on and sends a signal to the ID-ROM 5 to control it. SC retry register 28, frame register 29 and address registers 31, 32
Is a register for setting the data sequentially sent from the ID-ROM 5 under the control of the ID-ROM control decoder 27. That is, the SC retry register 28 is the permissible limit number of synchronization deviations, and the frame register 29 is the frame number (1 for the first frame, 2 for the second frame ... 8 for the individual frame of the paging receiver). 2) is set, and the address registers 31 and 32 are registers in which the addresses in the frame of the frame number set in the frame register 29 are respectively set. For example, the address register 1 is the receiver. The address register 32 is set to the address used when calling a group of several receivers including the receiver simultaneously. The address register 3
1, 32 are controlled by the frame register 29 under the control of the timing control circuit 21, and send the set addresses to the address comparison circuits 37, 38, respectively. Frame register 30, address registers 33-3
Reference numeral 6 indicates that when the switch SW ₁ is turned on, when the ROM card 7 is attached to the main body of the paging receiver, the reception control data stored in the ROM card 7 is sent from the CPU 1. The registers are sequentially set. That is, the frame register 30 is set to the frame number of the frame used for receiving the information providing service, for example, 5, and the address registers 33 to 36 are set to the frame number of the frame number set in the frame register 30 (that is, the fifth frame). Address registers in the register are set. For example, the address register 33 is the gold market price information, the address register 34 is the stock price information of the company A, the address register 35 is the weather forecast of a specific region, and the address register 36 is the horse racing information. Addresses for receiving contract information are set respectively. The address registers 33 to 36 are controlled by the frame register 30 under the control of the timing control circuit 21 and send the set addresses to the address comparison circuits 39 to 42, respectively. The address comparison circuits 37 to 42 are controlled by the timing control circuit 21, and the addresses sent from the BCH correction circuit 24 and the address registers 31 to 36, respectively.
The addresses sent from the two are compared, and when they match, a match detection signal is sent to the address message decoder 44 through the OR gate 43, and the 2-bit function added to the match detection signal and the address data for which the match is detected. Bit data and address processing circuit 45
It is a circuit to send to. The output of the OR gate 43 is also sent to the battery save signal decoder 26 as a reception continuation instruction signal. Address message decoder 44
Is a circuit which receives a signal sent through the OR gate 43, first sends an operation command signal to the address processing circuit 45, and then sends the operation command signal to the data processing circuit 46 after a lapse of a fixed time. The address processing circuit 45 operates by receiving the operation command signal from the address message decoder 44, and operates at the time, and the address type of the address comparison circuit (any of the address comparison circuits 37 to 42) which sends the coincidence detection signal at that time. A circuit for converting data and function bit data into parallel bit signals used in the CPU 1 and sending them to the CPU 1. For example, 6 bits output from each address comparison circuit and 2 function bits added to the address detected as a match. Output a parallel 8-bit signal. Further, the data processing circuit 46 receives the operation command signal from the address message decoder 44 and starts the operation, and under the control of the timing control circuit 21, a message given as a serial signal from the BCH correction circuit 24 is a parallel bit signal used in the CPU 1. And CPU
It is a circuit for sending to 1.

FIG. 4 shows the internal structure of the ROM card 7. That is, the rows of the row addresses 1 to 4 form the address data memory AM, and the addresses set in the address registers 33 to 36, that is, the addresses used when receiving the information providing service are fixedly stored in each row. There is. Further, the row of the row address 5 is the frame data memory FM, and the frame register 30
The frame number to be set to, that is, the frame number of the frame when receiving the information providing service is fixedly stored. Further, the rows after the row address 6 constitute the information seed memory KM, and the above-mentioned address data memory A
At each address stored in M, the correspondence between the address and the information type code indicating what information is received is fixedly stored. Note that one address has 1
One information type code does not always correspond, and a plurality of information type codes may correspond to one address. For example, a plurality of information type codes such as an information type code indicating a gold price in Tokyo, a gold price in London, and a gold price in New York correspond to each address related to the gold price.

FIG. 5 shows the appearance of the paging receiver of this embodiment. That is, (a) of the figure shows the main body 15 excluding the ROM card 7, and (b) of the figure shows the ROM card 7. When receiving the information providing service, the ROM card 7 is inserted from the terminal portion 7a side and attached to the attaching portion 16 formed on the right side surface of the main body portion 15. The display unit 14 on the upper surface of the main body unit 15 includes the first sub display unit 14a and the second sub display unit 14
b, a first main display section 14c and a second main display section 14d, and whether the buzzer 13 is set to be sounded or not to be sounded when the first sub display section 14a receives a signal (for example, during a meeting). That is, whether the sound is set or not, and the battery life of the power source 6 is displayed.
When there is a reception in b, the address registers 31 to 36
An indication is made as to which address has been set, and an indication as to which memory of the message memory 8 it was stored. Then, the first main display portion 14c and the second main display portion 14
Although the received message and the like are displayed in d, the reception time of the message is displayed at the right end of the first main display portion 14c while the message is being displayed, and in a normal time (the reception content is displayed by the first main display). The current time is displayed in the areas 14c and the second main display portion 14d, except when checking these). A mode switch SW ₃ , a read switch SW ₄ , and a page switch SW ₅ are arranged on the upper surface of the main body 15. The mode switch SW ₃ is a switch used for switching the mode, and is usually used when the display unit 14 displays the memory stored in the message memory 8 by receiving it each time it is operated or by the addresses of the address registers 31 and 32. The modes are sequentially and cyclically switched to a mode, a correction mode for correcting the current time displayed on the first main display portion 14c, and a display mode for displaying various provided information received and stored. The read switch SW ₄ is a switch operated when sequentially displaying the received messages received several times in the past and stored in the message memory 8 on the display unit 14. The page switch SW ₅ is a switch for displaying the subsequent message data portion when the received message designated by the read switch SW ₄ cannot be displayed on one screen.

[0012] Operation Next, the operation of this embodiment constructed in as above. When the switch SW ₁ is turned on by the user, the CPU 1 detects this and detects the ID of the decoder unit 4.
-When a start signal is output to the ROM control decoder 27 and the ROM card 7 is attached, the stored data is read and sent to the frame register 30 and the address registers 33 to 36 to be set. Then, the ID-ROM control decoder 27 which has received the activation signal is
-Sending a control signal to the ROM 5 to output the stored data, and to set them in the SC retry register 28, the frame register 29, and the address registers 31 and 32. As a result, the SC retry register 28 stores S
C retry data, the frame register 29 is the frame number of the frame used for calling the entire paging receiver alone or a group of several paging receivers including the paging receiver, that is, 2, and the address register 31 is the above frame. The address when receiving the call of only the paging receiver in the frame related to the register 29 (that is, the second frame), and the address register 32 when receiving the call of the entire group in the frame related to the frame register 29. The register 30 has the frame number of the frame used when receiving the information providing service, that is, 5, and the address registers 33 to 36 have the frame number corresponding to the frame register 30 (that is, the fifth frame). Address is set, respectively.

After the above, a control signal is sent from the CPU 1 to the battery save signal decoder 26, whereby the battery save signal decoder 26 enters the preamble search operation. That is, as shown in FIG. 6, the switch SW _{2 is set} to 17 word time (1 word time is 1
The time required for transmitting / receiving a word) is set as a cycle and is turned on for one word time. On the other hand, the preamble signal A
Is sent continuously for 18 words each time, so while the preamble signal A is sent twice, the preamble signal A is necessarily sent when the switch SW ₂ is in the ON state. There is a timing to come. Then, at this timing, that is, when the preamble signal A is sent while the switch SW ₂ is in the ON state, power is supplied from the power source 6 to the receiving unit 3 via the switches SW ₁ and SW _2. (See FIG. 2), the preamble signal A is input to the bit synchronization circuit 20 of the decoder unit 4 as a bit string via the antenna 2 and the receiving unit 3. The preamble signal A is synchronized with the circuit operation timing in the bit synchronization circuit 20, and then sent to the preamble detection circuit 22. At this time, the preamble detection circuit 22 detects that the transmitted signal is the preamble signal A, that is, the repetition of "0" and "1" continues for 8 bits or more, and sends the detection signal to the timing control circuit 21. Upon receiving the detection signal, the timing control circuit 21 sends a control signal to the battery save signal decoder 26 to stop the preamble search operation,
A synchronous code search operation for continuously turning on the switch SW ₂ is performed (see FIG. 6). That is, the bit string from the bit synchronization circuit 20 is sequentially input to the synchronization signal detection circuit 23 every time one bit is input, and this is combined with the 31 bits sent before that to 32 bits.
It is checked whether or not a predetermined sync code pattern is obtained in units of bits (one word, that is, the number of bits of the sync code pattern). When the sync signal detection circuit 23 detects the sync code SC, the detection signal from the sync signal detection circuit 23 resets the bit counter and the word counter in the timing control circuit 21. Thus, the timing control circuit 21 has the battery save signal decoder 26
As shown in FIG. 7, the control signal is transmitted to the frame, and the timing at which the synchronization code is transmitted and the frame to which the paging receiver is assigned, that is, the frame numbers 2 and 5 are assigned.
The switch SW ₂ is turned on only at the timing of, and power is supplied to the receiving unit 3 only at those timings (actually, power is supplied from about 8 bit time before) to perform reception. That is, reception is performed only when the paging receiver may be called. When the sync code SC is not detected within 64 word time after entering the sync code search operation, the operation returns to the preamble search operation.

Next, the operation at the timing of the frame numbers 2 and 5 will be described separately for each timing.

First, at the timing of frame number 2, an address codeword is received, and its address is sent from the bit synchronization circuit 20 to the BCH correction circuit 24, where BCH error correction processing is performed, and then address comparison is performed. Provided to circuits 37-42. At the timing, the control signal is sent from the timing control circuit 21 to the frame register 29 regardless of whether or not the address is received, whereby the frame register 29 gives the control signal to the address registers 31 and 32 managed by the frame register 29. , And the address data set therein are sent to the address comparison circuits 37 and 38 as bit strings, respectively.

Thus, the address comparison circuits 37 and 38 are
When the address received from the BCH correction circuit 24 is sent, the address assigned to the paging receiver (that is, the address registers 31, 3) is sent.
Address set to 2 and sent from then)
Is compared to determine whether the two coincide with each other, that is, whether the paging receiver is called. At this time, when either of the address comparison circuits 37 and 38 detects the coincidence of the addresses, the detection signal from the address comparison circuit is sent to the battery save signal decoder 26 and the address message decoder 44 via the OR gate 43. The battery save signal decoder 26 receives the detection signal and continuously maintains the switch SW ₂ in the ON state to continue the reception. The address message decoder 44 receives the detection signal and first sends an operation command signal to the address processing circuit 45. As a result, the address processing circuit 45 sends the detection signal as described above (either the address comparison circuit 37 or 38).
The address type data related to the above, that is, the output signals of all the address comparison circuits 37 to 42 and the function bit data added to the transmitted address data are CP.
A parallel bit signal used in U1 is sent to CPU1.

After the above operation, the address message decoder 44 sends an operation command signal to the data processing circuit 46. As a result, the data processing circuit 46 sequentially takes in the bit string related to the message of the message codeword sent after the address codeword related to the above address from the BCH correction circuit 24 and converts it into a parallel bit signal used in the CPU 1. And sends it to the CPU 1.

On the other hand, when the address is not received at the timing of the frame number 2 and the address is received at the timing of the frame number 5, the address is transferred from the bit synchronization circuit 20 to the BCH correction circuit 24.
BCH error correction processing is performed here, and is then given to the address comparison circuits 37 to 42. on the other hand,
Regardless of the presence or absence of reception of the above address, the timing control circuit 21 to the frame register 30
To the frame register 30.
From this, a control signal is given to the address registers 33 to 36 which it manages, and the addresses set in these are sent to the address comparison circuits 39 to 42, respectively.

Thus, the address comparison circuits 39 to 42 are
When the address received via the BCH correction circuit 24 is sent, the address assigned to the receiver (that is, the address set in the address registers 33 to 36 and sent from them) is sent. )
Compare each. At this time, the address comparison circuit 39-
When any of 42 detects a match of the addresses (that is, when there is a call to the paging receiver), the detection signal from the address comparison circuit is transmitted via the OR gate 43 to the battery save signal decoder 26 and the address message. It is sent to the decoder 44. In response to the detection signal, the battery save signal decoder 26 continues the reception, and the address message decoder 44 sends an operation command signal to the address processing circuit 45. As a result, the address processing circuit 45 converts the address type data related to the address comparison circuit which has sent the detection signal and the function bit data added to the received address data into parallel bit signals used by the CPU 1 as described above. Send to.

After the above operation, the address message decoder 44 sends an operation command signal to the data processing circuit 46.
As a result, the data processing circuit 46 sequentially outputs the bit string related to the message of the message codeword sent after the address codeword related to the above address to the BC.
It is fetched from the H correction circuit 24, converted into a parallel bit signal used in the CPU 1, and sent to the CPU 1.

On the other hand, the CPU 1 sequentially operates as described above.
The sent data is temporarily set in the built-in buffer register, but when the first bit (message bit) of the sent word becomes 0 and it becomes another address code word, the battery save signal decoder A signal is sent to 26 to release the continuous ON state of the switch SW ₂ , and the normal intermittent reception operation is resumed.

When the address type data and the message data are sent to the CPU 1 as described above, the incoming call processing described below is executed. FIG. 8 shows this incoming call processing. That is, in step S1, the sent address type data and message data are stored in the buffer register built in the CPU 1,
Once set, then in step S2, address discrimination is performed based on the address type data sent. That is, the called address is the address register 3
1 or 32, or an address set in any of the address registers 33 to 36 (that is, whether the address is called and received at the timing of frame number 2 or frame number 5). It was called and received at the timing of
If it is the former, the process proceeds to step S3. And
In step S3, the current reception is a repeat call (the same content is transmitted twice in 60 seconds in order to reduce reception errors as described above. Re-reception of the same content within the 60 seconds is called a repeat call. ),
In the case of a repeat call, the buffer register is cleared (step S9) and the processing ends. However, in the case of no repeat call, the address type data and the message data stored in the buffer register are sent to the message memory 8. And store it in the normal message storage area. Next, it is judged whether or not the silent state is set (step S5). When the silent state is set, the process directly proceeds to step S7, but when not set, the buzzer driver 12 drives the buzzer 13 to drive. A buzzer sound is generated, and then the process proceeds to step S7. Then, in step S7, the LED driver 10 drives the LED 11 to blink the LED 11. After that, the address type data, the message data, etc. relating to the present reception stored in the message memory 8 are displayed on the display unit 14 (step S8).

On the other hand, when it is determined in step S2 that the current reception is related to the address set in the address registers 33 to 36, that is, related to the information providing service, the information type code in the message is received. Determines whether any of the information type codes stored in the information type memory KM of the ROM card 7 matches (step S10), and if they do not match, the paging receiver is not the information to be provided (for example, , The address is stored in the ROM card 7 to receive the information of the gold market price, but the contract to receive the information is only the gold market price of Tokyo, and the ROM card 7 stores only the information type code, and This applies when the current reception was information about the New York money market), and clears the buffer register. Te (step S9), and ends the process. On the other hand, if they match, it is determined whether the current reception is a repeat call as in step S3 (step S11), and if it is a repeat call, after the processing in step S9, Finish incoming call processing. If it is not a repeat call, the message data is stored in the corresponding memory area of the message memory 8 based on the address type information and the information type code received this time (step S12), and the incoming call process is terminated.

In addition, as described above, the message memory 8
The received message and its address stored in can be displayed and confirmed on the display unit 14 as follows. That is, for the address received by the address registers 31 and 32, the normal mode is selected by the mode switch SW ₃ , and then the read switch SW ₄ is operated to sequentially display on the display unit 14, and the address registers 33 to 36 are sequentially displayed. The mode switch SW ₃ receives the address, and sequentially specifies the modes for displaying the various types of provided information received by these addresses. After the mode becomes the mode for displaying the desired type of information, the read switch SW 3 is displayed. _The user operates ₄ to display on the display unit 14 the specific type of provided information sequentially sent at the address.

The present invention is not limited to the above-mentioned embodiments, and various modifications and applications are possible within the scope of the present invention.

For example, in the present embodiment, the ROM card 7 stores the address and the information seed code, but it may be stored only in the address, and the ROM card 7 stores only the information seed code. , All addresses are I
Of course, the data may be stored in the D-ROM.

[0027]

As described above in detail, the present invention is modified.
Receiving control data that does not need to be stored in the storage means of the device
Receiving control that can be changed as well as stored
The data is stored in a storage medium that can be attached to and detached from the device body,
Since it relates to the information receiving device which can be input from this storage medium, it is not necessary to change the receiving control data.
Change without affecting the reception of information related to
(EN) It is possible to provide an information receiving device that can easily change only reception control data that may possibly change.

[Brief description of drawings]

FIG. 1 is a diagram showing a transmission signal format used in a paging system using a paging receiver according to an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a paging receiver according to an embodiment of the present invention.

FIG. 3 is a diagram showing in detail the configuration of a decoder section in FIG.

FIG. 4 is a diagram showing a configuration of a ROM card in FIG.

FIG. 5 is a diagram showing an appearance of a paging receiver according to the above embodiment.

FIG. 6 is a diagram illustrating a preamble search operation and a sync code search operation.

FIG. 7 is a diagram illustrating an operation at the time of reception.

FIG. 8 is a flowchart showing an incoming call process.

[Explanation of symbols]

1 CPU 2 Antenna 3 Receiver 4 Decoder 5 ID-ROM 6 Power 7 ROM Card 7a Terminal 8 Message Memory 9 Switch Circuit 10 LED Driver 11 LED 12 Buzzer Driver 13 Buzzer 14 Display 14a First Sub Display 14b Second Sub display part 14c First main display part 14d Second main display part 15 Main body part 16 Mounting part 20 Bit synchronization circuit 21 Timing control circuit 22 Preamble detection circuit 23 Sync signal detection circuit 24 BCH correction circuit 25 SC mismatch counter 26 Battery save signal Decoder 27 ID-ROM control decoder 28 SC retry register 29 Frame register 30 Frame register 31-36 Address register 37-42 Address comparison circuit 44 Address message decoder 45 Address processing Circuit 46 Data processing circuit SW ₁ , SW ₂ switch SW ₃ mode switch SW ₄ read switch SW ₅ page switch

Claims (2)

(57) [Claims] 1. An information receiving device for receiving information, wherein a storage means for storing first reception control data and a storage medium for storing second reception control data are removable.
And the first reception control data stored in the storage means.
The reception of such information is permitted and the information is recorded on the storage medium.
The reception of the information related to the stored second reception control data
Information reception characterized by comprising a reception control means for allowing
Communication device. (2) The first reception control data is an individual call
It is control data that allows the reception of information at the time of The second reception control data is transmitted to a large number of information receiving devices.
Control data that allows the reception of information provided by
The information receiving apparatus according to claim 1, characterized in that.