JP2935037B2 - Call detection device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a paging receiver that detects its own call by comparing a plurality of call numbers stored and set in an ID-ROM with a received call number. .

[Prior Art and Problems to be Solved] Recent paging receivers can set not only a call number (address data) unique to itself but also a call number for group call and service information reception. I have.

However, in the conventional paging receiver, when these additional call numbers are not set, the address data read from the corresponding area of the ID-ROM is all “1” (or all “0”). An unset call number was compared with the received call number as a call number in which all "1" s were set.

Therefore, useless power is consumed in the call detection unit, and the battery life is unduly shortened.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a paging receiver that can prevent wasteful power consumption in a call detection unit and can prolong battery life.

[Means for Solving the Problems] The present invention relates to a call detecting device which stores address data for defining a call to the self and detects a call by receiving the address data. Identification data for identifying the setting state of the address data is stored, and when the address data is detected, control is performed to restrict the call detection operation, for example, to prohibit the call detection operation.

Also, the present invention provides a call detection device which has a storage unit including address data defining a call to the self, and performs a call detection by receiving the address data in the storage unit. It is configured to store identification data for identifying a setting state of the storage unit, and to control a call detection operation such as prohibiting a call detection operation when detecting address data in the storage unit. is there.

Further, the present invention has a storage unit including address data that defines a call to the self, and a call detection device that performs a call detection by receiving the address data in the storage unit. The identification data for identifying the setting state of the storage unit is stored. For example, when the identification data is data indicating invalidity of the frame data in the corresponding storage unit, the address data at the timing specified by the frame data is stored. In this configuration, reception is stopped.

According to the present invention, when a paging signal transmitted from a radio base station is received, a call is detected by comparing it with stored address data. The call detection operation is controlled by the stored identification data. That is, if the setting state corresponding to the identification data is data that restricts the call detection operation, the call detection operation is restricted by, for example, prohibiting the call detection operation using the address data.

Further, according to the present invention, when a call signal transmitted from a radio base station is received, a call is detected by comparing it with address data included in a storage unit. The call detection operation is controlled by the identification data stored corresponding to the included storage unit. That is, if the setting state corresponding to the identification data is data that restricts the call detection operation, the call detection operation is restricted by, for example, prohibiting the call detection operation using the address data.

Further, the present invention has a storage unit including address data defining a call to the self, and a call detection device that detects a call by receiving the address data in the storage unit. When identification data for identifying a setting state of the storage unit is stored, and the identification data is data indicating invalidity of frame data in the storage unit, reception of address data at a timing defined by the frame data is performed. Stop.

Therefore, for example, in the call detection of the paging receiver, power consumption due to useless operation can be reduced.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, the overall circuit configuration of the paging receiver will be described with reference to FIG. In the figure, 11 is an antenna,
Radio waves output from the wireless base of the message service company are received and input to the receiving unit 12. The radio wave output from the wireless base of the message service company is, for example, 280M
Hz FM radio waves are used and modulated by the FSK signal (NRZ) method. The receiving section 12 includes a selecting circuit for selecting a 280 MHz signal, a demodulating circuit for demodulating an FSK signal, and the like. The receiving section 12 demodulates the FSK FM signal into “0” and “1” signals, and sends the signal to the decoder section 13. Output. The decoder unit 13 is connected to an ID-ROM 14 that stores its own calling number and the like. That is, in the ID-ROM 14, an individual call number (composed of frame data and address data) assigned only to the receiver, a group call number assigned to a specific receiver group in the same frame as the individual call number, Further, for example, four kinds of call numbers assigned to an unspecified number of receivers to receive service information provided for a fee, such as stock information, precious metal information, exchange information, etc., can be set. Retry count data is set to control whether synchronization is deemed to be out of synchronization when no communication is detected.

The decoder unit 13 is, for example, a POCSAG (POCS
AG), the received data is analyzed, and it is determined with reference to the ID-ROM 14 whether or not the received calling number is its own calling number. Receives and outputs to CPU15. This CPU15
, The operating power is always supplied from the DC power supply 16.
This DC power supply 16 is further supplied to the decoder unit 13 via the manual switch SW1, and furthermore, the electronic switch
It is supplied to the receiving unit 12 via SW2. In addition, DC power supply 16
Is output from the switch S1 through the switch SW1.
It is input to the CPU 15 as an operation signal for W1. The decoder unit 13 includes an electronic switch SW2 based on support from the CPU 15 and the like.
Is turned on / off, and power supply to the receiving unit 12 is controlled.

The CPU 15 further includes a message memory 17 for storing message data, a switch circuit 18 for reading stored contents of the message memory 17, a driver 20 for driving a speaker 19, a driver 22 for driving an LED 21 to emit light, a received message, and the like. Is displayed on the display unit 23. The driver 20 drives the speaker 19 in accordance with a command from the CPU 15 when receiving the call signal to notify the incoming call. At this time, the LED 21 is driven to emit light by the driver 22.

Next, an outline of the pox sag method used in the paging receiver will be described. FIGS. 2 (A) to 2 (D)
FIG. 4 is a data configuration diagram of a poxag method.

FIG. 2 (A) shows the entire transmission signal format. In the Poxag system, a preamble signal A in which 576 bits of bit data sequentially follows 101010 and a plurality of batch signals B, C,. Has become. The preamble signal is a signal for causing the paging receiver to recognize that data will be sent from now on and for achieving bit synchronization. The decoder unit 13 detects the preamble signal and prepares for reception of the subsequent batch data.

FIG. 2B shows a batch format of the batch data. In this batch format, there is first a one-word synchronization code SC, followed by eight frames CD1 to CD8 each consisting of a two-word code. Each code word has a 32-bit configuration, and word codes include an address code word and a message code word.

FIGS. 2C and 2D show the structures of an address code word and a message code word, respectively.
FIG. 2C shows an address code word, which has a message flag at the beginning, an address code, a function bit, a BCH parity, and an even parity.

The message flag is a flag for identifying whether the next code is an address code or a message code. When the code is "0", it indicates an address code word, and when it is "1", it indicates a message code word. The 2nd to 19th bits after the message flag are the address code, which corresponds to the above-mentioned calling number. Further, there are two function bits after this. This is a bit for indicating the display mode and the alarm mode, for example, “00”, “0”.
There are four types of functions, "1", "10", and "11". This function information can be input by the caller with a touch-tone telephone by contracting with the message company, and can also be used to identify the caller. In the poxag method, an error may occur within one code, for example, an address code. In particular, when the reception state is poor, the demodulation of the FSK signal is not complete, and an aerial error occurs. To correct this, BCH parity is provided in bits 22-31. Thereafter, an even parity bit is provided. This even parity indicates whether the total number of bits whose first to last bits represent the number of “1” is an odd number or an even number.

In the case of the message code word shown in FIG. 2D, a message bit is added after the message flag. This is in addition to the message from the caller, for example a telephone number and other information. Similarly, BCH parity and even parity data are added to the same code word to form a message code word.

Next, the details of the decoder section 13 will be described with reference to FIG.

In the figure, reference numeral 31 denotes a timing control circuit, which includes an oscillation circuit, a frequency dividing circuit, a bit counter (32 base), a word counter (17 base), a preamble signal detection circuit, a synchronization code detection circuit, and the like. In response to the initialization command signal, the response signal, and the message end detection signal from the CPU 15 and the CPU 15, a command and a clock pulse are supplied to necessary circuits. That is, the timing control circuit 31 outputs an on / off signal to the electronic switch SW2 in a predetermined synchronization,
When the switch SW1 is operated, the operation command O1 is output from the terminal "1" to the ID-ROM control decoder 32. The timing control circuit 31 sends the first frame register 3 from the terminals O2 to O8.
3. The shift clock is output to the second frame register 34, the retry number register 35, and the first to sixth address registers 36a to 36f. Further, the first to sixth address registers 36a to 36f and the flip-flops 37a to Give control command to 37f. Each of the frame registers 33 and 34 is a 4-bit shift register, and each retry number register 35 is a 3-bit shift register or address register.
36a to 36f are cyclic shift registers having a 19-bit configuration.

The ID-ROM control decoder 32 operates in accordance with the operation command to read the stored data from the ID-ROM 14 and serially inputs the read data to the retry number register 35, the second frame register 34, and the first frame register 33. The serial output of the frame register 33 is further transferred to a sixth address register 36f.
To enter. The first frame register 33 reads, for example, an individual call number for frame No. 2, and the second frame register 34 reads, for example, a call number for receiving service information for frame No. 8. Then, the data held in the retry number register 35, the second frame register 34, and the first frame register 33 are read out in parallel and input to the timing control circuit 31.

On the other hand, the data input to the sixth address register 36a is serially transferred to the fifth to first address registers 36e to 36a. Further, the address registers 36a to 36a
The first bit of the data set in 6f is also input to flip-flops 37a to 37f. This flip-flop 37
The bits input to a to 37f are the address registers 36a to 3
It indicates whether the address data set in 6f is valid or invalid. If it is valid, "0" is set, and if it is invalid, "1" is set.

The address data set in the address registers 36a to 36f are input to the first to sixth address first comparing units 38a to 38f, respectively, and also input to the check bit generation circuit 40 via the OR circuit 39. Is done. Further, the received signals received by the receiving unit 12 are input to the first address comparing units 38a to 38f via the bit synchronization circuit 41. The bit synchronization circuit 41 converts the received signal into the timing control circuit 31
The waveform is shaped and output in accordance with the sampling signal received from the first and second address comparators 38a to 38f, and is also input to a 13-bit shift register 42 and a BCH error correction circuit 43. In addition, the bit synchronization circuit 41 detects a change point of the received signal,
That is, a change point where “1” changes to “0” and “0” changes to “1” is detected, and a detection signal is output to the timing control circuit 31. The timing control circuit 31 includes a bit synchronization circuit 41
The timing signal generation position is adjusted in accordance with the change point detection signal from.

The BCH error correction circuit 43 is a circuit that performs error detection and correction on received data. For example, when a 1-bit error is detected, the error is corrected and output to the message output buffer 44, and an error of 2 bits or more is detected. If detected, the received data is output to the message output buffer without correction.
At the same time, the error signal is output to the message output buffer 44.

Thus, the address first comparing units 38a to 38f
As shown in the figure, an EXOR circuit (hereinafter, abbreviated as an EX OR circuit) 51 and a counter 52 are provided, and address data from the address registers 36a to 36f and address data from the bit synchronization circuit 41 are stored in the EX OR circuit 51. Is input to the counter 52 via the. The output signals of the flip-flops 37a to 37f are input to the reset terminal R of the counter 52. Address first comparing unit configured as described above
If the set data of the corresponding flip-flops 37a to 37f is "0", the reset state of the counter 52 is released, and the comparison operation becomes possible for the flip-flops 37a to 38f.
If the set data of .about.37f is "1", the counter 52 is held in the reset state and the comparison operation is prohibited.

Therefore, if the outputs of the corresponding flip-flops 37a to 37f are "0", the first address comparing sections 38a to 38f transmit the 19-bit address data held in the address registers 36a to 36f and the bit synchronization circuit 41. The received address data input through the EX OR circuit 51 is compared and compared with each other. If the received address data does not match, the counter 52 is counted up by a “1” signal output from the EX OR circuit 51. In this way, the first address comparing units 38a to 38f count the number of data mismatch bits, output the counted number to the address second comparing units 45a to 45f, and check whether the number of data mismatch bits is 2 bits or less. Whether it is or not is transmitted to the timing control circuit 31 through the illustrated signal line. The above-mentioned address second comparing sections 45a-4
Details of 5f will be described later.

The output signals of the flip-flops 37a to 37f are input to the address second comparison units 45a to 45f as operation control signals, and the check bit data generated by the check bit generation circuit 40 is input to the AND circuits 46a to 46f. Respectively. The AND circuits 46a to 46f are:
Gate signals G1 to G6 output from the timing control circuit 31
Is controlled by Also, the address second comparing units 45a to 45f
The outputs of a counter circuit 47 for generating function bits and an exclusive OR circuit (hereinafter abbreviated as an EX OR circuit) 48 are provided to the input terminal. The counter circuit 47 constitutes a quaternary counter by flip-flops 47a and 47b, and its output signal is input to the address second comparators 45a to 45f directly and via the EX OR circuit 48.

When the output signals of the corresponding flip-flops 37a to 37f are "0", the address second comparing units 45a to 45f check the check bit data supplied via AND circuits 46a to 46f, the counter circuit 47, and the EX OR. The signal from the circuit 48 is synthesized and compared with the data of the 20th to 32nd bits of the address code word held in the shift register 42 to count the number of data mismatch bits.
It is determined whether or not the total value of the number of data mismatch bits obtained in .about.38f is 2 bits or less, and if it is 2 bits or less, a match detection signal is output to the detection address output unit 49. The detected address output unit 49 is provided as an address second comparing unit.
The match detection signals from 45a to 45f are output to the timing control circuit 31. When the timing control circuit 31 receives the coincidence detection signal from the detection address output unit 49, it first supplies an output command signal to the detection address output unit 49. In response to this command, the detection address output unit 49 causes the address second comparison unit 45
a to 45f and 8 input from flip-flops 47a and 47b
The bit data is sent to the CPU 15. When the timing control circuit 31 receives the response signal from the CPU 15, the timing control circuit 31 waits until one message word of message data is stored in the message output buffer 44 and gives an output command. The data for one message word is sent to the CPU 15.

FIG. 5 shows the details of the address second comparators 45a to 45f. Each of the address second comparing units 45a to 45f includes a check bit register 61, a check bit data conversion circuit 62, a comparing circuit 63, a counter 64, and a determining unit 65. The check bit register 61, the counter 64, and the determining unit 65
Output terminals of the flip-flops 37a to 47f are input to the reset terminal R. The check bit register 61 stores 11
In a bit configuration, check beet data sent from the check bit generation circuit 40 is serially input, and each bit output is sent to the check bit data conversion circuit 62. The conversion circuit 62 includes EX OR circuits 62a to 62k,
The bit output of the check bit register 61 is input to one input terminal of each of the EX OR circuits 62a to 62k, and the output of the counter circuit 47 and the output of the EX OR circuit 48 are input to the other input terminals. . That is, the counter circuit
The output of flip-flop 47a constituting 47 is EX OR circuit 6
2a, 62h, 62k, the output of the flip-flop 47b is connected to the EX OR circuit 62c, 62f, 62i, and the output of the EX OR circuit 48 is set to the EX OR circuit 62.
b, 62e, 62g, and 62j. “0” is input to the other input terminal of the EX OR circuit 62d. The output signals of the EX OR circuits 62a to 62k are flip-flops 47a and 47b.
Is sent to the comparison circuit 63 together with the output signal of This comparison circuit
In 63, 20 of the reception address code from the shift register 42 is stored.
~ 32 data is input and the timing control circuit
A comparison timing signal is input from 31. In this case, the comparison timing signal input to the comparison circuit 63 also
The gates may be controlled by signals obtained by inverting the outputs of the flip-flops 37a to 37f. The comparison circuit 63
When the comparison timing signal is given, the check bit data conversion circuit 62 outputs the shift register 42 as output data.
, And counts up the counter 64 by the number of data mismatch bits. The count value of the counter 64 is sent to the determination unit 65. Also, the determination unit 65 determines whether the total value of the number of data mismatch bits transmitted from the address unit 1 comparison units 38a to 38f and the count value of the counter 64 is 2 bits or less,
If it is 2 bits or less, a match detection signal is output to the detection address output unit 49.

Next, the operation of the above embodiment will be described. When the manual switch SW1 shown in FIG. 1 is turned on, the operating power is supplied to the decoder unit 13. On the other hand, the CPU 15 detects that the switch SW1 is turned on, and detects the timing control circuit 31 in the decoder unit 13.
To output the initialization command signal. Timing control circuit 31
Upon receiving this initialization command signal, it gives a start command to the ID-ROM control decoder 32, sets the control command (output of the terminal O9) to "1", switches the address registers 36a to 36f to a serial connection, and Data can be taken into the registers 36a to 36f and the flip-flops 37a to 37f.

Then, by the activation of the ID-ROM control decoder 32, I
From the D-ROM 14, storage data, that is, first to sixth address data each having a 19-bit configuration, first and second frame data each having a 4-bit configuration, and retry number data having a 3-bit configuration are read out in series. Terminal of timing control circuit 31
The data is stored in the address registers 36a to 36f, the first frame register 33, the second frame register 34, and the retry number register 35 in synchronization with the shift clock output from O2 to O8. At this time, the data of the first bits of the first to sixth address data are also set in the flip-flops 37a to 37f.

The 2nd to 19th bits of each address data correspond to the address bits of the address code word shown in FIG. The first bit of the address data is data indicating whether the address data of the 2nd to 19th bits is valid, that is, whether the address data is set or not. If the data is set, “0” is set. If the data is invalid (address data is not set), “1” is set.

In the frame data set in the first frame register 33 and the second frame register 34, the second to fourth bits indicate the frame number, and the first bit indicates whether or not it is valid as in the case of the address data. Represents. If the first bit of the frame data is “0” (valid), the timing control circuit 31 turns on the electronic switch SW2 to supply power to the receiving unit 12 during a period corresponding to the frame number. In the case of 1 "(invalid), the electronic switch SW2 is kept off. Then, when the call signal transmitted from the base station is received by the receiving unit 12, the received address data is synchronized by the bit synchronization circuit 41, and thereafter,
The address data is input to the first address comparing units 38a to 38f and is compared with the address data held in the address registers 36a to 36f. The coincidence comparison of the address data is performed in parallel.

The timing control circuit 31 includes address registers 36a to 36f
The address data held in the address is read out to the address first comparing sections 38a to 38f in synchronization with the received signal (512 bps in the case of the poxag method), sequentially compared with the received address data in bit units, and the number of mismatches is determined. The counter 62 counts. Since the address word code used in the poxag scheme has BCH (31,21) +1 parity, if the number of unmatched bits is 2 or less at the stage when 32 bits have been compared, it can be regarded as an address match.

Therefore, if the count value of the counter 52 is 2 or less, there is a possibility that the address matches, and the counter 52 outputs a signal to the timing control circuit 31. When the timing control circuit 31 receives a signal indicating that the count value is 2 or less from the counter 52, the corresponding address register 36a
A high-speed shift clock is supplied from terminals O3 to O8 to terminals 36f to 36f to read address data at high speed and send it to the check bit generation circuit 40, and check if the function bit is a specific value, for example, "0""0" A bit, that is, BC
An H check bit (10 bits) and an even parity bit are created, sent to the corresponding address second comparing units 45a to 45f, and stored in the check bit register 61 shown in FIG.

The process of generating the check bits and storing the check bits in the check bit register 61 is sequentially performed when the number of data mismatch bits is detected to be 2 or less in the plurality of address first comparing units. If any one of the address first comparing sections 38a to 38f detects that the number of data mismatch bits is 2 or less, check bits of all six types of address data are generated and the corresponding address second comparing section is generated. The information may be stored in the check bit register 61 of each of the units 45a to 45f.

The data stored in the check bit register 61 is sent to a check bit data conversion circuit 62, where the data is converted. This check bit data conversion circuit 62
Based on the check bit data when the function bits stored in the check bit register 61 are “0” “0”, the function bits are changed to “1” “0”,
This is for outputting check bit data at "0""1" and "1""1". The switching is performed by the quaternary counter circuit 47 and EX OR circuit 48 in FIG. Signal. The data converted by the check bit data conversion circuit 62 is sent to the comparison circuit 63 and is compared with the reception data held in the shift register 42 for matching. Address second comparing units 45a to 45f
Is preferably completed after the 32nd bit of the address code word, that is, the bit data of the even parity, is taken into the shift register 42 and the next bit data is received.

When the even parity bit is taken into the shift register 42, the address second comparing units 45a to 45f
In the comparison circuit 63, first, the function bit is set to “0”
Count the number of data mismatch bits when "0".
In addition, the determination unit 65 determines whether the total count value of the first address comparison units 38a to 38f is 2 or less.

When the total number of mismatched bits is detected to be 2 or less in any of the address second comparing sections 45a to 45f, it is determined that the address data matches the self address, and the matching signal is output from the determining section 65 to the detected address. It is sent to the output unit 49. When the coincidence signal is input, the detection address output unit 49 latches the signals from the six address second comparison units 45a to 45f and the signal from the counter circuit 47 (flip-flops 47a and 47b), It outputs the coincidence detection signal to the timing control circuit 31, maintains the electronic switch SW2 in the ON state, and receives the subsequently transmitted word code.

On the other hand, when no match is detected in the address second comparing units 45a to 45f, the timing control circuit 31 releases the reset signals of the flip-flops 47a and 47b and
The contents of the flip-flops 47a and 47b obtained by applying a clock pulse to the flip-flop 47a of the stage are set to “0” “1”,
That is, the comparison process is performed in the same manner as described above by switching the function data. If no coincidence of the address data is detected, the flip-flops 47a and 47b are sequentially switched to “1” “0” and “1” “1” to perform a match comparison, and the process ends.

When the match detection signal is sent to the timing control circuit 31 by the above-described match comparison processing, the timing control circuit 31 maintains the electronic switch SW2 in the ON state as described above, and at the same time, outputs the output command signal to the detection address output unit 49. Send out. As a result, the detected address output unit 49 sends out a total of 8 bits of data input from the address second comparing units 45a to 45f and the flip-flops 47a and 47b to the CPU 15.

Further, when the response signal is sent from the CPU 15, the timing control circuit 31 outputs the message output to the buffer 44 for one message word of data, that is, 20-bit message data (message word 2 to 21 bit data),
It waits for the flag bit data (the first bit data of the message word) to be stored, adds data indicating whether there is an error to this data, and outputs the data to the CPU 15.

The CPU 15 determines whether or not the flag bit data in the received data is “0” and determines the maximum number of words of the received data permitted by the paging system company, for example, 4 message words in the case of numerical data, and character data. In the case of
It determines whether or not 16 message words have been reached, and outputs a message end detection signal to the timing control circuit 31 when flag bit data "0" is detected and when the maximum number of words of received data is detected, and the reception mode is set. Return to normal intermittent reception mode. That is, the electronic switch SW2 is turned on during the period of the frame to which the synchronization signal SC and the self signal are allocated, and it is checked whether or not the read signal is being transmitted.

In the above embodiment, the end of the message is detected by the CPU 15, but the end of the message is detected by the decoder unit 13, that is, the flag bit "0" is detected by the message output buffer 44, and the maximum number of words is detected. May be detected in the timing control circuit 31. In this case, the message end code detection signal is sent from the decoder unit 13 to the CPU 15
Will be sent out.

[Effects of the Invention] As described above in detail, according to the present invention, in the call detection device for storing address data defining a call to the self and detecting the call by receiving the address data, The identification data for identifying the setting state of the address data is stored in correspondence with the address data, and when the address data is detected, the control is performed to restrict the call detection operation, for example, by prohibiting the call detection operation. In addition, the operation of matching and comparing received address data with address data corresponding to an unset calling number can be prohibited to prevent wasteful power consumption, and a battery can be used for a long time in a paging receiver or the like.

Further, the present invention has a storage unit including address data defining a call to the self, and a call detection device that detects a call by receiving the address data in the storage unit. When the identification data for identifying the setting state of the storage unit is stored, and when the address data is detected, for example, the detection call operation is prohibited, the control is performed so as to control the call operation. The operation of matching the received address data with the address data corresponding to the calling number is prohibited, so that unnecessary power consumption can be prevented, and the battery can be used for a long time in a paging receiver or the like.

Further, the present invention has a storage unit including address data defining a call to the self, in a call detection device that performs a call detection by receiving the address data in the storage unit, corresponding to the storage unit, When identification data for identifying a setting state of the storage unit is stored, for example, when the identification data is data indicating invalidity of frame data in the corresponding storage unit, address data at a timing defined by the frame data is stored. Is configured to stop receiving data at the timing specified by the frame data corresponding to the unset call number. It can be used.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention. FIG. 1 is a block diagram showing the overall configuration, FIG. 2 is a data configuration diagram for explaining the outline of the Poxag system, and FIG. FIG. 4 is a block diagram showing details of a decoder unit, FIG. 4 is a block diagram showing details of an address first comparison unit in FIG. 3,
FIG. 5 is a block diagram showing details of the address second comparing section in FIG. 12 ... receiving unit, 19 ... decoder unit, 14 ... ID-ROM, 15
…… CPU, 16 …… DC power supply, 17 …… Message memory, 1
9 speaker, 21 LED, 31 timing control circuit, 32 ID-ROM control decoder, 36a to 36f address register, 37a to 37f flip-flop, 38a to 38f
... Address first comparator 40, check bit generation circuit 42, shift register 44, message output buffer 45a to 45f address second comparator 47, counter circuit 48, EX OR circuit, 49 ... Detection address output unit, 52 ... Counter, 61 ... Check bit register,
62: check bit data conversion circuit, 63: comparison circuit, 64: counter, 65: determination unit.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04B 7/24-7/26 H04Q 7/00-7/38 H04M 1/00 H04M 1/56-1/57 H04M 1 / 66-1/78

Claims (5)

(57) [Claims] 1. A call detection device, comprising: storage means for storing address data for defining a call to the user, and performing call detection by comparing received address data with address data stored in the storage means. In the device, corresponding to the address data stored in the storage means,
Identification data storage means for storing identification data for identifying the setting state of the address data; and control means for controlling a call detection operation based on the identification data corresponding to the address data targeted for the call detection. A call detection device characterized by the above-mentioned. 2. The call detection device according to claim 1, wherein the identification data is data for restricting a call detection operation based on address data corresponding to the identification data. 3. A call detecting apparatus comprising: a storage unit having a storage unit including address data defining a call to the self unit, and performing a call detection by comparing the received address data with the address data in the storage unit. An identification data storage unit for storing identification data for identifying a setting state of the storage unit corresponding to the storage unit; and an identification data corresponding to a storage unit including address data targeted for call detection. And control means for controlling a call detection operation based on the call. 4. The call detection device according to claim 3, wherein the identification data is data for restricting a call detection operation based on address data contained in a storage unit corresponding to the identification data. 5. The apparatus according to claim 3, wherein the identification data is data for stopping reception of address data at a timing defined by frame data included in a storage unit corresponding to the identification data. Call detection device.