JP3983026B2 - Information processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to power saving in an information processing apparatus.
[0002]
[Prior art]
  In recent years, with the spread of portable small computers and the like, power saving of information processing apparatuses including a CPU and its peripheral devices has become an important issue for extending battery life.
  As a general power saving method for an information processing apparatus, when an idle state in which the CPU is not in particular working for a predetermined time, such as a waiting state for key input, is detected for a predetermined time, the CPU is switched to a power saving mode. There is something to migrate. This power saving mode is a standby state (interrupt standby state) that waits for the input of a predetermined interrupt signal. When the interrupt signal is detected, the circuit is not connected to a circuit (component) other than the minimum necessary to return to the original state. The power supply is in a stopped state.
  For the purpose of minimizing power consumption in the power saving mode, Japanese Patent Application Laid-Open No. 7-121259 discloses that when the CPU idle state is detected, the CPU shifts to an interrupt standby state (power saving mode). , Those that stop the clock signal to the CPU and shift to other power saving modes (such as stopping the control circuit) of other peripheral devices (such as a hard disk drive) have been proposed. As a result, the information processing apparatus as a whole can be reduced in power consumption.
  By the way, when the CPU is shifted to the power saving mode and the peripheral devices such as ROM and RAM are also shifted to the power saving mode such as circuit stop at the same time, in order to further reduce power consumption, the CPU is switched to the power saving mode. It is necessary to ensure that the ROM and RAM can be accessed until the transition of the above is completed. Otherwise, since the CPU accesses peripheral devices such as ROM and RAM even during the transition to the power saving mode, it cannot normally shift to the power saving mode. Furthermore, there is a case in which the order of shifting to the power saving mode may have to be taken into consideration between peripheral devices, for example, when there is a peripheral device that accesses the RAM, which is another peripheral device, when shifting to the power saving mode. .
  The above is the same when returning from the power saving mode to the original state. For example, if the CPU recovers before the access to the ROM or RAM is guaranteed and the process is resumed, there is a problem that normal operation cannot be guaranteed. In particular, in recent information processing devices, a PLL (Phase Locked Loop) circuit is used as a control circuit for CPUs and peripheral devices for speeding up.Built-inHowever, many of them are operated in synchronism with a clock having the same phase, and this problem becomes remarkable. In other words, since the PLL requires a long time in ms until the output is stabilized after the clock input is started, the peripheral device operated by the clock output of the PLL is accessed until the clock output is stabilized. Therefore, normal operation cannot be guaranteed.
[0003]
[Problems to be solved by the invention]
  However, the technique disclosed in the above publication does not have means for controlling the order of transition to the power saving mode and return to the original state between the CPU and peripheral devices, such as the ROM and RAM. When the peripheral device is also shifted to the power saving mode or operates using the PLL, there is a problem that the transition to the power saving mode and the return to the original state cannot be performed normally. there were.
  Further, in the technique disclosed in the above publication, in order to output a signal indicating that the CPU is in an idle state to the peripheral device side, it is necessary to provide an output line or the like separately from the existing interface such as a bus to the CPU. There is also a problem in that the CPU characteristic that it can flexibly cope with a change in the system configuration is lost.
  Accordingly, the present invention has been made in view of the above circumstances, and its object is to provide a power saving mode between a CPU and peripheral devices.FromAn object of the present invention is to provide an information processing apparatus that can control the order of return to the original state and can flexibly cope with changes in the system configuration.
[0004]
[Means for Solving the Problems]
  To achieve the above objectiveBookThe inventionWhen the CPU and one or more peripheral devices are connected to the CPU via a predetermined bus and the peripheral device is in a predetermined power saving mode, based on the input of a predetermined return interrupt signal And a peripheral device control means for controlling the peripheral device to return from the power saving mode, wherein the peripheral device control means has a predetermined power saving mode return time after inputting the return interrupt signal. After the elapse of time, the peripheral device is returned from the power saving mode, and a return interrupt mask instruction that does not cause the peripheral device control means to return from the power saving mode according to the return interrupt signal is sent to the bus. A return interrupt mask register provided so as to be set via the peripheral device, and the peripheral device is controlled by the peripheral device control means. Forced return instruction to al forcibly return the information processing apparatus characterized by a power saving mode forced return registers provided so as to be set via the bus formed by comprising for each said peripheral deviceIt is.
Thus, if the power saving mode return time is appropriately set for each peripheral device, the return order from the power saving mode between the peripheral devices can be controlled.
In addition, by setting the return interrupt mask instruction, it is possible to cope with peripheral devices that do not want to return from the power saving mode in conjunction with the CPU. The forced return instruction allows the peripheral device to be put out of the power saving mode at any timing. Can be restored.
  In addition, access to peripheral devices from the CPU.IsSince it is performed via a bus provided in the CPU as a standard, it is not necessary to provide a special signal line or the like, and the characteristic of the CPU that can flexibly cope with a change in system configuration is not impaired..
[0005
  It is also possible to have a power saving mode return timer setting register provided so that the power saving mode return time for each of the peripheral devices can be set via the bus.
  This makes it easy to change the time information in the power saving return timer setting register from the CPU or the like even when the order of returning from the power saving mode between peripheral devices changes due to a change in the system configuration or the like. It becomes possible to cope with.
[0006
  The internal interrupt signal generating means for generating a predetermined internal interrupt signal under predetermined conditions for each of the peripheral devices, and when the internal interrupt signal and an external interrupt signal input from the outside are input It is also conceivable to include return interrupt signal generation means for generating a return interrupt signal.
  As a result, the trigger for returning from the power saving mode can be generated not only by an external interrupt signal but also by the condition of the peripheral device. For example, in a peripheral device that is a communication interface with an external device, when a communication input from the external device occurs, the internal interrupt signal can be generated to return from the power saving mode.
[0007]
  In addition, for the return interrupt signal generation means, for each of the internal interrupt signal and the external interrupt signal,IgnoreAn internal / external interrupt mask register provided so that an internal / external interrupt mask instruction can be set via the bus is also conceivable.
  As a result, it is possible to select whether to return from the power saving mode in response to the internal interrupt signal from any of the peripheral devices, thereby increasing flexibility..
[0008]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that the present invention can be understood. The following embodiment is an example embodying the present invention, and does not limit the technical scope of the present invention.
  FIG. 1 is a block diagram showing the configuration of the information processing apparatus X according to the embodiment of the present invention, and FIG. 2 is a configuration example of a peripheral device control circuit configuring the information processing apparatus X according to the embodiment of the present invention. FIG. 3 is a block diagram showing a configuration example of an interrupt control circuit constituting the information processing apparatus X according to the embodiment of the present invention. FIG. 4 shows the information processing apparatus X according to the embodiment of the present invention. FIG. 5 is a block diagram showing a configuration example of the clock control circuit 16 to be configured, FIG. 5 is a flowchart showing a procedure for shifting to the power saving mode in the information processing apparatus X according to the embodiment of the invention, and FIG. 6 is an embodiment of the invention. It is a flowchart showing the return procedure from the power saving mode in the information processing apparatus X concerning.
[0009]
  First, the configuration of the information processing apparatus X according to the embodiment of the present invention will be described with reference to FIG.
  The information processing apparatus X includes a CPU 11, a clock control circuit 16, an interrupt control circuit 14, and a plurality of peripheral device control circuits 131, 132,... Are connected by 1821, 1822, 1823,... (That is, connected to the CPU 11 via the system bus 181), and the high-speed transmitter 151 and the low-speed transmitter 152. It is configured.
  The CPU 11 performs various arithmetic processes in accordance with programs and data acquired from the peripheral devices 121, 122,... Such as ROM, RAM, and keyboard, and the calculation results are sent to the peripheral devices 121, 122,. Output. Data is exchanged with the peripheral devices 121, 122,... Via the system bus 181. When the CPU 11 enters the idle state due to waiting for input from the keyboard or the like, the CPU 11 automatically shifts to the power saving mode and enters the interrupt standby state, and a predetermined interrupt signal (in this embodiment, a delayed interrupt signal described later). ) Is automatically restored to the original state (such as the CPU described in the above publication). Further, the CPU 11 operates the PLL 111 for operating at high speed in synchronization with a clock having the same phase as the peripheral devices 121, 122,... Based on the high-speed clock signal 1711 from the high-speed transmitter 151.Built-inis doing. In order to achieve this synchronization, a PLL 161 is also incorporated in the clock control circuit 16 described later, and the peripheral devices 121, 122,... Operate based on a main clock signal 1721 generated by the PLL 161.
[0010]
  Next, the configuration of the peripheral device control circuits 131, 132,... Will be described with reference to FIG. For convenience, the numbers in FIG. 2 are numbered corresponding to one of the peripheral device control circuits (131), but the same applies to the other peripheral device control circuits 132, 133,.
  The peripheral device control circuit 131 controls the peripheral device 121 connected by a control line 1821 and has the following components.
  That is, five registers (temporary storage devices) connected to the system bus 181 are a power saving mode transition control register 13141, a power saving mode transition timer setting register 13142, a power saving mode return timer setting register 13143, and a power saving mode forced. Return register 13144, interrupt mask register 13151, peripheral device main control circuit 1311 also connected to the system bus 181, power saving mode transition timer circuit 13145, power saving mode return timer circuit 13146, interrupt mask circuit 13152, main clock A mask circuit 1313 and a power saving mode control circuit 1312 are included.
  The five registers 13141 to 13144 and 13151 are accessed by the CPU 11 via the system bus 181 to set various information.
  The peripheral device main control circuit 1311 controls the peripheral device 121 according to a control command from the CPU 11 via the system bus 181 and a control signal 1318 from the power saving mode control circuit 1312. Other functions of each component will be described later.
[0011]
  Next, the configuration of the interrupt control circuit 14 will be described with reference to FIG.
  The interrupt control circuit gives the CPU 11, the clock control circuit 16, and the peripheral device control circuits 131, 132,... A timing for returning from a state in which the interrupt control circuit has shifted to a predetermined power saving mode to the original state. An interrupt signal to be notified (a return interrupt signal 193 and a delayed interrupt signal 194, which will be described later) is generated, and has the following components.
  That is, an interrupt mask register 142 and an interrupt delay timer setting register 144 which are two registers connected to the system bus 181 and an external interrupt mask circuit for inputting an external interrupt signal 191 input from the outside of the information processing apparatus X. , The internal interrupt mask circuits 1432, 1433,..., The return interrupt generation circuit 141, and the interrupt delay timer circuit 145 that receive the internal interrupt signals 1921, 1922,... Output from the peripheral device control circuits 131, 132,. It consists of and.
  The external and internal interrupt mask circuits 1431, 1432,... Are connected to be able to read information set in the interrupt mask register 142.
  The two registers 142 and 144 are accessed by the CPU 11 via the system bus 181 to set various information. Other functions of each component will be described later.
[0012]
  Next, the configuration of the clock control circuit 16 will be described with reference to FIG.
  The clock control circuit 16 receives a high-speed clock signal 1711 and a low-speed clock signal 1712 that are outputs of the high-speed oscillator 151 and the low-speed oscillator 152, and a main clock signal 1721 having the same phase as the clock used by the CPU 11. Are generated when the peripheral device control circuits 131, 132,... Are in the power saving mode state, and do not require synchronization with the CPU 11, and the peripheral devices 121, 122,. It has the following components.
  That is, three registers connected to the system bus 181 are a main clock stop control register 1631, a main clock stop timer setting register 1632, a main clock return timer setting register 1641, a main clock stop timer circuit 1633, and a main clock return. The timer circuit 1642, the high-speed clock control circuit 1621, the PLL 161, the main clock control circuit 1622, and the sub clock selection circuit 165 are configured.
  The sub clock selection circuit 165 is a circuit for switching which one of the high-speed clock signal 1711 and the low-speed clock signal 1712 is output as the sub-clock signal 1722 with a switch or the like. The circuit 165 determines which one is selected as the sub clock signal 1722, and is unnecessary when there is no need for switching.
  The three registers 1631, 1632, and 1641 are accessed by the CPU 11 via the system bus 181 to set various information. Other functions of each component will be described later.
[0013]
  Next, an operation procedure in which the CPU 11 and other devices shift to the power saving mode when the CPU 11 enters the idle state will be described with reference to FIG. Hereinafter, S101, S102, and the like represent operation procedure (step) numbers.
  First, when the CPU 11 enters the idle state, the peripheral devices 121, 122,... That are similarly shifted to the power saving mode in conjunction with the transition to the power saving mode are connected to the CPU 11. The power saving mode shift control register 13141 of each peripheral device control circuit 131, 132,... Is accessed via the system bus 181 to notify that it shifts to the power saving mode (S101). As a result, the operation of shifting the peripheral device control circuits 131, 132,... Described later to the power saving mode is started. Information about which of the peripheral devices 121, 122,... Is transferred to the power saving mode is registered in advance in storage means such as a nonvolatile RAM that is one of the peripheral devices 121, 122,. This is read by the CPU 11. (Hereinafter, the information registered in advance in the storage means such as the nonvolatile RAM will be referred to as information registered in advance in the CPU 11 for the sake of simplicity.)
[0014]
  Next, whether or not it is impossible to stop the supply of the main clock signal 1721 to the peripheral device control circuits 131, 132,... Is determined based on the judgment information (“stop impossible” / “stop possible” )) Is determined (S102).
  Each of the peripheral devices 121, 122,... Includes those that require the main clock signal 1721 (such as an external communication interface) and those that do not need (such as a hard disk) even in the state of shifting to the power saving mode. Since the discriminating information may exist, the discriminating information may be “cannot be stopped” when one of the peripheral devices 121, 122,... Requires the main clock signal 1721 in the power saving mode. Otherwise, it is stored as “Can stop”.
  If it is determined in S102 that the main clock signal 1721 is “stoppable”, the CPU 11 accesses the main clock stop control register 1631 of the clock control circuit 16 and stops the main clock signal 1721. After being notified (S103), the process proceeds to S104.
  On the other hand, if it is determined in S102 that the main clock signal 1721 is “cannot be stopped”, the process proceeds to S104 as it is.
  In S104, after the CPU 11 itself shifts to the power saving mode (interrupt standby state), the shift operation to the power saving mode in the CPU 11 ends.
[0015]
  By the way, only the CPU 11 can notify the peripheral devices 121, 122,... That the CPU 11 is in the idle state (S101, S03), and the system is the standard input / output means for the notification. In order to perform via the bus 181, the CPU 11 must be operating (before transition to the power saving mode). Nevertheless, when the CPU 11 shifts to the power saving mode (S104), since the CPU 11 reads a predetermined program, the peripheral devices 121, 122,. The peripheral device 121, 122,... Needs to be shifted to the power saving mode after the CPU 11 has completely shifted to the power saving mode.
  In order to solve this problem, the feature of the present invention is that a timer circuit is provided for each of the peripheral devices 121, 122,..., And the CPU 11 receives a notification of transition to the power saving mode (access to a register), and then The CPU 11 shifts the peripheral devices 121, 122, etc. to the power saving mode after the time required for the CPU 11 to shift to the power saving mode.
  Hereinafter, the transition operation to the power saving mode in the peripheral device control circuits 131, 132,... And the clock control circuit 16 having the above characteristics will be described with reference to FIG.
[0016]
  In the peripheral device control circuits 131, 132,... (FIG. 2), the CPU 11 confirms the contents of the power saving mode transition control register 13141 by the power saving mode transition timer circuit 13145 (S111). It is in a standby state until there is an access (notification) (S112 → S111). When access from the CPU 11 is detected (Yes in S112), time information is read from the power saving mode transition timer setting register 13142 by the power saving mode transition timer circuit 13145 (S113). The time information is a waiting time until the peripheral devices 121, 122,... Connected to the peripheral device control circuits 131, 132,. Hereinafter, the information registered in the CPU 11 in advance is set in advance from the CPU 11 via the system bus 181 when the information processing apparatus X is started up. .
[0017]
  The power saving mode transition time is set to be equal to or longer than the time required for the CPU 11 to transition to the power saving mode, and the relationship with other peripheral devices 121, 122,. In the peripheral devices 121, 122,..., A ROM or a RAM, which is one of the peripheral devices 121, 122,... When shifting to the power saving mode, such as a PCI bus controller, for example. In this case, for the ROM, RAM, etc., which are accessed, the power saving mode transition time is set longer than the peripheral devices 121, 122,. .
[0018]
  Next, when the power saving mode transition timer circuit 13145 starts timing and the power saving mode transition time has elapsed, a power saving mode transition signal 13165 is output to the power saving mode control circuit 1312 (S114). .
  Next, the power saving mode control circuit 1312 to which the power saving mode transition signal 13165 is input causes the main clock mask circuit 1313 and the peripheral device main control circuit 1311 to pause the peripheral devices 121, 122,. A mode control signal 1318 indicating that is output (S115).
  Further, after the connected peripheral devices 121, 122,... Are controlled to shift to the power saving mode by the main clock mask circuit 1313 and the peripheral device main control circuit 1311 to which the mode control signal 1318 is input. (S116), the operation of shifting to the power saving mode in the peripheral device control circuits 131, 132,.
  Here, the main clock mask circuit 1313 and the peripheral device main control circuit 1311 are individually configured according to the peripheral device 121 to be connected. For example, when the corresponding peripheral device 121 does not require the main clock signal 1721 in the power saving mode, the main clock mask circuit 1313 receives the mode control signal 1318 from the peripheral device 121. Is a signal indicating that the main clock signal 1721 is suspended, the supply of the main clock signal 1721 to the peripheral device 121 is cut off.
[0019]
  As described above, the peripheral devices 121, 122,... Are controlled so as to shift to the power saving mode after the set time has elapsed after receiving the notification from the CPU 11 (S111). The order of transition to the power saving mode can be controlled between the CPU 11 and the other peripheral devices 121, 122,... Depending on the set time, and the transition to the power saving mode can be ensured.
  Further, since the notification from the CPU 11 to the peripheral devices 121, 122,... Is performed via the system bus 181 provided as a standard, there is no need to provide a special output line or the like. There is no loss of flexible scalability.
  Further, since the power saving mode transition time can be set via the system bus 181, even when the configuration of the peripheral devices 121, 122,... Is changed, for example, the time stored in the nonvolatile RAM is changed. Therefore, it is possible to make the information processing apparatus more flexible.
[0020]
  On the other hand, in the clock control circuit 16 (FIG. 4), the main clock stop timer circuit 1633 confirms the contents of the main clock stop control register 1631 (S121) until there is an access from the CPU 11. It is in a standby state (S122 → S121). When access from the CPU 11 is detected (Yes in S122), time information is read from the main clock stop timer setting register 1632 by the main clock stop timer circuit 1633 (S123). The time information is a waiting time (hereinafter, referred to as the time until the clock control circuit 16 is shifted to the power saving mode) after the access from the CPU 11 until the supply of the main clock signal 1721 is stopped. The information registered in advance in the CPU 11 is preset from the CPU 11 via the system bus 181 when the information processing apparatus X is started up.
  The main clock stop mode transition time is set to a time longer than the longest time among the power saving mode transition times in the peripheral device control circuits 131, 132,... (FIG. 2).
[0021]
  Next, when the main clock stop timer circuit 1633 starts timing and the main clock stop mode transition time has elapsed, a main clock stop signal 1673 is output to the high-speed clock control circuit 1621 and the main clock control circuit 1622. (S124).
  Furthermore, after the high-speed clock control circuit 1621 and the main clock control circuit 1622 to which the main clock stop signal 1673 is input, the supply of the high-speed clock 1711 to the PLL 161 and the output of the main clock 1721 are stopped ( S125), the operation of shifting to the power saving mode in the clock control circuit 16 ends.
  In this way, after receiving the notification from the CPU 11 (S121), the output of the main clock 1721 is stopped after a lapse of a predetermined time, so that the peripheral devices 121, 122,... Shift to the power saving mode. During the operation, the main clock 1721 is not stopped, and the power saving mode can be reliably transferred.
[0022]
  Next, referring to FIG. 6, the CPU 11, the clock control circuit 16, and the peripheral devices 121, 122,... Serve as an operation procedure for returning from the power saving mode to the original state and a return trigger. An operation procedure of the interrupt control circuit 14 for generating a signal will be described.
  First, in the interrupt control circuit 14 (FIG. 3), the contents of the interrupt mask register 142 are confirmed by the external interrupt mask circuit 1431 and the internal interrupt mask circuits 1432, 1433,... If it corresponds to the internal / external interrupt mask instruction, it is read (S201). The mask command is set in advance by the CPU 11 via the system bus 181 when the information processing apparatus X is activated, and the external and internal interrupt signals 191, 1921, 1922,. Only those that ignore the input are set. As a result, what is used as a trigger for return and what is not used can be arbitrarily set, so that it becomes more flexible.
  Further, by the external and internal interrupt mask circuits 1431, 1432,..., A predetermined external interrupt signal 191 inputted from outside the information processing apparatus X and the peripheral device main control in the peripheral device control circuits 131, 132,. The input of predetermined internal interrupt signals 1921, 1922,... Generated by the circuit 1311 is confirmed (S202). These interrupt signals 191, 1921, 1922,... Are signals that serve as triggers for returning from the power saving mode.
  As an example of the internal interrupt signal 1921, a signal generated when there is a key input or a communication input from the external device when the peripheral devices 121, 122,... Are communication devices with a keyboard or an external device. Etc. The peripheral device main control circuit 1311 that generates the internal interrupt signals 1921, 1922,... Is individually configured according to the characteristics of the corresponding peripheral devices 121, 122,.
  The external and internal interrupt mask circuits 1431, 1432,... Ignore the input of the external and internal interrupt signals 191, 1921, 1922. The predetermined signals 1471, 1472,... Are output to the return interrupt generation circuit 141 only when the external and internal interrupt signals 191, 1921, 1922,.
[0023]
  Next, whether or not the external interrupt signal 191, 1921, 1922,... For which the mask instruction is not set is input by the return interrupt generation circuit 141 (that is, the external and internal interrupt mask circuits 1431, 1432,. (Presence / absence of predetermined signals 1471, 1472,... From 1433,...) Is checked (S203). If there is no input, the process returns to S201 and the above-described operations are repeated (S201 to S203).
  On the other hand, if any one of the external and internal interrupt signals 191, 1921, 1922,... For which the mask instruction is not set is input by the return interrupt generation circuit 141 (Yes in S203) , A predetermined return interrupt signal 193 is generated and output to the clock control circuit 16, the peripheral device control circuits 131, 132,... And the interrupt delay timer circuit 145 (S204). The return interrupt signal 193 is a trigger, and the clock control circuit 16 and the peripheral device control circuits 131, 132,... Enter the return operation from the power saving mode. These return operations will be described later.
  Next, a predetermined delay time (hereinafter referred to as a return interrupt signal delay time) is read from the interrupt delay timer setting register 144 by the interrupt delay timer circuit 145 to which the return interrupt signal 193 is input, and the return interrupt signal is output. A delayed interrupt signal 194 (corresponding to the delayed interrupt signal), which is a signal obtained by delaying the signal 193 by the return interrupt signal delay time, is generated and output to the CPU 11 (S206), and then the interrupt control circuit 14 returns. The operation ends. The CPU 11 returns from the power saving state to the original state by the input of the delay interrupt signal 194.
  The return interrupt signal delay time is at least longer than the time required for the peripheral devices 121, 122,... Accessed when the CPU 11 returns from the power saving mode to the original state to return from the power saving mode. Is set. As a result, the CPU 11 can return to the peripheral devices 121, 122,... Normally without being accessed before the return is completed.
[0024]
  On the other hand, in the clock control circuit 16 (FIG. 4), the main clock recovery timer circuit 1642 and the high-speed clock control circuit 1621 receive the recovery interrupt signal 193 generated by the interrupt control circuit 14 (FIG. 3). When waiting (S221, S222) and the return interrupt signal 193 is input (Yes in S222), the high-speed clock control circuit 1621 returns the output of the high-speed clock signal 1711 to the PLL 161 ( S223). As a result, the PLL 161 returns from the stopped state to the operating state.
  Next, time information is read from the main clock recovery timer setting register 1641 by the main clock recovery timer circuit 1642 (S224), and a main clock recovery signal is sent to the main clock control circuit 1622 after the waiting time has elapsed. 1672 is output (S225). Further, when the main clock return signal 1672 is input, the main clock control circuit 1622 outputs the main clock signal 1721 that is an output signal of the PLL 161 (the interrupt control circuit 14 and the peripheral device control circuit 131, (Supply to 132,...) Is restored (S226), the restoration operation of the clock control circuit 16 is completed.
  The time information set in the main clock return timer setting register 1641 is from the input of the return interrupt signal 193 until the supply of the main clock signal 1721 is resumed (that is, the clock control circuit 16 is set to the time information). Wait time (hereinafter referred to as main clock stop mode return time), and information registered in advance in the CPU 11 is transferred from the CPU 11 to the information processing apparatus X when the information processing apparatus X is started up. It is set in advance via the system bus 181. The recovery time of the main clock stop mode is set to be longer than the time required until the main clock signal 1721 that is the output of the PLL 161 is stabilized after the output of the main clock 1711 to the PLL 161 is restarted. As a result, it is possible to prevent the peripheral devices 121, 122,... From malfunctioning when the main clock signal is supplied to the peripheral devices 121, 122,.
[0025]
  On the other hand, in the peripheral device control circuits 131, 132,... (FIG. 2), the content of the power saving mode forced return register 13144 is confirmed by the power saving mode control circuit 1312 (S211), and a predetermined forcing described later is performed. If no return instruction is set (No in S212), the interrupt mask circuit 13152 confirms the contents of the interrupt mask register 13151, and a predetermined return interrupt mask instruction (corresponding to the return interrupt mask instruction). Is set, it is read (S213).
[0026]
  Further, the interrupt mask circuit 13152 confirms the input of the return interrupt signal 193 output from the interrupt control circuit 14 (S214). The return interrupt signal 193 serves as a trigger for the peripheral device control circuits 131, 132,... To return from the power saving mode.
  The interrupt mask circuit 13152 is configured to output a predetermined signal 13172 to the power saving mode return timer circuit 13146 only when the return interrupt mask instruction is not set in the interrupt mask register 13151. That is, when the return interrupt mask command is set, the input of the return interrupt signal 193 is ignored.
[0027]
  Next, whether or not the return interrupt signal 193 is input when the return interrupt mask command is not set by the power saving mode return timer circuit 13146 (that is, whether or not the predetermined signal 13172 from the interrupt mask circuit 13152 is present). ) Is checked (S215), and if there is no input, the process returns to S211 and the above-described operation is repeated (S211 to S215).
  On the other hand, when the return interrupt signal 193 is input when the return interrupt mask command is not set (Yes in S215), the power saving mode return timer 13146 causes the power saving mode return timer circuit 13146 to Predetermined time information is read from the setting register 13143 (S216). As the time information, after the return interrupt signal 193 is input, the peripheral devices 121, 122,... Connected to the peripheral device control circuits 131, 132,. This is a waiting time until recovery (hereinafter referred to as power saving mode recovery time), and information registered in advance in the CPU 11 is preset via the system bus 181 when the information processing apparatus X is started up. Is. The power saving mode return time is set so that the return order is correct between the clock control circuit 16 and the other peripheral device control circuits 131, 132,..., Similarly to the power saving mode transition time.
[0028]
  Next, when the power saving mode return timer circuit 13146 starts timing and when the power saving mode return time has elapsed, a power saving mode return signal 13166 is output to the power saving mode control circuit 1312 ( S217).
  Next, the power-saving mode control circuit 1312 to which the power-saving mode return signal 13166 has been input causes the main clock mask circuit 1313 and the peripheral device main control circuit 1311 to return the peripheral devices 121, 122,. A mode control signal 1318 indicating that is output (S218).
  Further, the connected peripheral devices 121, 122,... Are restored from the power saving mode to the original state by the main clock mask circuit 1313 and the peripheral device main control circuit 1311 to which the mode control signal 1318 is input. After being controlled (S219), the return operation from the power saving mode in the peripheral device control circuits 131, 132,.
[0029]
  On the other hand, when the forced return command is set in the power saving mode forced return register, and this is read by the power saving mode control circuit 1312 (Yes in S212), the above is executed regardless of other conditions. A mode control signal 1318 indicating that the peripheral devices 121, 122,... Are restored is output by the power saving mode control circuit 1312 (S218), and the main clock mask circuit 1313 and the peripheral device main control circuit 1311 connect them. Are controlled to return to the original state from the power saving mode (S219).
  The return interrupt mask instruction is preset for each of the peripheral device control circuits 131, 132,... By the CPU 11 via the system bus 181 and ignores the input of the return interrupt signal 193. Only set. By setting the return interrupt mask instruction and accessing the power saving mode forced return register, the peripheral devices 121, 122,... Can be moved from the CPU 11 without interlocking with the return of the CPU 11 from the power saving mode. It can be returned at any timing. For example, for the peripheral devices 121, 122,... That are not always used, such as a hard disk, the return interrupt mask command is set, and the power saving mode is forced when the CPU 11 needs to be accessed after returning. Power saving can be achieved by performing control to access and return the return register 13144.
[0030]
【The invention's effect】
  As described above, according to the present invention, the power saving mode between the CPU and the peripheral device is set.FromSince it has means to control the order of return to the original state,FromPeripheral devices such as ROM and RAM accessed when returning to the original stateofPower saving modeFromIt is possible to return to the original state normally. As a result, further power saving can be achieved.Furthermore, it is possible to cope with peripheral devices that do not want to return from the power saving mode in conjunction with the CPU, and the peripheral devices can be returned from the power saving mode at any timing.
  Power saving modeFromSince the order of returning to the original state can be changed simply by resetting the time information in the registers connected to the bus, it is possible to flexibly respond to changes in the system configuration, etc. Become.
  In addition, the CPU is connected to the peripheral device.DoSince the notification is performed via a standard bus, there is no need to provide an output line or the like, and the CPU feature that can flexibly cope with a change in the system configuration is not lost.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an information processing apparatus X according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration example of a peripheral device control circuit configuring the information processing device X according to the embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration example of an interrupt control circuit included in the information processing apparatus X according to the embodiment of the present invention.
4 is a block diagram illustrating a configuration example of a clock control circuit 16 included in the information processing apparatus X according to the embodiment of the present invention. FIG.
FIG. 5 is a flowchart showing a procedure for shifting to a power saving mode in the information processing apparatus X according to the embodiment of the present invention.
FIG. 6 is a flowchart showing a return procedure from the power saving mode in the information processing apparatus X according to the embodiment of the present invention.
[Explanation of symbols]
11 ... CPU
14 ... Interrupt control circuit
16: Clock control circuit
111, 161 ... PLL (Phase Locked Loop)
121, 122, ... peripheral devices
131, 132,... Peripheral device control circuit
141: Return interrupt generation circuit
142: Interrupt mask register
144: Interrupt delay timer setting register
145 ... Interrupt delay timer circuit
151 ... High-speed transmitter
152 ... Low speed transmitter
165 ... Sub clock selection circuit
181 ... System bus
191: External interrupt signal
193: Return interrupt signal
194: Delayed interrupt signal
1311 ... Peripheral device main control circuit
1312 ... Power saving mode control circuit
1313: Main clock mask circuit
1431: External interrupt mask circuit
1432, 1433,... Internal interrupt mask circuit
1621 ... High-speed clock control circuit
1622 ... Main clock control circuit
1631: Main clock stop control register
1632 ... Main clock stop timer setting register
1633: Main clock stop timer circuit
1641 ... Main clock recovery timer setting register
1642... Main clock recovery timer circuit
1711: High-speed clock signal
1712: Low-speed clock signal
1721 ... Main clock signal
1722 ... Sub clock signal
1821, 1822,... Control line
1921, 1922, ... Internal interrupt signal
13141 ... Power saving mode transition control register
13142 ... Power saving mode transition timer setting register
13143 ... Power saving mode return timer setting register
13144 ... Power saving mode forced return register
13145 ... Power saving mode transition timer circuit
13146 ... Power saving mode return timer circuit
13151 ... Interrupt mask register
13152 ... Interrupt mask circuit
S101, S102, ... Processing procedure (step)

Claims (4)

When the CPU and one or more peripheral devices are connected to the CPU via a predetermined bus and the peripheral device is in a predetermined power saving mode, based on the input of a predetermined return interrupt signal In an information processing apparatus comprising peripheral device control means for controlling the peripheral device to return from the power saving mode,
Said peripheral device control means, after the input of the return interrupt signal, after the lapse of a predetermined power saving mode return time is in the pre-Symbol peripheral ones to return from the power saving mode,
A return interrupt mask register provided so that a return interrupt mask instruction that does not execute return from the power saving mode according to the return interrupt signal by the peripheral device control means can be set via the bus;
For each peripheral device, a power saving mode forced return register provided so that a forced return command for forcibly returning the peripheral device from the power saving mode by the peripheral device control means can be set via the bus. An information processing apparatus comprising the information processing apparatus. The information processing apparatus according to claim 1 , further comprising: a power saving mode return timer setting register provided so that the power saving mode return time for each of the peripheral devices can be set via the bus. Internal interrupt signal generating means for generating a predetermined internal interrupt signal under predetermined conditions for each of the peripheral devices;
3. A return interrupt signal generating means for generating the return interrupt signal when either the internal interrupt signal or an external interrupt signal input from the outside is input. The information processing apparatus described. An internal / external interrupt mask register provided so that an internal / external interrupt mask instruction can be set via the bus for causing the return interrupt signal generation means to ignore each of the internal interrupt signal and the external interrupt signal. The information processing apparatus according to claim 3 , comprising:

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