JP2012173847A - Bus arbitration device and bus arbitration method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus arbitration device for achieving access control while maintaining data transfer efficiency even when the same access request is redundantly generated from a plurality of masters to slaves.SOLUTION: A bus arbitration device 10 configured to arbitrate access from masters 2a-2c to slaves 3a-3b connected to a bus 1 includes: an under-transfer request storage part 12 for storing the information of a first request command and a first destination address under transmission from the masters as first request information; a pre-transfer request storage part 13 for storing the first request information which has been transmitted from the masters to the slaves as second request information; and a determination part 11 for receiving the first and second request information from the under-transfer request storage part 12 and the pre-transfer request storage part 13, and for selecting the masters 2a-2c by using those information, and for determining the masters as those which are able to perform access to the slaves 3a and 3b as access request destinations.

Description

The present invention relates to memory access control by a split transaction method.

As a device that efficiently accesses the memory by the split transaction method, conventionally, a transmission processing interface that transmits a write command to the memory, write data, and a read command from the memory to the transmission path, and reading from the memory Receiving processing interface for receiving the read data read from the receiving path, a receiving unit for receiving the write command, the write data and the read command, a buffer for temporarily storing the received write command, a write command and a write command The next write command received during transmission processing of one or more of the stored data is stored in the buffer, and the subsequent read command is received while the write command is stored in the buffer And a control unit that performs control to pass the read command to the transmission processing interface before the write command that is being stored, thereby reducing the idle period of the transmission path on the transmission side and the reception side There is a semiconductor integrated circuit that (for example, see Patent Document 1).

JP 2008-250985 A

However, in the semiconductor integrated circuit described in Patent Document 1, when the same access request (that is, a write command or a read command) is repeatedly generated from a plurality of masters to a slave memory, Since the request from other masters can be delayed with priority given to the request, the data transfer efficiency may be deteriorated.

The present invention has been made to solve such a problem, and even when the same access request is repeatedly generated from a plurality of masters to a slave, access control can be performed while maintaining data transfer efficiency. An object is to obtain a bus arbitration device.

In the bus arbitration device according to the present invention, when an access request is made at the same timing from the first master and the second master connected to the bus to the slave connected to the bus, the first master and the second master A bus arbitration device connected to the bus for arbitrating an access request from a master to a slave, wherein the first master requests an access request to the slave by the first master, and an execution slave of the first request command The first destination address information indicating the first request address is received from the first master at the first timing, and the second request command from which the second master requests access to the slave and the execution destination of the second request command Information on the second destination address indicating the slave is received from the second master at the first timing, and the received first request command is received. A first request holding unit that holds the first destination address information, the second request command, and the second destination address information as the first request information, and the first master or the second master. A request command that is requested to be accessed by the slave and executed at a second timing before the first timing and a destination address indicating the execution destination slave of the request command are held as second request information. The first request information is received from the request holding unit and the first request holding unit, the second request information is received from the second request holding unit, and using the first and second request information, Execute either the access request from the first master or the access request from the second master at the first timing A determining unit to Luke, those having a.

According to the present invention, the bus arbitration apparatus has the above-described configuration, so that access control can be performed while maintaining the data transfer efficiency even when the same access request is repeatedly generated from a plurality of masters.

1 is a configuration diagram of a bus system including a bus arbitration device according to Embodiment 1. FIG. It is a figure which shows the structure details of the bus arbitration apparatus in FIG. FIG. 3 is a conceptual image diagram of data held by an in-transfer request holding unit and a previous transfer request holding unit in FIG. 2. It is a flowchart which shows the determination process which the determination part in FIG. 1 performs. It is an image figure of the request state table which the determination part of FIG. 1 uses. It is a flowchart which shows another determination process which the determination part in FIG. 1 performs. It is another structure image figure of the data which the front transfer request holding part in FIG. 1 hold | maintains.

Embodiment 1 FIG.
A bus arbitration apparatus according to Embodiment 1 for carrying out the present invention will be described with reference to FIGS. FIG. 1 shows a configuration of a bus system 100 including a bus arbitration unit 10. The bus system 100 includes masters 2a to 2c such as CPU and DMA, a bus 1, and slaves 3a and 3b connected to the masters 2a to 2c via the bus 1. A bus arbitration unit 10 that arbitrates access requests from the masters 2a to 2c to the slaves 3a and 3b, a request command that is an access request of the masters 2a to 2c, and a request address selection that selects the address of the request request destination slave 4, selected by the write data selection unit 5 that selects data to be written from the masters 2 a to 2 c to the slaves 3 a and 3 b, the read data selection unit 6 that selects data to be read from the slaves 3 a and 3 b, and the request / address selection unit 4. Address control units 7a and 7b for controlling the addresses are provided.

Here, the bus 1, the masters 2a to 2c, and the slaves 3a and 3b operate in synchronization with the same clock (not shown), and bus arbitration is performed every clock. Although the slaves 7a and 7b are described as two-port memories here, they may be one-port memories, and the number of masters 2a to 2c, address control units 7a and 7b, and slaves 3a and 3b is also the same as that of the present embodiment. It is not limited to the number. The request / address selection unit 4 may be provided with a request selection unit and an address selection unit separately.

During the transmission of data from a certain master (for example, master 2a) to a certain slave (for example, slave 3a), the bus arbitration unit 10 is identical to the slaves 3a and 3b from the plurality of masters 2a to 2c. When request commands (write request or read request) are transmitted in duplicate, the burst data corresponding to which request command is transferred after the data transfer of the currently transferred burst data, that is, the destination slave 3a is reached. It mediates what to do.

As shown in FIG. 2, the bus arbitration unit 10 determines a command to be transferred and a destination slave 3a (or 3b) based on a predetermined condition (described later), and requests / address selection signal 20 and write data selection signal 21. The determination unit 11 that generates the read data selection signal 22 receives the request command signals 101a to 101c and the address signals 102a to 102c from the masters 2a to 2c, temporarily stores these information, and then transfers them as the transferred data signal 34. In-transfer request holding unit 12 to be transmitted, pre-transfer request holding unit 13 that receives the transferred data signal 34 from the in-transfer request holding unit 12 and temporarily holds it, and external arbitration mode setting signal 37 input from the outside And an arbitration mode setting unit 14 for setting the bus arbitration mode.
When the request / address selection unit 4 is divided into a request selection unit and an address selection unit, two request selection signals and address selection signals are required instead of the request / address selection signal 20.

FIG. 3 shows an image of the configuration of data held by the in-transfer request holding unit 12 and the previous transfer request holding unit 13.
The in-transfer request holding unit 12 and the previous transfer request holding unit 13 have a command area 40 for storing information of the request command signals 101a to 101c and a request request source master 3a to the request request slaves 2a and 2b, respectively. And a master number area 41 for storing 3c numbers. Specifically, the information of the request command signals 101a to 101c includes three types of information: a write request for requesting data writing to the slave, a read request for requesting data reading from the slave, and an idle request for neither data writing nor reading. Any one of them.

Here, the operation of the bus system 100 will be described.
When request command signals 101a to 101c, address signals 102a to 102c, and write data signals 103a to 103c are input to the bus 1 from the masters 2a to 2c, the request command signals 101a to 101c and the address signals 102a to 102c are respectively two. One is sent to the bus arbitration unit 10 and the other is sent to the request command / address selection unit 4. The write data signals 103 a to 103 c are transmitted to the write data selection unit 5.

The request command / address selection unit 4 responds to the request command / address selection signal 20 received from the determination unit 11 in the bus arbitration unit 10 and requests command signals 101a to 101c and address signals 102a input from the masters 2a to 2c. A request command signal and an address signal corresponding to the request command signal are selected from -102c, and a selection request command / address signal 200 is transmitted to the address control units 7a and 7b.

Similarly, the write data selection unit 5 selects one write data signal from the write data signals 103a to 103c input from the masters 2a to 2c in accordance with the write data selection signal 21 received from the determination unit 11. The selected burst data 201 is transmitted to the slave 3a (or 3b) that is the destination of the request command corresponding to this write data.

When the address control unit 7a receives the selection request command / address signal 200 from the request command / address selection unit 4, the address control unit 7a determines whether the selected request command requests write data or read data. To do.
In the case of a request command for requesting write data, the address controller 7a determines whether or not the selected address signal is addressed to the corresponding slave 3a, and if it is addressed to the slave 3a, the write enable signal 202a for burst data is determined. A burst address signal 204a is generated and transmitted to the slave 3a. At this time, the address control unit so that the timing at which the burst data 201 selected by the write data selection unit 5 reaches the slave 3a and the timing at which the generated write enable signal 202a and burst address signal 204a arrive at the slave 3a coincide with each other. Adjust with 7a.

On the other hand, when the request command selected by the request command / address selection unit 4 is a request command for requesting read data, the address control unit 7a determines whether the selected address signal is addressed to the corresponding slave 3a. If it is addressed to the slave 3a, a burst data read enable signal 203a and a burst address signal 204a are generated and transmitted to the slave 7a.
When the transmission of the write enable signal 202a, the read enable signal 203a, and the burst address signal 204a for successive burst data of the same request and the same destination is completed, the transfer end signal 23a is transmitted to the determination unit 11 in the bus arbitration unit 10. To do.

Similarly, when the address control unit 7b receives the selection request command / address signal 200 from the request command / address selection unit 4, the address control unit 7b requests the write data or the read data. Determine whether.
In the case of a request command for requesting write data, it is determined whether or not the selected address signal is addressed to the slave 3b corresponding to itself, and if it is addressed to the slave 3b, the write enable signal 202b for burst data and the burst address are determined. A signal 204b is generated and transmitted to the slave 3b.

In the case of a request command for requesting read data, it is determined whether or not the selected address signal is addressed to the slave 3b corresponding to itself, and if it is addressed to the slave 3b, the read enable signal 203b for burst data and the burst address are determined. A signal 204b is generated and transmitted to the slave 3b.
When the transmission of the write enable signal 202b, the read enable signal 203b, and the burst address signal 204b for successive burst data of the same request and the same destination is completed, the transfer end signal 23b is transmitted to the determination unit 11 in the bus arbitration unit 10. To do.
In this case, since a two-port memory is assumed as a slave, a write enable signal and a read enable signal are generated. However, in the case of a one-port memory, one kind of enable signal is used for both writing and reading. become.

When the slave 3a receives the write enable signal 202a and the burst address signal 204a from the address control unit 7a and the burst data 201 from the write data selection unit 5, the slave 3a writes the received burst data 201. When the read enable signal 203a and the burst address signal 204a are received from the address control unit 7a, the read data is output to the read data selection unit 6 with the requesting masters 2a to 2c as destinations.
Similarly, when the slave 3b receives the write enable signal 202b and the burst address signal 204b from the address controller 7b, and receives the burst data 201 from the write data selector 5, the burst data 201 is written, and the read enable signal 203b and the burst address signal 204b are received. When received, the read data is output to the read data selection unit 6 with the requesting masters 2a to 2c as destinations.

The read data selection unit 6 selects the read data signals 205a and 205b input from the slaves 3a and 3b according to the read data selection signal 22 received from the determination unit 11, and the masters 2a to 2c that are read request sources. The read data signal 205 is transmitted to either of them.
The masters 2a to 2c receive the read data signal 205 and read the data of desired slaves 3a and 3b.

Hereinafter, the internal operation of the bus arbitration unit 10 will be described in detail with reference to FIG.
The request command signals 101a to 101c and the address signals 102a to 102c input from the masters 2a to 2c to the bus arbitration unit 10 are branched into two, respectively, and input to the determination unit 11 and the transfer request holding unit 12.

In addition to the request command signals 101a to 101c and the address signals 102a to 102c from the masters 2a to 2c, the determination unit 11 receives the transfer request command / address signal 33 being received from the transfer request holding unit 12 and the previous transfer request holding unit 13 From the received request command / address signal 36 and the internal arbitration mode setting signal 38 from the arbitration mode setting unit 14. These signals are used to determine the request command, address, and data to be selected for the next clock, and a request / address selection signal 20, a write data selection signal 21, and a read data selection signal 22 are generated. The generated signal is transmitted to each predetermined block in the next clock period. That is, the request / address selection signal 20 is transmitted to the request / address selection unit 4, the write data selection signal 21 is transmitted to the write data selection unit 5, and the read data selection signal 22 is transmitted to the read data selection unit 6.

The determination unit 11 also includes a request command / address signal 30 during transfer indicating request command information and address information during transfer, and a master number signal 31 during data transfer indicating which master is transferring burst data. Transmission is performed toward the request holding unit 12 during transfer in the same clock period as the burst data transfer period.
Further, when the determination unit 11 receives the transfer end signals 23a and 23b from the address control units 7a and 7b, the determination unit 11 determines that the burst data being transferred is the end of the burst, and sends a transfer end notification signal 32 to the transfer request holding unit 12. The clear signal 35 is transmitted to the previous transfer request holding unit 13 during the clock period for transferring the data at the end of the burst.
One clock indicates a determination period in which the determination unit 11 performs one determination.

The in-transfer request holding unit 12 stores request command information and destination slave address information for each of the masters 2a to 2c based on the request command signals 101a to 101c and the address signals 102a to 102c from the masters 2a to 2c. And temporarily hold.
In addition to the signals from the masters 2a to 2c, the in-transfer request holding unit 12 receives the in-transfer request command / address signal 30, the in-data transfer master number signal 31, and the transfer end notification signal 32 from the determination unit 11. To do.

When the transfer request holding unit 12 receives signals from the masters 2a to 2c and does not receive a signal from the determination unit 11, the transfer request holding unit 12 receives the request command signals 101a to 101c and addresses received from the masters 2a to 2c. The signals 102a to 102c are transmitted as they are to the determination unit 11 as the reception transfer command / address signal 33 in the same clock period.

When the transfer request holding unit 12 receives signals from the masters 2a to 2c and receives the transfer end notification signal 32 from the determination unit 11, the transfer request holding unit 12 receives the received request command signals 101a to 101c and the address signal 102a. To 102c are transmitted as they are to the transfer command / address signal 33 during reception to the determination unit 11 as they are during the same clock period, and the master number information obtained from the master number signal 31 during data transfer and the request command / address signal 30 during transfer A transferred data signal 34 is generated based on the obtained request command information and the address information of the destination slave stored in the own apparatus, and is transmitted to the previous transfer request holding unit 13 in the next clock period.
The destination slave address information used to generate the transferred data signal 34 is the transfer request command / address signal 30 received from the determination unit 11 instead of using the information stored in the transfer request holding unit 12. The information may be used.

Further, the transfer request holding unit 12 receives signals from the masters 2a to 2c, and receives the transfer request command / address signal 30 and the data transfer master number signal 31 without receiving the transfer end notification signal 32 from the determination unit 11. In the case of reception, the transfer request holding unit 12 transmits the received transfer request command / address signal 30 signal and the data transfer master number signal 31 to the determination unit 11 in the next clock period. That is, the signal input from the determination unit 11 is returned to the determination unit 11 with one clock delay.

When the pre-transfer request holding unit 13 receives the transferred data signal 34 from the in-transfer request holding unit 12, it stores the master number, the request command, and the address information of the destination slave in association with each other and stores them in its own device. This is held until the clear signal 35 is received from the unit 11.
Further, the previous transfer request holding unit 13 transmits information stored in the own device to the determination unit 11 as a transferred request command / address signal 36. This transmission process is repeated every clock until the previous transfer request holding unit 13 receives the transferred data signal 34 until the clear signal 35 is received.

When the pre-transfer request holding unit 13 receives the clear signal 35 from the determining unit 11, the pre-transfer request holding unit 13 clears the information of the transferred data signal 34 that is held. Even when the clear signal 35 is not received, when the new transferred data signal 34 is received from the request-in-transfer holding unit 12, the stored information is overwritten and updated.

For example, the arbitration mode setting unit 14 performs mode setting when the determination unit 11 includes two of a master averaging mode and a command averaging mode. Master averaging mode is a mode that selects the master so that the master selected as the request request source is average. In the command averaging mode, the request command is averaged for each of the write request and the read request. In this mode, the master is selected. The mode is switched by an external arbitration mode setting signal 37 input from the outside.

Here, the determination process performed by the determination unit 11 during one clock period will be described with reference to the flowchart of FIG. 4 and the request status table of FIG. Here, the request status table is a status table indicating a request history generated in the determination unit 11 by the determination unit 11 using the transfer request command / address signal 33 being received and the transferred request command / address signal 36. Note that the arbitration mode is set to the master averaging mode.
In FIG. 4, the slave number is i (i = 1 to n, n is an integer). The determination unit 11 initializes the slave number to “i = 0” in S1, and requests whether this slave is in a request command full state, that is, a state in which both a write request and a read request are received, as shown in FIG. Judgment is made with reference to the state table (S2). In the example of FIG. 5, slave # 0 has received a write request from master # 0 and read requests from master # 1 and master # 2, and is in a request command full state.

If it is determined in S2 that the request command is in the full state, the determination unit 11 refers to the request state table and sets the number of write requests and the number of read requests for each master # 0 to # 2 as the total number of request commands. Aggregate (S3).
In the case of FIG. 5, master # 0 has a total number of write requests “2”, a total number of read requests “1”, master # 1 has a total number of write requests “1”, a total number of read requests “2”, a master # 2 is the total number of write requests “1” and the total number of read requests “1”.

Next, for each write request and read request, the total number of masters with request history (request information by transfer request command / address signal 33 being received and request information by transferred request command / address signal 36) is counted for each master. (S4).
In the case of FIG. 5, the write request is the total number of master # 0 “2”, the total number of master # 1 is “1”, the total number of master # 2 is “1”, and the read request is the master # 0. The total number is “1”, the total number of master # 1 is “2”, and the total number of master # 2 is “1”.

When the calculation of the total number of each master is completed, the total number of request commands (total number of write requests “4”, total for all write requests and read requests of all masters # 0 to # 2 counted in S3. The total number of read requests “4”) is calculated (S5), and the total number of total masters (total number of masters “8”) of all masters counted in S4 is calculated (S6).

When S6 ends, it is determined whether the total number of write requests calculated in S5 is equal to the total number of masters calculated in S6 (S7). In the above example, the total number of write requests is “4” and the total number of total masters is “8”, so the process proceeds to S8, and the total number of read request commands calculated in S5 and the total calculated in S6. It is determined whether the total number of masters is equal (S8). Also here, since the total number of total read requests is “4” and the total number of total masters is “8”, the process proceeds to S9.

In S9, it is determined whether or not the total number of total masters calculated in S6 is smaller than the total number of write requests calculated in S6 and the total read request. (S9).
In the above example, the total number of masters “8” is larger than the total number of write requests “4”. Therefore, “No” is determined in S9 and the process proceeds to S10. In addition, since the total number of masters “8” is larger than the total number of read requests “4”, similarly, “No” is determined in S9 and the process proceeds to S10.

When it is determined in S7 that the total number of write request total requests (total number of write commands) is equal to the total number of total masters, or in S8 the total number of read request total request commands (total total read request totals). Number) and the total number of total masters are the same, the process proceeds to S10 as in the case where “No” is determined in S9.
In S10, for each of the write request and the read request, a master with the smallest total number of masters calculated in S4 is preferentially selected as a master to be selected next (S10). That is, in the example of FIG. 5, since the write request from the in-transfer request holding unit 12 is only master # 0, master # 0 is selected, but the read request is from master # 1 and master # 2, and master # 1 in S4 Since the total number of masters “2” and the total number of masters # 2 are “1”, master # 2 having a smaller master number is selected.

If the total number of write requests is smaller than the total number of masters in S9, the master with the smallest number of write requests is preferentially selected as the next master to be written (S11). Similarly, if the total number of read requests is smaller than the total number of masters in S9, the master with the smallest number of read requests is preferentially selected as the next master to be read (S11).
If there are a plurality of masters having the smallest number of masters, one master is selected by round robin or weighting.

After S10 and S11, a request / address selection signal 20, a write data selection signal 21, and a read data selection signal 22 corresponding to the selected masters 2a to 2c are generated based on the result selected by the determination unit 11, respectively. To each corresponding functional block. This process corresponds to an act of determining which access request is to be executed from the access requests from the masters 2a to 2c.
If it is determined that at least one of the write request and the read request is not received from the request command holding unit 12 during transfer after S10 and S11 or in S2 (when it is determined “No”), the slave number i is n It is determined whether it is (final slave number) (S12). If it is determined “No” in S2 and a request command that is not being received (not used for transfer) is received, the operation is performed according to the request command.

If the determination is completed for all n slaves in S12 (if i = n), the flow ends. If the determination is not completed for all slaves, i is incremented by 1 in S13 and the process proceeds to S2. Return.
In FIG. 4, the initial value of the slave number is “i = 0”, but the initial value may be changed to the round robin method at any time.

Also, although the case where the master averaging mode is selected has been described here, when the command averaging mode is selected, as shown in FIG. 6, the master averaging mode of FIG. Is different. Specifically, S1 to S9 perform the same processing as the master averaging mode, and if “Yes” in S8, the above-mentioned S11, that is, the master having the smallest number of request commands is selected, and “No” is selected in S8. If so, the process proceeds to S9. If “No” in S9, the process proceeds to S11. If “Yes” in S11, the master having the smallest number of masters is selected in S10.

By the way, the total number of write request commands (or the total number of read request commands) is always less than the total number of masters except when all request commands are write requests (or read requests). The total number of commands (or the total number of read request commands) may be weighted for comparison.

In addition, as shown in FIG. 7, in the previous transfer request holding unit 13, an access count area 42 is provided in addition to the command area 40 and the master number area 41 to determine which slave is accessed by which request command and how many times. The history information may be included in the transferred request command / address signal 36 and sent to the determination unit.
It is assumed that the access count is reset when the power is turned on or every predetermined time. For example, when the predetermined time is 1000 clocks (1000 determination periods), the access count history during this period is transmitted to the determination unit 11 so that the number of request commands and the number of masters can be determined during bus arbitration. As the number, an average value for a longer period than two clocks can be used.

Here, the case of a two-port memory having the write enable signals 202a to 202c and the read enable signals 203a to 202c has been described. However, in the case of a one-port memory using a common enable signal for the write request and the read request, a request during transfer With reference to the receiving transfer command / address signal 33 sent from the holding unit 12 to the determination unit 11, the request command to be selected next may be set to be different from the currently selected request command.

According to the present embodiment, by summing up the total number of requests from the master to the slave and the number of masters that made the request, by comparing these total numbers, bus arbitration is performed so that the request commands are averaged. Even when multiple access requests are generated from a plurality of masters, access control can be performed while maintaining data transfer efficiency.

Also, by summing up the total number of requests from the master to the slaves and the number of masters that made the requests, and comparing these totals, bus arbitration is performed so that the number of requests received from each master is averaged. Even when multiple access requests are generated from a plurality of masters, access control can be performed while maintaining data transfer efficiency.

In addition, the number of accesses to the slaves 3a to 3c for the masters 2a to 2c is counted, and the bus arbitration is performed using the number of accesses, thereby averaging the number of accesses between a plurality of masters and data as the entire bus system. Transfer efficiency can be improved.

The embodiment of the present invention has been described above. In the above embodiment, “request command signals 101a to 101c”, “first destination address information” and “second destination command” as “first request command” and “second request command” recited in the claims "Address signals 102a to 102c" as "destination address information", "transfer request holding unit 12" as "first request holding unit", "transferred data signal 34", "second request information" The “previous transfer request holding unit 13” has been described as the “2 request holding unit”, but these are not limited to the above-described embodiment, and any modifications are possible as long as they are included in the spirit of the present invention. It may be done.

1 Buses 2a to 2c Masters 3a to 3c Slave 4 Command / address selection unit 5 Write data selection unit 6 Read data selection units 7a and 7b Address control unit 10 Bus arbitration unit 11 Judgment unit 12 Transfer request holding unit 13 Pretransfer request holding Unit 14 Arbitration mode setting unit 20 Request / address selection signal 21 Write data selection signal 22 Read data selection signal 23a, 23b Transfer end signal 30 Transfer request command / address signal 31 Data transfer master number signal 32 Transfer end notification signal 33 Medium transfer request command / address signal 34 Transferred data signal 35 Clear signal 36 Transferred request command / address signal 37 External arbitration mode setting signal 38 Internal arbitration mode setting signal 40 Command area 41 Master number area 42 Number of accesses region
100 bus system
101a to 101c Request command signal
102a to 102c Address signal
103a to 103c Write data signal
200 Select request command / address signal
201 burst data
202a to 202c Write enable signal
203a to 203c Read enable signal
204a to 204c Burst address signal
205, 205a, 205b Read data signal

Claims (8)

Access from the first master and the second master to the slave when an access request is made at the same timing from the first master and the second master connected to the bus to the slave connected to the bus In a bus arbitration device connected to the bus for arbitrating requests,
A first request command from which the first master makes an access request to the slave and information on a first destination address indicating an execution destination slave of the first request command are sent from the first master to a first timing. The second master receives the second request command for the second master requesting access to the slave and the second destination address indicating the slave to which the second request command is executed. The first request information is received at the first timing, and the received first request command, the first destination address information, the second request command, and the second destination address information are received as the first request information. A first request holding unit that holds as
A request command that is requested to be accessed from the first master or the second master to the slave and is executed at a second timing before the first timing, and a destination address that indicates an execution slave of the request command A second request holding unit that holds the information as second request information;
Receiving the first request information from the first request holding unit, receiving the second request information from the second request holding unit, and using the first and second request information, A determination unit that determines whether to execute an access request from the first master or an access request from the second master at a first timing;
A bus arbitration device comprising: The determination unit
The number of request commands at the first timing and the second timing requested from the first master, and the request commands at the first timing and the second timing requested from the second master The total number of request commands is calculated by totaling the total number of request commands of the first and second masters.
The number of first masters that transmitted the request command at the first timing and the second timing, and the number of second masters that transmitted the request command at the first timing and the second timing. Respectively, and calculate the total number of masters by summing up the total number of the first and second masters,
The access request from the first master or the access request from the second master is determined using the calculated total number of request commands and the total number of masters. The bus arbitration device according to 1. The determination unit
When the total request command and the total master number are compared, and the total master number is less than or equal to the total request command number, the access request from the first master and the access request from the second master 3. The bus arbitration apparatus according to claim 2, wherein the bus arbitration device is determined as an access request for executing an access request from a master having a small number of first masters or second masters. The determination unit
When the total request command and the total master number are compared, and the total master number is less than or equal to the total request command number, the access request from the first master and the access request from the second master The access request is determined to be an access request for executing an access request from a master with a small number of request commands requested from the aggregated first master or a request command requested from the second master. Item 3. The bus arbitration device according to Item 2. The determination unit
Based on the result of determining whether to execute the access request from the first master or the access request from the second master, the access request from the first master or the access from the second master 5. The bus arbitration apparatus according to claim 1, wherein a selection signal for selecting any one of the requests is output. The first request holding unit outputs a request command executed at the second timing and a destination address indicating an execution destination slave of the request command to the second request holding unit, and holds the second request holding unit. The bus arbitration apparatus according to claim 1, wherein the unit holds the request command and the destination address as the second request information. The second request holding unit is configured to request access from the first master and the number of times of the first access request executed before the second timing, and to request the second master to access the second timing. Count the number of second access requests that have been executed previously, and hold information on the number of access requests counted,
The determination unit
The first request information output from the first request holding unit, the second request information output from the second request holding unit, and the access output from the second request holding unit 2. The bus arbitration apparatus according to claim 1, wherein it is determined whether to execute an access request from the first master or an access request from the second master using information on the number of requests. . Access from the first master and the second master to the slave when an access request is made at the same timing from the first master and the second master connected to the bus to the slave connected to the bus In a bus arbitration method connected to the bus for arbitrating requests,
A first request command from which the first master makes an access request to the slave and information on a first destination address indicating an execution destination slave of the first request command are sent from the first master to a first timing. And the second master requesting the second master to access the slave and information on the second destination address indicating the slave to which the second request command is executed are obtained from the second master. A first information acquisition step acquired at the first timing from:
A request command that is requested to be accessed from the first master or the second master to the slave and is executed at a second timing before the first timing, and a destination address that indicates an execution slave of the request command A second information acquisition step of acquiring the information of
The first request command, the first destination address information, the second request command, acquired at the first timing, acquired by the first information acquisition step and the second information acquisition step, And the second destination address information, and the request command executed at the second timing and the destination address information indicating the execution destination slave of the request command. And a determination step of determining whether to execute an access request from one master or an access request from the second master.

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