CN104657330A - High-performance heterogeneous computing platform based on x86 architecture processor and FPGA (Field Programmable Gate Array) - Google Patents
High-performance heterogeneous computing platform based on x86 architecture processor and FPGA (Field Programmable Gate Array) Download PDFInfo
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Abstract
The invention discloses a high-performance heterogeneous computing platform based on an x86 architecture processor and an FPGA (Field Programmable Gate Array). The high-performance heterogeneous computing platform belongs to the technical field of computer construction, and comprises a universal processor module with the x86 architecture processor, a PCIe SWITCH module and an FPGA computing module on the basis of a current platform, wherein the universal processor module is responsible for high-performance task distributing and dispatching, flow control and computing result collecting summarizing; an FPGA chip is built in the PCIe SWITCH module; the PCIe SWITCH module is responsible for interconnection and a data transmission task between the universal processor module and the FPGA computing module; the FPGA computing module is used for converting data to be operated into a computing result through internal logic, and processing and storing. According to the high-performance heterogeneous computing platform based on the x86 architecture processor and the FPGA, the expandability of a computing system is strong; appropriate FPGA computing module quantity is designed according to the application of different scales, so that higher computing parallelism is achieved, and the aim of improving the whole computing performance is achieved.
Description
Technical field
The present invention discloses a kind of high-performance heterogeneous computing platforms, belongs to computing machine and deposits constructing technology field, specifically a kind of high-performance heterogeneous computing platforms based on x86 architecture processor and FPGA.
Background technology
High-performance calculation HPC (High Performance Computing) refers to and utilizes the high-performance computer with superpower computing power to resolve current super large, superelevation, hypercomplex calculation task.The mainstream scheme realizing at present high-performance calculation is both at home and abroad computer cluster machine system, and core calculations unit generally adopts based on general processor and CPU architecture or based on the Heterogeneous Computing framework of CPU in conjunction with GPU.Although adopt GPU to form heterogeneous computing platforms, improve the high performance computing system performance for some calculation task, the cost performance of its computing system and power consumption are still too high, and also there is a big difference for computing velocity and ASIC chip computing velocity.The high-performance heterogeneous computing platforms that the present invention is based on x86 architecture processor and FPGA comprises universal processor module, PCIe SWITCH module and some FPGA computing modules containing x86 architecture processor, PCIe bus interface is utilized to carry out data transmission, technology maturation, transmission speed is fast, can meet the application of current high-speed computation; After overall calculation platform of the present invention is set up, only need develop the computational logic for different computing tasks, and be downloaded in fpga chip, the special-purpose computing system for particular problem can be formed, there is the system expandability strong, according to the application of different scales, suitable FPGA computing module quantity can be designed, reach higher calculating degree of parallelism, promote the advantages such as overall computational performance.
FPGA, Field Programmable Gate Array, field programmable gate array.Can not only as ASIC(Application Specific Integrated Circuit, special IC) equally realize the logic function of various complex custom, and can integrated Digital Signal processing DSP (Digital Signal Processing) unit and various high speed communication interface module, in complex calculation application, play powerful computing power, accelerate extensive high-performance calculation.Meanwhile, FPGA has flexible configuration and the lower good characteristic of power consumption, can reconfigure and realize new logic function, be easy to maintenance and the upgrading of equipment, significantly reduces application cost and power consumption.The calculated performance of continuous lifting and the dirigibility of reconstruct make FPGA can tackle traditional high-performance calculation machine architecture be difficult to tackle system high efficiency can challenge, obtain better cost performance in high-performance calculation application.
Summary of the invention
The cost performance and the power consumption that the present invention is directed to existing computing system are still too high, and computing velocity can not reach the problem of ASIC chip computing velocity, a kind of high-performance heterogeneous computing platforms based on x86 architecture processor and FPGA is provided, achieve computing system extensibility strong, can according to the application of different scales, design suitable FPGA computing module quantity, reach higher calculating degree of parallelism, promote the object of overall computational performance.
The concrete scheme that the present invention proposes is:
Based on a high-performance heterogeneous computing platforms of x86 architecture processor and FPGA, on the basis of existing platform, there is the universal processor module of x86 architecture processor, PCIe SWITCH module and FPGA computing module;
Wherein universal processor module is responsible for the input of high performance tasks, output, calculation task scheduling, computational resource allocation, calculation task Row control and result of calculation and is collected and gather;
The built-in fpga chip of PCIe SWITCH module, is responsible for the interconnection between universal processor module and FPGA computing module and data transfer task;
FPGA computing module is used for needing the data of computing to be translated into result of calculation by internal logic, go forward side by side row relax and storage, the bus interface providing inquiry and control.Universal processor module can mutual with multiple FPGA computing module.
Described FPGA computing module comprises internal logic and realizes unit and external memory unit;
Internal logic realizes logical operation and the control that unit is responsible for the reception task of inner FPGA computing module;
External memory unit is responsible for the buffer memory of data, provides reading and writing data function.
Described internal logic realizes unit and comprises master management unit, computing unit, PCIe interface control module, memory control unit;
The entirety that master management unit is responsible for system FPGA computing module controls, and comprises the reception of task to be calculated, the reception of data to be calculated and buffer memory, the process control of calculating and returning of result of calculation;
Concrete evaluation work is carried out in the order that computing unit is responsible for sending according to master management unit, and the computing interval external memory unit that may have access in module reads data to be calculated.After calculating completes, result is returned to master management unit;
PCIe interface control module is responsible for the information such as calculation task, data to be calculated of distributing from universal processor module, is in charge of the equipment hot swap of FPGA computing module, traffic monitoring, data integrity detection, Service Quality Management simultaneously;
Memory control unit is responsible for the request of data received from master management unit or computing unit, access external memory unit, and completes desired data read-write capability.
Described external memory unit comprises DIMM internal storage location, is responsible for the temporary of data, provides reading and writing data function.
Described computing platform calculation task treatment scheme is:
The functional character of high-performance calculation task according to each FPGA computing module distributes by universal processor module, transmits the raw data needed for calculating simultaneously;
Each FPGA computing module receives the calculation task distributed, and by the primary data cache needed for calculating;
FPGA computing module calculates, and by PCIe bus interface, result is back to universal processor module after calculating;
Each result of calculation gathers by universal processor module, forms the net result of calculation task.
Based on a method for the high-performance heterogeneous computing platforms process calculation task of x86 architecture processor and FPGA, realize according to described a kind of high-performance heterogeneous computing platforms based on x86 architecture processor and FPGA, treatment scheme is:
The functional character of high-performance calculation task according to each FPGA computing module distributes by universal processor module, transmits the raw data needed for calculating simultaneously;
Each FPGA computing module receives the calculation task distributed, and by the primary data cache needed for calculating;
FPGA computing module calculates, and by PCIe bus interface, result is back to universal processor module after calculating;
Each result of calculation gathers by universal processor module, forms the net result of calculation task.
Usefulness of the present invention is: the present invention adopts PCIe bus interface to carry out data transmission, and transmission speed is fast, meets the application of current high-speed computation; Programmability is strong, after overall calculation platform is set up, only need develop the computational logic of the FPGA computing module for different computing tasks, in fpga chip, can form the special-purpose computing system for particular problem; The system expandability is strong, according to the application of different scales, suitable FPGA computing module quantity can be designed, reaches higher calculating degree of parallelism, promote overall computational performance: superior performance, hardware platform is the system control cpu that x86 architecture processor and FPGA constitute that has a high throughput.
Accompanying drawing explanation
Fig. 1 is configuration diagram of the present invention;
Fig. 2 is that FPGA computing module functional unit of the present invention forms schematic diagram;
Fig. 3 is the calculation task treatment scheme schematic diagram of computing platform of the present invention.
Embodiment
As shown in Figure 1, the general frame based on the high-performance heterogeneous computing platforms of x86 architecture processor and FPGA is as follows:
X86 series processors in universal processor module is responsible for entire system and is controlled.Be connected with PCIe SWITCH module by PCIe bus interface.Universal processor module is the core control equipment of computing platform structure.
The connection of PCIe SWITCH module in charge universal processor module and FPGA computing module.PCIe affairs can be routed to another port from any one port by PCIe SWITCH module.It has multiple port, and each port connects a PCIe link, thus realizes the mutual of universal processor module and multiple FPGA computing module.
FPGA computing module is responsible for concrete calculation task, is connected with PCIe SWITCH module by PCIe bus interface.FPGA computing module is the role calculating implementor, is a concrete PCIe equipment in system.The PCIe endpoint type of FPGA computing module can be Legacy, PCIe end points, supports IO affairs; Also support traditional interruption generation method, comprise MIS interrupt mode.It can send PCIe transactions requests and can complete the equipment of PCIe transmission.
As shown in Figure 2, the FPGA computing module functional unit based on the high-performance heterogeneous computing platforms of x86 architecture processor and FPGA is constructed as follows.Wherein master management unit, computing unit, PCIe interface control module and memory control unit are logic realization in FPGA, and DIMM internal storage location is that FPGA outside realizes.
The entirety that master management unit is responsible for system FPGA computing module controls, and comprises the reception of task to be calculated, the reception of data to be calculated and buffer memory, the process control of calculating and returning of result of calculation.
Concrete evaluation work is carried out in the order that computing unit is responsible for sending according to master management unit, and the DIMM internal storage location that the computing interval may have access in module reads data to be calculated.After calculating completes, result is returned to master management unit.
PCIe interface control module is responsible for the information such as calculation task, data to be calculated of distributing from universal processor module.Be in charge of the equipment hot swap of FPGA computing module, traffic monitoring, data integrity detection, Service Quality Management etc. simultaneously.
Memory control unit is responsible for the request of data received from master management unit or computing unit, the DIMM internal storage location of access fpga chip outside, and completes desired data read-write capability.
DIMM internal storage location is responsible for the temporary of data, provides reading and writing data function.
As shown in Figure 3, the calculation task treatment scheme based on the high-performance heterogeneous computing platforms of x86 architecture processor and FPGA is as follows:
1. the functional character of high-performance calculation task according to each FPGA computing module distributes by universal processor module, transmits the raw data needed for calculating simultaneously;
2. each FPGA computing module receives the calculation task distributed, and by the raw data buffer memory in DIMM internal storage location needed for calculating;
3. FPGA computing module calculates, and by PCIe bus interface, result is back to universal processor module after calculating;
4. each result of calculation gathers by universal processor module, forms the net result of high-performance calculation task.
Claims (7)
1., based on a high-performance heterogeneous computing platforms of x86 architecture processor and FPGA, on the basis of existing platform, it is characterized in that having the universal processor module of x86 architecture processor, PCIe SWITCH module and FPGA computing module;
Wherein universal processor module is responsible for the input of high performance tasks, output, calculation task scheduling, computational resource allocation, calculation task Row control and result of calculation and is collected and gather;
The built-in fpga chip of PCIe SWITCH module, is responsible for the interconnection between universal processor module and FPGA computing module and data transfer task;
FPGA computing module is used for needing the data of computing to be translated into result of calculation by internal logic, go forward side by side row relax and storage, the bus interface providing inquiry and control.
2. a kind of high-performance heterogeneous computing platforms based on x86 architecture processor and FPGA according to claim 1, is characterized in that described FPGA computing module comprises internal logic and realizes unit and external memory unit;
Internal logic realizes logical operation and the control that unit is responsible for the reception task of inner FPGA computing module;
External memory unit is responsible for the buffer memory of data, provides reading and writing data function.
3. a kind of high-performance heterogeneous computing platforms based on x86 architecture processor and FPGA according to claim 2, is characterized in that described internal logic realizes unit and comprises master management unit, computing unit, PCIe interface control module, memory control unit;
The entirety that master management unit is responsible for system FPGA computing module controls, and comprises the reception of task to be calculated, the reception of data to be calculated and buffer memory, the process control of calculating and returning of result of calculation;
Concrete evaluation work is carried out in the order that computing unit is responsible for sending according to master management unit, and the computing interval external memory unit that may have access in module reads data to be calculated.
4., after calculating completes, result is returned to master management unit;
PCIe interface control module is responsible for the information such as calculation task, data to be calculated of distributing from universal processor module, is in charge of the equipment hot swap of FPGA computing module, traffic monitoring, data integrity detection, Service Quality Management simultaneously;
Memory control unit is responsible for the request of data received from master management unit or computing unit, access external memory unit, and completes desired data read-write capability.
5. a kind of high-performance heterogeneous computing platforms based on x86 architecture processor and FPGA according to Claims 2 or 3, is characterized in that described external memory unit comprises DIMM internal storage location, is responsible for the temporary of data, provides reading and writing data function.
6. a kind of high-performance heterogeneous computing platforms based on x86 architecture processor and FPGA according to any one of claim 1-4, is characterized in that described computing platform calculation task treatment scheme is:
The functional character of high-performance calculation task according to each FPGA computing module distributes by universal processor module, transmits the raw data needed for calculating simultaneously;
Each FPGA computing module receives the calculation task distributed, and by the primary data cache needed for calculating;
FPGA computing module calculates, and by PCIe bus interface, result is back to universal processor module after calculating;
Each result of calculation gathers by universal processor module, forms the net result of calculation task.
7. the method based on the high-performance heterogeneous computing platforms process calculation task of x86 architecture processor and FPGA, a kind of high-performance heterogeneous computing platforms based on x86 architecture processor and FPGA according to any one of claim 1-5 realizes, and it is characterized in that treatment scheme is:
The functional character of high-performance calculation task according to each FPGA computing module distributes by universal processor module, transmits the raw data needed for calculating simultaneously;
Each FPGA computing module receives the calculation task distributed, and by the primary data cache needed for calculating;
FPGA computing module calculates, and by PCIe bus interface, result is back to universal processor module after calculating;
Each result of calculation gathers by universal processor module, forms the net result of calculation task.
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|---|---|---|---|---|
| CN106020425A (en) * | 2016-05-27 | 2016-10-12 | 浪潮(北京)电子信息产业有限公司 | FPGA heterogeneous acceleration calculating system |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101086729A (en) * | 2007-07-09 | 2007-12-12 | 西安飞鹰科技有限责任公司 | A dynamic reconfigurable high-performance computing method and device based on FPGA |
| CN101650639A (en) * | 2009-09-11 | 2010-02-17 | 成都市华为赛门铁克科技有限公司 | Storage device and computer system |
| CN101986305A (en) * | 2010-11-01 | 2011-03-16 | 华为技术有限公司 | File system operating method and communication device |
| CN102609389A (en) * | 2011-12-22 | 2012-07-25 | 成都傅立叶电子科技有限公司 | Digital signal processing platform achieved on basis of VPX bus |
| CN103020008A (en) * | 2012-12-26 | 2013-04-03 | 无锡江南计算技术研究所 | Reconfigurable micro server with enhanced computing power |
| CN103020002A (en) * | 2012-11-27 | 2013-04-03 | 中国人民解放军信息工程大学 | Reconfigurable multiprocessor system |
| US20130145431A1 (en) * | 2011-12-02 | 2013-06-06 | Empire Technology Development Llc | Integrated circuits as a service |
-
2015
- 2015-03-05 CN CN201510097483.6A patent/CN104657330A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101086729A (en) * | 2007-07-09 | 2007-12-12 | 西安飞鹰科技有限责任公司 | A dynamic reconfigurable high-performance computing method and device based on FPGA |
| CN101650639A (en) * | 2009-09-11 | 2010-02-17 | 成都市华为赛门铁克科技有限公司 | Storage device and computer system |
| CN101986305A (en) * | 2010-11-01 | 2011-03-16 | 华为技术有限公司 | File system operating method and communication device |
| US20130145431A1 (en) * | 2011-12-02 | 2013-06-06 | Empire Technology Development Llc | Integrated circuits as a service |
| CN102609389A (en) * | 2011-12-22 | 2012-07-25 | 成都傅立叶电子科技有限公司 | Digital signal processing platform achieved on basis of VPX bus |
| CN103020002A (en) * | 2012-11-27 | 2013-04-03 | 中国人民解放军信息工程大学 | Reconfigurable multiprocessor system |
| CN103020008A (en) * | 2012-12-26 | 2013-04-03 | 无锡江南计算技术研究所 | Reconfigurable micro server with enhanced computing power |
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| CN106776024B (en) * | 2016-12-13 | 2020-07-21 | 苏州浪潮智能科技有限公司 | Resource scheduling device, system and method |
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