CN106250349A - A kind of high energy efficiency heterogeneous computing system - Google Patents
A kind of high energy efficiency heterogeneous computing system Download PDFInfo
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- CN106250349A CN106250349A CN201610645582.8A CN201610645582A CN106250349A CN 106250349 A CN106250349 A CN 106250349A CN 201610645582 A CN201610645582 A CN 201610645582A CN 106250349 A CN106250349 A CN 106250349A
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- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
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Abstract
The invention discloses a kind of high energy efficiency heterogeneous computing system, including multiple server units, the corresponding station server of each server unit, every station server configures multiple FPGA boards；FPGA board, as isomery accelerator, uses PCIe interface to be connected with the CPU in same server unit by PCIe Switch；Switch is used to interconnect between server unit.Owing to fpga chip has the many advantages such as low-power consumption, dynamic reconfigurable, parallel processing, high-throughput and computation delay be low, become current server and strengthen a kind of ideal component that reconfigurability parallel computation is accelerated.High energy efficiency heterogeneous computing system provided by the present invention, the logic customizability taking full advantage of FPGA device is that server introduces reconfigurability, it is achieved that the lifting to the calculated performance of data-center applications.
Description
Technical field
The present invention relates to Heterogeneous Computing technical field, particularly relate to a kind of high energy efficiency heterogeneous computing system.
Background technology
Heterogeneous Computing (Heterogeneous computing) technology can obtain cost-effectively high-performance calculation ability,
Extensibility is good, it is high to calculate resource utilization, development potentiality is huge, has the most become the research in parallel/distribution calculating field
One of focus.Heterogeneous Computing is primarily referred to as using the calculation of the computing unit composition system of different architectural framework.
Common computing unit classification includes CPU, GPU, DSP, ASIC, FPGA etc..Although dedicated computing unit work frequency
Rate is relatively low, but has more computation capability, and overall performance/power dissipation ratio is the highest, is suitable for being applied to high-performance high energy
Imitate big data processing field.The design of CPU allows it compare and is good at process irregular data structure and uncertain access mode,
This kind of program task has the steps such as instruction scheduling, circulation, branch, logical judgment and the execution of complexity.And FPGA etc. are good at
Process rules data structure and measurable access mode, reach the optimization of overall performance by Heterogeneous Computing.
The energy consumption using the high performance computing system of CPU+GPU isomery framework is super large, uses lower power consumption to provide
More powerful computing capability becomes high-performance calculation and develops the problem that have to solve.
Summary of the invention
It is an object of the invention to provide a kind of high energy efficiency heterogeneous computing system, it is therefore intended that the logic utilizing FPGA device can
Customization is that server introduces reconfigurability and isomerism, it is achieved the lifting to the calculated performance of data-center applications.
For solving above-mentioned technical problem, the present invention provides a kind of high energy efficiency heterogeneous computing system, including:
Multiple server units, the corresponding station server of each server unit, every station server configures multiple FPGA plates
Card；Described FPGA board, as isomery accelerator, uses PCIe interface by PCIe Switch and same server unit
CPU be connected；Switch is used to interconnect between described server unit.
Alternatively,
The number of described FPGA board is two, is respectively provided with four input clocks: 100MHz PCIe3.0 clock,
The input of 133.33MHz differential clocks, the input of 125MHz differential clocks, the input of 50MHz clock.
Alternatively, by high-speed PCI e3.0x8 interface, dma mode is used to set up internal memory and the main frame of described FP GA board
Between the transmission of data.
Alternatively, described FPGA board uses the DDR4 with 8 ECC check codes, could support up 2 SODIMM bars, single
Bar maximum supports 8GB DDR4x72bit@1333MH z/2400MT/s.
Alternatively, described FPGA board includes that multiple computing unit, each computing unit include multiple treatment element, each
In computing unit, all for the treatment of element directly carries data processing pipeline.
Alternatively, also include:
Fault detect server, in real time detecting each server and the FPGA board that is connected with described server
Running status, generates fault message when detecting when running status breaks down.
Alternatively, also include:
Task scheduling server, after generating described fault message at described fault detect server, starts task weight
New scheduling operation, maintains system to continue normal work.
Alternatively, described fault detect server is additionally operable to when detecting that described FPGA board lost efficacy, and controls described
FPGA board carries out soft reboot or firmly restarts.
High energy efficiency heterogeneous computing system provided by the present invention, including multiple server units, each server unit pair
Answering a station server, every station server configures multiple FPGA boards；FPGA board, as isomery accelerator, uses PCIe interface to lead to
Cross PCIe Switch to be connected with the CPU in same server unit；Switch is used to interconnect between server unit.
Owing to fpga chip has the many advantages such as low-power consumption, dynamic reconfigurable, parallel processing, high-throughput and computation delay be low, become
A kind of ideal component that reconfigurability parallel computation is accelerated is strengthened for current server.High energy efficiency isomery meter provided by the present invention
Calculation system, the logic customizability taking full advantage of FPGA device is that server introduces reconfigurability, it is achieved that in data
The lifting of the calculated performance of heart application.
Accompanying drawing explanation
For the clearer explanation embodiment of the present invention or the technical scheme of prior art, below will be to embodiment or existing
In technology description, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this
Some bright embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to root
Other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 is the structured flowchart of a kind of detailed description of the invention of high energy efficiency heterogeneous computing system provided by the present invention；
Showing of a kind of detailed description of the invention of the server-FPGA board structure figure that Fig. 2 is provided by the embodiment of the present invention
It is intended to；
Fig. 3 is to calculate the structured flowchart of FPGA board used in platform；
Fig. 4 is synovial membrane Design of Observer flow chart；
Fig. 5 is the Organization Chart of the another kind of detailed description of the invention of high energy efficiency heterogeneous computing system provided by the present invention.
Detailed description of the invention
In order to make those skilled in the art be more fully understood that the present invention program, below in conjunction with the accompanying drawings and detailed description of the invention
The present invention is described in further detail.Obviously, described embodiment be only a part of embodiment of the present invention rather than
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creative work premise
Lower obtained every other embodiment, broadly falls into the scope of protection of the invention.
A kind of structured flowchart such as Fig. 1 institute of the detailed description of the invention of high energy efficiency heterogeneous computing system provided by the present invention
Showing, this system includes:
Multiple server units 1, the corresponding station server 11 of each server unit 1, the configuration of every station server is multiple
FPGA board 12；Described FPGA board 12, as isomery accelerator, uses PCIe interface by PCIe Switch and same clothes
CPU in business device unit is connected；Switch 2 (not shown) is used to interconnect between described server unit 1.
High energy efficiency heterogeneous computing system provided by the present invention, including multiple server units, each server unit pair
Answering a station server, every station server configures multiple FPGA boards；FPGA board, as isomery accelerator, uses PCIe interface to lead to
Cross PCIe Switch to be connected with the CPU in same server unit；Switch is used to interconnect between server unit.
Owing to fpga chip has the many advantages such as low-power consumption, dynamic reconfigurable, parallel processing, high-throughput and computation delay be low, become
A kind of ideal component that reconfigurability parallel computation is accelerated is strengthened for current server.High energy efficiency isomery meter provided by the present invention
Calculation system, the logic customizability taking full advantage of FPGA device is that server introduces reconfigurability, it is achieved that in data
The calculated performance of heart application promotes.
It is pointed out that in high energy efficiency heterogeneous computing system provided by the present invention, the quantity of server can basis
Actual production environment is configured so that it is has and can carry the ability of medium-scale application under actual production environment.
On the basis of above-described embodiment, in high energy efficiency heterogeneous computing system provided by the present invention, described FPGA board
Number can be specially two, be respectively provided with four input clocks: when 100MHz PCIe3.0 clock, 133.33MHz difference
Clock input, the input of 125MHz differential clocks, the input of 50MHz clock.
Showing of a kind of detailed description of the invention of the server-FPGA board structure figure provided such as Fig. 2 embodiment of the present invention
Shown in being intended to, FPGA board uses PCIe interface, FPGA0 with FPGA1 is connected by PCIe Switch with CPU.If every piece
FPGA board performs identical task, i.e. forms 2 parallelization data paths.By high-speed PCI e3.0x8 interface, use
Dma mode sets up the transmission of data between internal memory and the main frame of described FPGA board.
Calculate the structured flowchart of FPGA board used by platform as shown in Figure 3.For improving the reliability of internal storage access, enter one
Step ground, FPGA board can use the DDR4 with 8 ECC check codes, could support up 2 SODIMM bars, and wall scroll maximum supports 8GB
DDR4x72bit@1333MHz/2400MT/s.When FPGA operating frequency reaches 300MHz, single-chip calculated performance theoretical peak
Up to 1.3Tflop/s.Above-mentioned for multiple stage server is connected composition plateform system by network and then formation has high-performance, low
The calculating platform of power consumption.
This platform model is host-guest architecture, and it performs model can be divided into host program and kernel program.Kernel is to hold
The core of row model, can perform on equipment.Before a kernel performs, need to specify the scope of a N-dimensional
(NDRange).One NDRange can be one-dimensional, a two-dimentional or three-dimensional index space, also needs to specify the overall situation simultaneously
The number of working node, the number of working group's interior joint.Such as the overall situation working node in the range of 12,12}, the joint of working group
Point range is that { 4,4}, a total of 9 working groups, synovial membrane Design of Observer flow chart is as shown in Figure 4.Definition working group is mainly
The program that only need to exchange data for some in group provides convenient, and working node number can be limited by equipment.If one
Equipment has 1024 to process node, the then vector of 1024 dimensions, and each node calculates and the most just can complete.And if an equipment is only
128 are had to process node, then each node needs to calculate 8 times.Rationally arranging interstitial content, working group's number can improve program
Degree of parallelism.
Heterogeneous computing platforms based on FPGA uses advanced language programming model development such as OpenCL language etc..Compare tradition
The hardware description language development modes such as Verilog, VHDL, use the high-level language construction cycle significantly to shorten, the most ripe BSP
Kit enables calling program to be deployed to rapidly in FPGA board system.
Organization Chart such as Fig. 5 institute of the another kind of detailed description of the invention of high energy efficiency heterogeneous computing system provided by the present invention
Show, use single cpu server to add as isomery as elementary cell, the FPGA board of every station server 2 pieces of PCIe interface of configuration
Speed device.Platform is disposed by multiple elementary cells and is formed, and uses 10,000,000,000 switch interconnection between server.
In the present embodiment, FPGA board can include that multiple computing unit, each computing unit include multiple treatment element,
In each computing unit, all for the treatment of element directly carries data processing pipeline.
Further, the embodiment of the present invention can also include:
Fault detect server, in real time detecting each server and the FPGA board that is connected with described server
Running status, generates fault message when detecting when running status breaks down.
And task scheduling server, after generating described fault message at described fault detect server, start and appoint
Business reschedules operation, maintains system to continue normal work.
Described fault detect server is additionally operable to, when detecting that described FPGA board lost efficacy, control described FPGA board and enter
Row soft reboot or firmly restart.
Fault detect is responsible for each server of real-time monitor and detection and is connected with server with task management server
The running status of FPGA board.When certain the FGPA board on platform is hung up for some reason, at its subordinate server
Can detect and this fault message is sent to fault detect server.Then, task management server startup task is adjusted again
Degree operation, maintains system to continue normal work.If server normal operation, can be to the local FPGA of fault detect server reflection
Work state information.Based on these information, fault detect server can carry out soft reboot to a FPGA board lost efficacy
Or firmly restart, so that reconfigurable computing platform based on FPGA recovers more available FPGA board.
Heterogeneous computing platforms based on FPGA uses advanced language programming model development, a Centroid be responsible for task
Distribution and scheduling, multiple servers is responsible for the concrete calculating task of application.In server, FPGA is responsible for the computation-intensive portion of task
Point, the administrative section of subtask in CPU charge server, its Task Assigned Policy can carry out flexible customization according to application difference.
FPGA board equipment is divided into multiple computing unit, and each computing unit is further divided into multiple treatment element (PE), each
In computing unit, all of PE directly carries data processing pipeline.
High energy efficiency heterogeneous computing system provided by the present invention, the logic customizability taking full advantage of FPGA device is clothes
Business device introduces reconfigurability, and achieves the lifting of the calculated performance to data-center applications, and has certain fault-tolerant energy
Power and meet the cost constraint of data center.
In this specification, each embodiment uses the mode gone forward one by one to describe, and what each embodiment stressed is and other
The difference of embodiment, between each embodiment, same or similar part sees mutually.For filling disclosed in embodiment
For putting, owing to it corresponds to the method disclosed in Example, so describe is fairly simple, relevant part sees method part
Illustrate.
Professional further appreciates that, in conjunction with the unit of each example that the embodiments described herein describes
And algorithm steps, it is possible to electronic hardware, computer software or the two be implemented in combination in, in order to clearly demonstrate hardware and
The interchangeability of software, the most generally describes composition and the step of each example according to function.These
Function performs with hardware or software mode actually, depends on application-specific and the design constraint of technical scheme.Specialty
Technical staff specifically should can be used for using different methods to realize described function to each, but this realization should not
Think beyond the scope of this invention.
The method described in conjunction with the embodiments described herein or the step of algorithm can direct hardware, processor be held
The software module of row, or the combination of the two implements.Software module can be placed in random access memory (RAM), internal memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, depositor, hard disk, moveable magnetic disc, CD-ROM or technology
In any other form of storage medium well known in field.
Above high energy efficiency heterogeneous computing system provided by the present invention is described in detail.Used herein specifically
Principle and the embodiment of the present invention are set forth by individual example, and the explanation of above example is only intended to help and understands the present invention
Method and core concept.It should be pointed out that, for those skilled in the art, former without departing from the present invention
On the premise of reason, it is also possible to the present invention is carried out some improvement and modification, these improve and modification also falls into right of the present invention and wants
In the protection domain asked.
Claims (8)
1. a high energy efficiency heterogeneous computing system, it is characterised in that including:
Multiple server units, the corresponding station server of each server unit, every station server configures multiple FPGA boards；Institute
State FPGA board and pass through PCIe Switch and the CPU in same server unit as isomery accelerator, employing PCIe interface
It is connected；Switch is used to interconnect between described server unit.
2. high energy efficiency heterogeneous computing system as claimed in claim 1, it is characterised in that
The number of described FPGA board is two, is respectively provided with four input clocks: 100MHzPCIe3.0 clock, 133.33MHz
Differential clocks input, the input of 125MHz differential clocks, the input of 50MHz clock.
3. high energy efficiency heterogeneous computing system as claimed in claim 2, it is characterised in that by high-speed PCI e3.0x8 interface, adopt
The transmission of data between internal memory and the main frame of described FPGA board is set up with dma mode.
4. high energy efficiency heterogeneous computing system as claimed in claim 3, it is characterised in that described FPGA board uses has 8
The DDR4 of ECC check code, could support up 2 SODIMM bars, and wall scroll maximum supports 8GB DDR4x72bit@1333MHz/
2400MT/s。
5. high energy efficiency heterogeneous computing system as claimed in claim 4, it is characterised in that described FPGA board includes multiple calculating
Unit, each computing unit includes multiple treatment element, and in each computing unit, all for the treatment of element directly carries at data
Reason streamline.
6. the high energy efficiency heterogeneous computing system as described in any one of claim 1 to 5, it is characterised in that also include:
Fault detect server, in real time detecting each server and the operation of FPGA board being connected with described server
State, generates fault message when detecting when running status breaks down.
7. high energy efficiency heterogeneous computing system as claimed in claim 6, it is characterised in that also include:
Task scheduling server, after generating described fault message at described fault detect server, startup task is adjusted again
Degree operation, maintains system to continue normal work.
8. high energy efficiency heterogeneous computing system as claimed in claim 7, it is characterised in that described fault detect server is additionally operable to
When detecting that described FPGA board lost efficacy, control described FPGA board and carry out soft reboot or firmly restart.
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