CN103020008A - Reconfigurable micro server with enhanced computing power - Google Patents
Reconfigurable micro server with enhanced computing power Download PDFInfo
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- CN103020008A CN103020008A CN2012105756482A CN201210575648A CN103020008A CN 103020008 A CN103020008 A CN 103020008A CN 2012105756482 A CN2012105756482 A CN 2012105756482A CN 201210575648 A CN201210575648 A CN 201210575648A CN 103020008 A CN103020008 A CN 103020008A
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Abstract
The invention provides a reconfigurable micro server with enhanced computing power, which comprises a microprocessor, a system bus, an internal memory, reconfigurable acceleration units and an input/output peripheral. The microprocessor, the internal memory and the input/output peripheral are connected to the system bus so that the microprocessor can have data exchange with the internal memory and the input/output peripheral through the system bus; the microprocessor is directly connected with the reconfigurable acceleration units which are connected to the system bus so as to have data exchange with the internal memory and the input/output peripheral through the system bus; the reconfigurable units comprise at least one of a reconfigurable instruction extension unit, a reconfigurable hardware thread unit and a reconfigurable task acceleration unit.
Description
Technical field
The present invention relates to the computing technique field, more particularly, the present invention relates to the restructural microserver that a kind of computing power strengthens.
Background technology
Continuous increase along with the server scale in data center and enterprise-level field, the low problem of data center and large system energy efficiency is more given prominence to and is serious, system power dissipation unnecessary consumption and waste, the power consumption utilization factor less than 10% of data center, the overall Cost Problems that brings thus is also outstanding all the more.Data show that the energy expenditure of global annual server consumption has accounted for half of server buying expenses.
Under such background, microserver (Micro Server) progresses into people's the visual field, the proposition of its concept can be traced back to 2009 the earliest, it is a kind of innovative idea of about cloud data center the basis of low-power server demand being advocated in Intel, the Main Processor Unit manufacturer that comprises Intel, AMD, ARM has all released the low power processor of using towards microserver, the main servers manufacturers such as HP, Dell its microserver product that also released one after another.Microserver adopts novel low power processor, it is higher to compare the traditional server efficiency, volume is less, and therefore integration density is higher in the cabinet of same size, is mainly used at present network services such as the less unique host of computational resource requirements, the supports of the static Web page.
Efficiency and the node density of present microserver in order to improve system, main low power processor or other low-power consumption miniaturized device of adopting come constructing system, cause its absolute performance in each side such as computing power, storage capacity, I/O abilities to be lower than existing standard server, limited application and the popularization of microserver.
Therefore, hope can provide a kind of computing power strengthen and server that can not cause system power dissipation unnecessary consumption and waste.
Summary of the invention
Technical matters to be solved by this invention is for having defects in the prior art, providing a kind of computing power strengthen and server that can not cause system power dissipation unnecessary consumption and waste.
According to the present invention, the restructural microserver that provides a kind of computing power to strengthen comprises: microprocessor, system bus, internal memory, restructural acceleration components and input/output peripheral; Wherein, microprocessor, internal memory and input/output peripheral are connected to system bus, thereby microprocessor carries out exchanges data by system bus and internal memory and input/output peripheral; And microprocessor is connected directly to the restructural acceleration components; And the restructural acceleration components is connected to system bus, thereby carries out exchanges data by system bus and internal memory and input/output peripheral; Wherein, the restructural acceleration components comprises at least one in reconfigurable instruction expanding element, reconfigurable hardware thread units and the reconfigurable task accelerator module.
Preferably, the restructural acceleration components adopts programmable logic device (PLD) to realize.
Preferably, the reconfigurable instruction expanding element directly links to each other with microprocessor, is used for certain operations or the operation form with specific instruction extension unit is realized; And the reconfigurable instruction expanding element directly links to each other with the data path of microprocessor, and directly carries out certain operations or operation with the form realization of specific instruction extension unit.
Preferably, the a plurality of hardware threads that comprise in the reconfigurable hardware thread units, described a plurality of hardware thread moves in order to realize the calculation function identical with software thread in the restructural acceleration components, thereby realizes the thread-level of software application is accelerated by the mode of hardware thread.
Preferably, the reconfigurable task accelerator module is used for realization to accelerate the task level of using, and be reconfigured as and have the dedicated hardware logic unit of realizing the complete application task ability, and the reconfigurable task accelerator module is directly controlled and access memory and input/output peripheral by the privately owned interface of system bus or restructural acceleration components, thereby whole application load is transferred to the restructural acceleration components from microprocessor.
The invention provides a kind of with low-power consumption microprocessor and the closely-coupled restructural microserver of restructural acceleration components system architecture, can be by the restructural acceleration components be carried out hardware reconstruct, realize the restructural computing accelerating module of object-oriented application demand, the arithmetic capability of enhancing system improves system performance and efficient.And restructural microserver provided by the invention system realizes optimizing application and computing acceleration to various scale different characteristics in instruction-level, thread-level, task level three logical levels structure and method of strengthening the system-computed abilities from low to high.
Description of drawings
By reference to the accompanying drawings, and by with reference to following detailed description, will more easily to the present invention more complete understanding be arranged and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the functional block diagram according to the restructural microserver of the computing power enhancing of first embodiment of the invention.
Fig. 2 schematically shows the functional block diagram according to the restructural microserver of the computing power enhancing of second embodiment of the invention.
Need to prove that accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings content of the present invention is described in detail.
Along with the development of semiconductor technology and the theory of computation, some unconventional form of calculation are also risen gradually, and it is exactly a very important class that restructural calculates.Hardware is fixed in the conventional computer system, immutable, people are by programming to realize the functions such as calculating to the software that operates on its hardware, restructural calculate to adopt the FPGA(field programmable gate array) etc. programmable logic device (PLD), can be by its hardware logic be programmed, the 26S Proteasome Structure and Function of hardware in the change system, thereby improved greatly the dirigibility of system, by realizing the specialized hardware structure towards application-specific, can greatly improve overall performance and the efficient of system.Simultaneously, the power consumption of the programming devices such as FPGA that restructural calculating is adopted is also relatively low, if can combine with microserver, must when keeping low-power consumption, improve greatly the processing power of microserver.
And, structure and methods in from low to high three the logical levels realization system-computed abilities enhancing of instruction-level, thread-level, task level, can flexible combination and reconstruct, realization is accelerated optimizing application and the computing of various scales, different characteristic, gives full play to the restructural computing acceleration capacity of restructural microserver.
Thus, the invention provides a kind of with low-power consumption microprocessor and the closely-coupled restructural microserver of restructural acceleration components system architecture, can be by the restructural acceleration components be carried out hardware reconstruct, realize the restructural computing accelerating module of object-oriented application demand, the arithmetic capability of enhancing system improves system performance and efficient.And restructural microserver provided by the invention system realizes optimizing application and computing acceleration to various scale different characteristics in instruction-level, thread-level, task level three logical levels structure and method of strengthening the system-computed abilities from low to high.
The＜the first embodiment 〉
Fig. 1 schematically shows the functional block diagram according to the restructural microserver of the computing power enhancing of first embodiment of the invention.
The restructural microserver that strengthens according to the computing power of the embodiment of the invention comprises: microprocessor 10, system bus 100, internal memory 20, restructural acceleration components 40 and input/output peripheral (hereinafter to be referred as the I/O peripheral hardware) 30.
Wherein, microprocessor 10, internal memory 20 and input/output peripheral 30 are connected to system bus 100, thereby microprocessor 10 carries out exchanges data by system bus 100 and internal memory 20 and input/output peripheral 30.
For example, I/O peripheral hardware 30 includes but not limited to the equipment such as hard disk, network, USB.
Wherein, for example, restructural acceleration components 40 comprises: reconfigurable instruction expanding element 41, reconfigurable hardware thread units 42 and reconfigurable task accelerator module 43.
That is to say, the restructural acceleration components can be reconstructed into the restructural computing accelerating modules such as reconfigurable instruction expanding element 41, reconfigurable hardware thread units 42, reconfigurable task accelerator module 43, thereby the calculating that is implemented in instruction-level, thread-level, three levels of task level is accelerated.
And, although in above-mentioned specific embodiment, show the example that restructural acceleration components 40 comprises reconfigurable instruction expanding element 41, reconfigurable hardware thread units 42 and reconfigurable task accelerator module 43, but it should be understood that, when specific implementation, restructural acceleration components 40 may include only one or two in reconfigurable instruction expanding element 41, reconfigurable hardware thread units 42 and the reconfigurable task accelerator module 43.
Wherein, reconfigurable instruction expanding element 41 directly links to each other with microprocessor, is used for certain operations or the operation form with specific instruction extension unit is realized; And reconfigurable instruction expanding element 41 directly links to each other with the data path of microprocessor, and directly carries out certain operations or operation with the form realization of specific instruction extension unit.
Computing or operation commonly used in using for some, can with its abstract be extended instruction, in the reconfigurable instruction expanding element, realize, realize the computing acceleration as the instruction set extension of microprocessor.Reconfigurable instruction expanding element 41 directly closely links to each other with microprocessor by Microprocessor Interface, the computing that some are commonly used or efficient is lower or the form that operates with specific instruction extension unit can be realized, optimize and improve execution performance and the efficient of original operation by hardware flowing water or parallel mode.And, reconfigurable instruction expanding element 41 directly links to each other with the data path of microprocessor, when the low exclusive disjunction of the intrinsic instruction efficient of processor is resource-constrained, this part command operating can carried out heavy instruction extension unit 41, thereby expanded the calculation resources of microprocessor, strengthened its arithmetic capability.
The a plurality of hardware threads that comprise in the reconfigurable hardware thread units 42 (for example the hardware thread among Fig. 11, hardware thread 2 ..., hardware thread 3, hardware thread 4), described a plurality of hardware thread moves in order to realize the calculation function identical with software thread in the restructural acceleration components, thereby realizes the thread-level of software application is accelerated by the mode of hardware thread.
Reconfigurable hardware thread units 42 is realized the thread-level of traditional software application is accelerated by the mode of hardware thread.Hardware thread operates on the restructural acceleration components, can realize the calculation function identical with software thread, can some calculated amount in using are large, and the limited thread of performance is transferred in the reconfigurable hardware thread units, with the form realization of hardware thread.The computing acceleration capacity of reconfigurable hardware thread units 42 is mainly reflected in two aspects, the degree of parallelism that can improve thread on the one hand, the traditional software thread operates in the microprocessor, although conceptive be executed in parallel, but limited computational resource that in fact can only multiplex processor inside, and in the reconfigurable hardware thread units can a large amount of hardware thread unit of instantiation, for each thread provides independently computational resource, realize real thread parallel; Operational performance and the efficient that can improve single thread on the other hand, the reconfigurable hardware thread units can be reconstructed into the dedicated hardware logic structure for optimizing application, the overhead of having avoided instruction scheduling, process switching etc. to bring, can also improve operational performance by flowing water, the mode such as parallel, realize the raising of thread execution efficient and the enhancing of operational performance.
Reconfigurable task accelerator module 43 is used for realization to accelerate the task level of using, and it can according to practical application request, be reconstructed into the dedicated hardware logic unit with realization complete application task ability.And, reconfigurable task accelerator module 43 can directly be controlled and access memory 20 and input/output peripheral 30 by the privately owned interface of system bus or restructural acceleration components, thereby whole application load is transferred to the restructural acceleration components from microprocessor, reduced the computing load of microprocessor, simultaneously can also improve its operational performance by hardware optimization methods such as streamlined, parallelizations, realize the task level computing acceleration of using.
In the application of restructural microserver, above-mentioned three kinds of functional parts can be according to application characteristic and actual demand, and flexible combination and reconstruct realize the efficient collaborative of microprocessor and restructural acceleration components, improve the efficient of the whole operational performance of system.
The＜the second embodiment 〉
Fig. 2 schematically shows the functional block diagram according to the restructural microserver of the computing power enhancing of second embodiment of the invention.
Different from the first embodiment shown in Figure 1 is, in the restructural microserver that the computing power according to second embodiment of the invention shown in Figure 2 strengthens, restructural acceleration components 30 can connect independently internal memory 21, independently I/O peripheral hardware 31 and other expansion interface, thus expansion and strengthen system resource and ability.
In addition, need to prove, unless otherwise indicated, otherwise the term in the instructions " first ", " second ", " the 3rd " etc. describe each assembly of only being used for distinguishing instructions, element, step etc., rather than are used for logical relation between each assembly of expression, element, the step or ordinal relation etc.
Be understandable that although the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not to limit the present invention.For any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (5)
1. the restructural microserver that computing power strengthens is characterized in that comprising: microprocessor, system bus, internal memory, restructural acceleration components and input/output peripheral;
Wherein, microprocessor, internal memory and input/output peripheral are connected to system bus, thereby microprocessor carries out exchanges data by system bus and internal memory and input/output peripheral;
And microprocessor is connected directly to the restructural acceleration components;
And the restructural acceleration components is connected to system bus, thereby carries out exchanges data by system bus and internal memory and input/output peripheral;
Wherein, the restructural acceleration components comprises at least one in reconfigurable instruction expanding element, reconfigurable hardware thread units and the reconfigurable task accelerator module.
2. the restructural microserver of computing power enhancing according to claim 1 is characterized in that, the restructural acceleration components adopts programmable logic device (PLD) to realize.
3. the restructural microserver that strengthens of computing power according to claim 1 and 2 is characterized in that the reconfigurable instruction expanding element directly links to each other with microprocessor, is used for certain operations or the operation form realization with specific instruction extension unit; And the reconfigurable instruction expanding element directly links to each other with the data path of microprocessor, and directly carries out certain operations or operation with the form realization of specific instruction extension unit.
4. the restructural microserver that strengthens of computing power according to claim 1 and 2, it is characterized in that, the a plurality of hardware threads that comprise in the reconfigurable hardware thread units, described a plurality of hardware thread moves in order to realize the calculation function identical with software thread in the restructural acceleration components, thereby realizes the thread-level of software application is accelerated by the mode of hardware thread.
5. the restructural microserver that strengthens of computing power according to claim 1 and 2, it is characterized in that, the reconfigurable task accelerator module is used for realization to accelerate the task level of using, and be reconfigured as and have the dedicated hardware logic unit of realizing the complete application task ability, and the reconfigurable task accelerator module is directly controlled and access memory and input/output peripheral by the privately owned interface of system bus or restructural acceleration components, thereby whole application load is transferred to the restructural acceleration components from microprocessor.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104657330A (en) * | 2015-03-05 | 2015-05-27 | 浪潮电子信息产业股份有限公司 | High-performance heterogeneous computing platform based on x86 architecture processor and FPGA |
| CN106464685A (en) * | 2014-11-04 | 2017-02-22 | 华为技术有限公司 | Adaptive allocation of server resources |
| WO2018157836A1 (en) * | 2017-03-02 | 2018-09-07 | 腾讯科技（深圳）有限公司 | Resource management method for programmable hardware, programmable hardware device, and storage medium |
| CN109254859A (en) * | 2018-09-12 | 2019-01-22 | 中国人民解放军国防科技大学 | Multilayer-control self-adaptive micro-service system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101630305A (en) * | 2008-07-16 | 2010-01-20 | 中国人民解放军信息工程大学 | Flexible management method for reconfigurable components in high-efficiency computer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101630305A (en) * | 2008-07-16 | 2010-01-20 | 中国人民解放军信息工程大学 | Flexible management method for reconfigurable components in high-efficiency computer |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106464685A (en) * | 2014-11-04 | 2017-02-22 | 华为技术有限公司 | Adaptive allocation of server resources |
| CN106464685B (en) * | 2014-11-04 | 2019-08-27 | 华为技术有限公司 | A kind of method and server of dynamic allocation medium server resource |
| CN104657330A (en) * | 2015-03-05 | 2015-05-27 | 浪潮电子信息产业股份有限公司 | High-performance heterogeneous computing platform based on x86 architecture processor and FPGA |
| WO2018157836A1 (en) * | 2017-03-02 | 2018-09-07 | 腾讯科技（深圳）有限公司 | Resource management method for programmable hardware, programmable hardware device, and storage medium |
| CN109254859A (en) * | 2018-09-12 | 2019-01-22 | 中国人民解放军国防科技大学 | Multilayer-control self-adaptive micro-service system |
| CN109254859B (en) * | 2018-09-12 | 2021-10-26 | 中国人民解放军国防科技大学 | Multilayer-control self-adaptive micro-service system |
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