CN105630735A - Coprocessor based on reconfigurable computational array - Google Patents
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- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
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Abstract
The invention relates to a coprocessor based on a reconfigurable computational array. The coprocessor comprises a main controller which receives control information sent by an external universal processor, then analyzes the control information and sends out a corresponding configuration instruction, a reconfiguration controller which sends out the configuration information according to an algorithm parameter in the configuration instruction, an operation core unit which receives the configuration information and completes basic computation such as complex multiplication, complex addition and real multiplication, and a DMA unit which receives a transmission parameter of the configuration instruction and carries out data among an external DDR, an internal storage module and the main controller, wherein the configuration instruction comprises the transmission parameter and the algorithm parameter, and the configuration information comprises an execution signal used for selecting and organizing a logic algorithm in the operation core unit and an internal network gating signal. The coprocessor has the advantages of being good in computing performance and small in area consumption.
Description
Technical field
The present invention relates to the coprocessor of reconfigureable computing array.
Background technology
Along with the progress of science and technology, people are more and more higher to the requirement of calculated performance, and high performance signal process is widely used in the fields such as image procossing, scientific algorithm and Industry Control. In addition, these high performance signal process Application Areass comprising advanced signal process technology and intensive calculations work are also improving year by year for the real-time of system and the requirement of versatility, and the calculation requirement of computing system is also more and more higher.
Existing general procedure device, comprise CPU(CentralProcessingUnit, central processing unit) and DSP (DigitalSignalProcessing, digital signal processing), the realization of high performance signal Processing Algorithm can also be completed, but still there is following problem: general procedure device is in order to realize versatility, structure is comparatively complicated, needing to pay bigger power consumption and area cost for floating-point matrix operation, general procedure device makes it realize consuming the long time at intensive algorithm based on the feature that instruction stream is executed the task in addition.
Along with the development of semiconductor fabrication, fpga logic capacity greatly promotes and also makes large-scale digital circuitry can be mapped on the FPGA chip of monolithic, but FPGA is based on searching table (LookUpTable, LUT) chip area that implementation determines it is much bigger compared to application specific integrated circuit (ApplicationSpecificIntegratedCircuit, ASIC).
It is for the special accelerating hardware module of specific algorithm design that another kind improves the mentality of designing of calculated performance, such as special FFT module, matrix inversion module and filtering operation module etc., but integrated too much accelerating module can strengthen hardware resource and area overhead undoubtedly in a system.
Summary of the invention
It is an object of the invention to provide a kind of coprocessor based on reconfigurable hardware, it may also be useful to fixing hardware computation resource, the acceleration of algorithms of different can be realized by configuring the change of information. For achieving the above object, the coprocessor of the present invention comprises
Principal controller, receives the control information that outside general procedure device sends, then resolves described control information, and send corresponding configuration-direct, and described configuration-direct comprises transmission parameter and algorithm parameter;
Reconfigurable controller, according to the algorithm parameter in described configuration-direct, sends configuration information, and described configuration information is for selecting and organizes the executive signal of the logic algorithm in arithmetic core unit and inner network gating signal;
Arithmetic core unit, receives described configuration information, completes the fundamental operation taken advantage of again, be added with, take advantage of in fact according to configuration information;
DMA unit, receives the transmission parameter of described configuration-direct, carries out outside DDR and the carrying of the data between storage inside module, principal controller.
The further design of described reconfigurable coprocessor is, described transmission parameter comprises transfer and counts, transfer start address, data transfer direction and data mode of transport; Described algorithm parameter comprises computing type and computing is counted.
The further design of described reconfigurable coprocessor is, described arithmetic core unit comprises reconfigureable computing array.
The further design of described reconfigurable coprocessor is, described reconfigureable computing array is made up of the computing array of coarsness, being integrated with six reconfigurable processing units, reconfigureable computing array can realize reconstruct between the reconstruct of reconfigurable processing unit inside and reconfigurable processing unit.
The further design of described reconfigurable coprocessor is, described arithmetic core unit also comprises some multi-path choice devices and input-output register, and described multi-path choice device, input-output register communicate to connect with reconfigureable computing array respectively.
The further design of described reconfigurable coprocessor is, configuration information comprises computing type and computing data.
The further design of described reconfigurable coprocessor is, also comprises AXI interface, and described AXI interface is used for being connected principal controller with outside general procedure device;
The further design of described reconfigurable coprocessor is, also comprises memory module, for receive arithmetic core unit, the data of principal controller and store.
The further design of described reconfigurable coprocessor is, principal controller comprises
Device configuration register, for storing the mode of operation of reconfigurable processing core, has holotype, from pattern, debugging mode, interrupts pattern and query pattern;
Computing configuration register, for storing described algorithm parameter, comprises computing type, and computing is counted, digital data transmission start address;
Status register, for storing the state of reconfigurable coprocessor.
The further design of described reconfigurable coprocessor is, reconfigurable controller comprises reconstituted state machine unit, heavy register unit and algorithm sub-controller, and algorithm sub-controller comprises FFT controller, FIR controller, relevant control device, addition controller, multiplication controller, dot product controller, conjugation controller, transposition controller, Covariance Controller, division controller, plural number ask mould controller, surely floating change over controller and matrix inversion controller.
The advantage of the present invention is as follows:
1) calculated performance is good; Compared to the system structure of DSP based on instruction stream, this coprocessor can reach higher efficiency based on the structure of configuration flow, after principal controller receives exterior arrangement, can again organize the interconnection mode between reconfigureable computing array according to configuration information. The scale being directed to computing array, have also been made optimization process to each subalgorithm supported in this system, reaches optimum performance.
2) area consumption is little; Completing same function, realize area based on the FPGA searching table and realize much bigger than what application specific integrated circuit adopted hardwire, in the chip design field that area requirements is very harsh, the existing way of coprocessor has very big area advantage.
Accompanying drawing explanation
Fig. 1 is the coprocessor overall architecture schematic diagram of the reconfigureable computing array of the present invention.
Fig. 2 is the workflow schematic diagram of the coprocessor of reconfigureable computing array.
Fig. 3 is the module diagram of the coprocessor of reconfigureable computing array.
Fig. 4 is the schematic diagram of reconfigureable computing array.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the coprocessor based on reconfigureable computing array of the present invention is described in detail.
Such as Fig. 1, coprocessor is primarily of principal controller, reconfigurable controller, arithmetic core unit and DMA unit composition. Principal controller, receives the control information that outside general procedure device sends, then resolves control information, and send corresponding configuration-direct. Reconfigurable controller, according to the described configuration-direct that principal controller sends, sends configuration information, and described configuration information is for selecting and organize the logic algorithm in arithmetic core unit and changes the internet gated fashion of arithmetic core unit. Arithmetic core unit, receives described configuration information, completes according to configuration information to take advantage of again, is added with, real the fundamental operation such as takes advantage of. DMA unit, receives described configuration information, carries out outside DDR and the carrying of the data between storage inside module, principal controller.
Should start based on the coprocessor of reconfigureable computing array and need outside general procedure device configuration. Control information is imported into by AXI interface, is stored in the register of principal controller. Principal controller comprises device configuration register, computing configuration register, status register and abnormal interruption register, and above-mentioned Parasites Fauna is for receiving configuration information and the information of characterization system state.
Configuration information is resolved by principal controller, contains the mode of operation of reconfigurable processing core, have holotype in device configuration register, from pattern, debugging mode, interrupts pattern and query pattern.
Further, completing each parameter of specific algorithm needed for computing configuration register contains, this parameter comprises computing type, and computing is counted, digital data transmission start address etc. Whether whether status register opening can be read, and indicates which kind of pattern this processor core is operated in, accept effectively to configure information, busy, whether the states such as interruption occurs. Outside general procedure device can read the parameter of coprocessor state register, to determine next step control information exporting to principal controller.
As shown in Figure 2, after coprocessor initialize, general procedure device is sent control information to coprocessor by AXI interface, after principal controller receives and confirms control information effectively, control information is resolved and is passed to reconfigurable controller and DMA respectively.
Reconfigurable controller is the main modular of execution algorithm control and operation, and principal controller is sent to the algorithm parameter in the configuration-direct of reconfigurable controller, and algorithm parameter comprises computing type and computing is counted. Reconfigurable controller just can start corresponding algorithm sub-controller according to these information. Meanwhile, DMA also receives the transmission parameter in the configuration-direct of principal controller, comprises transfer and counts, transfer start address, data transfer direction and data mode of transport. Computing source data is moved into from DDR and the output of result data is all completed by DMA, and after write data complete, DMA can notify principal controller, and for distributing next step task, result data have also been carried end with DMA by the completing an of algorithm. After reconfigurable controller completes to complete with DMA carrying source data, reconfigurable controller just can start computing.
Reconfigurable controller comprises reconstituted state machine unit, heavy register unit and algorithm sub-controller. Algorithm sub-controller comprises FFT controller, FIR controller, relevant control device, addition controller, multiplication controller, dot product controller, conjugation controller, transposition controller, Covariance Controller, division controller, plural number ask mould controller, surely floating change over controller and matrix inversion controller, see Fig. 3.
Reconfigurable controller receives configuration-direct from principal controller and resolves, the algorithm executive signal sent. This executive signal also comprises the execution parameter of corresponding algorithm. Reconfigurable controller, according to the final election device of executive signal gating required memory, processing unit, starts the sub-controller of this algorithm after completing data stream gating. Computing array received is to the algorithm executive signal sent of reconfigurable controller, and starts according to execution parameter to perform computing operation. By operation result and complete signal and return to reconfigurable controller after computing completes.
The core that each algorithm sub-controller completes computing is reconfigureable computing array, and as shown in Figure 4, also namely all algorithm sub-controllers are all connected with the most basic computing array its structure according to respective algorithm requirements. The different computing arrays selected by algorithm sub-controller is also different, and such as FIR sub-controller needs to use the RPE1 ~ RPE4 comprising complex multiplication and complex addition; Fixed floating conversion sub-controller only needs to use RPE5; Comparatively complicated matrix inversion sub-controller then to be used RPE1 ~ RPE4 and comprise the RPE6 of floating-point division.
Algorithm sub-controller can feed back to principal controller by completing signal by reconfigurable controller after terminating computing, and result data also have corresponding feedback signal after having been carried by DMA. Principal controller receive these two complete feedback signal after namely current computing terminate, this restructural system can receive and configure next time afterwards, performs next task.
From describing above, the combination of independent subalgorithm can be got up by configuration information by the scheduling of this restructural system, completes combinatorial operation. Its process is as follows: be first the division of subtask, and the application that complete is divided into some the subtasks successively performed; Then generating corresponding configuration information according to each subtask leaves in instruction district, due to the source data of subtask (such as the N+1 time) rearward may come from before the result of task (the N time), intermediate result can be left in storage inside device by treating processes, just need to, from external input sources data, only need to the source address of the result storage address of N task and the N+1 time task be set to identical before the N+1 time computing like this; Finally, after all subtasks complete, result is exported in outside DDR by DMA.
Based on above-mentioned hardware implementing, the main function of this coprocessor is as follows:
1. computing function is configurable, and process counts/and parameter is configurable.
2. support master and slave mode operation regimes.
3. support the batch processing function of algorithm combination.
4. support table tennis stream treatment.
5. small point data are stored in on-chip SRAM and directly process; A little bigger logarithmic data is stored in DDR, supports segmentation reading process.
6. built-in DMA, number removed by support order, transposition, supports chain type and two dimension DMA.
Reconfigurable coprocessor of the present invention, in Radar Signal Processing, realizes there is following advantage relative to the DSP of current main flow realization and FPGA:
1) calculated performance is good; Compared to the system structure of DSP based on instruction stream, this design can reach higher efficiency based on the structure of configuration flow, after principal controller receives exterior arrangement, can again organize the interconnection mode between reconfigureable computing array according to configuration information. The scale being directed to computing array, have also been made optimization process to each subalgorithm supported in this system, reaches optimum performance.
2) area consumption is little; Completing same function, realize area based on the FPGA searching table and realize much bigger than what application specific integrated circuit adopted hardwire, in the chip design field that area requirements is very harsh, the existing way of coprocessor has very big area advantage.
Claims (10)
1. the coprocessor based on reconfigureable computing array, it is characterised in that comprising:
Principal controller, receives the control information that outside general procedure device sends, then resolves described control information, and send corresponding configuration-direct, and described configuration-direct comprises transmission parameter and algorithm parameter;
Reconfigurable controller, according to the algorithm parameter in described configuration-direct, sends configuration information, and described configuration information is for selecting and organizes the executive signal of the logic algorithm in arithmetic core unit and inner network gating signal;
Arithmetic core unit, receives described configuration information, completes according to configuration information to take advantage of again, is added with, real the fundamental operation such as takes advantage of;
DMA unit, receives the transmission parameter of described configuration-direct, carries out outside DDR and the carrying of the data between storage inside module, principal controller.
2. reconfigurable coprocessor according to claim 1, it is characterised in that described transmission parameter comprises transfer and counts, transfer start address, data transfer direction and data mode of transport; Described algorithm parameter comprises computing type and computing is counted.
3. reconfigurable coprocessor according to claim 1, it is characterised in that described arithmetic core unit comprises reconfigureable computing array.
4. reconfigurable coprocessor according to claim 3, it is characterized in that described reconfigureable computing array is made up of the computing array of coarsness, being integrated with six reconfigurable processing units, reconfigureable computing array can realize reconstruct between the reconstruct of reconfigurable processing unit inside and reconfigurable processing unit.
5. reconfigurable coprocessor according to claim 3, it is characterized in that described arithmetic core unit also comprises some multi-path choice devices and input-output register, described multi-path choice device, input-output register communicate to connect with reconfigureable computing array respectively.
6. reconfigurable coprocessor according to claim 1, it is characterised in that configuration information comprises computing type and computing data.
7. reconfigurable coprocessor according to claim 1, it is characterised in that also comprise AXI interface, described AXI interface is used for being connected principal controller with outside general procedure device.
8. reconfigurable coprocessor according to claim 1, it is characterised in that also comprise memory module, for receive arithmetic core unit, the data of principal controller and store.
9. reconfigurable coprocessor according to claim 1, it is characterised in that principal controller comprises
Device configuration register, for storing the mode of operation of reconfigurable processing core, has holotype, from pattern, debugging mode, interrupts pattern and query pattern;
Computing configuration register, for storing described algorithm parameter, comprises computing type, and computing is counted, digital data transmission start address;
Status register, for representing the state of reconfigurable coprocessor.
10. reconfigurable coprocessor according to claim 1, it is characterized in that reconfigurable controller comprises reconstituted state machine unit, heavy register unit and algorithm sub-controller, algorithm sub-controller comprises FFT controller, FIR controller, relevant control device, addition controller, multiplication controller, dot product controller, conjugation controller, transposition controller, Covariance Controller, division controller, plural number ask mould controller, surely floating change over controller and matrix inversion controller.
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| CN106484657A (en) * | 2016-11-18 | 2017-03-08 | 成都嘉纳海威科技有限责任公司 | A kind of reconfigurable signal processor ASIC framework and its reconstructing method |
| CN107657316A (en) * | 2016-08-12 | 2018-02-02 | 北京深鉴科技有限公司 | The cooperative system of general processor and neural network processor designs |
| CN107688469A (en) * | 2016-12-23 | 2018-02-13 | 北京国睿中数科技股份有限公司 | Take into account the Reconfigurable Computation device of universal command and special instruction |
| CN108228529A (en) * | 2017-09-28 | 2018-06-29 | 清华大学无锡应用技术研究院 | For the method for reconfigureable computing array and its system to be configured |
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| CN112732639A (en) * | 2021-04-01 | 2021-04-30 | 南京大学 | Coarse-grained dynamic reconfigurable processor and data processing method thereof |
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| CN114328311A (en) * | 2021-12-15 | 2022-04-12 | 珠海一微半导体股份有限公司 | Storage controller architecture, data processing circuit and data processing method |
| CN114548390A (en) * | 2022-02-25 | 2022-05-27 | 电子科技大学 | RISC-V and nerve morphology calculation-based heterogeneous architecture processing system |
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