CN105207957B - A kind of system based on network-on-chip multicore architecture - Google Patents
A kind of system based on network-on-chip multicore architecture Download PDFInfo
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- CN105207957B CN105207957B CN201510507293.7A CN201510507293A CN105207957B CN 105207957 B CN105207957 B CN 105207957B CN 201510507293 A CN201510507293 A CN 201510507293A CN 105207957 B CN105207957 B CN 105207957B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
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Abstract
The present invention relates to a kind of network-on-chip multi-core architectures, including network-on-chip multicore architecture ontology, network-on-chip multicore architecture ontology includes multiple computing units, router and network interface, multiple computing units, which are connected by router with network interface, realizes parallel data processing and data interaction, one of computing unit is as master control core node, remaining computing unit is as operation core node, master control core node is responsible for and the data exchange outside piece, operation core node transfers data to master control core node, is completed and the data exchange outside piece by master control core node；Memory space in multiple computing units uses unified addressing, and the core in each computing unit is made to be able to access that the memory space in other any computing units.Batch data transmits between the present invention can realize computing unit, moreover it is possible to realize that network interface carries data, to improve the resource utilization of network-on-chip, reduce computational efficiency and network-on-chip performance that power consumption improves multiple-core processor systems simultaneously.
Description
Technical field
The present invention relates to network-on-chip technical field, especially a kind of system based on network-on-chip multicore architecture.
Background technology
With the development of microelectronics computing technique, the integrated level of super large-scale integration is higher and higher, network-on-chip system
The drawbacks of (SOC) bus structures of uniting, is gradually exposed, and caused by physical connection and single clock the problems such as clock delay, restricts
The further development of SOC, then proposed in 1999 using Sweden's Royal Institute of Technology as the academic institution of representative novel
Communication architecture-NOC, this design are attached to communication network concept in IC design, and each computing unit module is
One routing node of network-on-chip.And in traditional SOC design, all it is to be connected modules using bus architecture
And use a unified clock.Although SOC this scheme or feasible in the case where integrated level is low, with integrated
The continuous improvement of degree, for SOC by serious clock delay and bias effect, this brings great challenge, on piece to designer
Network (NOC) then thoroughly solves the problems, such as this, and NOC systems use a kind of distributed network structure, when they are not unified
Clock, each computing unit are connected by router, they can respectively be completely independent work independently of each other.
The SOC communication efficiencies of conventional bus structures are relatively low, cannot really realize that multiprocessors parallel processing communication is appointed
Business so that conventional bus structures encounter the communication performance bottleneck that can not be overcome, and main performance is as follows：
(1) not expansibility：With technological development, the requirement that big data calculates so that press-on-a-chip device number will be more next
More, the traffic between processor also increases therewith, cause between SOC bus address resource and processor number not
Match, in addition the increase of limited address resource limitation processor number.
(2) it is unable to parallel communications：All it is to use bus structures in SOC, although bus structures are a kind of shared mutually connections
Structure, but when multiple processors are simultaneously emitted by request, bus will generate arbitration according to priority, this causes system cannot
Parallel communications, so as to cause system communication inefficiency.
(3) single clock stationary problem：SOC requires signal global synchronization under bus structures, with technology characteristics and frequency
Rate requirement is higher and higher, and interconnection delay makes clock problem of misalignment become uncontrollable under bus structures, and single clock synchronizes entirely
The work of chip becomes extremely difficult, therefore there is an urgent need to propose that completely new interconnection mechanism substitutes traditional bus mechanism.
As shown in Figure 1, common NOC multicore architectures include computing unit, memory is shared, more than two networks connect
Mouthful, router.The NOC multicore architectures have following features：
(1) NOC scalabilities are strong：Since NOC is based on computer network communication framework, resource node connected to the network does not have
It is restricted, in theory can be with infinite extension, this can not imagine in traditional bus architecture.
(2) NOC parallel communications：NOC efficiently solves the problems, such as multiple resource nodes while communicating that NOC is based on net
Network structure, the communication between each node have mulitpath, this feature can solve communication task and be unable to parallel processing,
Reliable parallel processing is realized, to adapt to the demand for development of multi core chip.
(3) NOC uses the communication mechanism of globally asynchronous locally synchronous, each resource node that can be operated in independent clock
Domain, but be different between resource node and asynchronous communication is then carried out by communication node, it brings to solving global synchronization
Problem.
(4) NOC is conducive to improve reusability, and the scalability and reusability of bus architecture are poor, and the computing capability of chip is drilled
When change, it is necessary to which the design for change with the demand of processing capacity, this is a great workload for developer；If
Using NOC by communication architecture independent design, the reusability of module is improved in this way, to shortening the development cycle of product, reduces product
Development cost is of great significance.
To sum up, NOC design method and designing technique, have better scalability, predictability, higher band
Width, the clock scheme of local synchronization Global Asynchronous, in terms of coping with physical limit also advantageously, therefore NOC technology quilts
Industry is considered to solve the strategic technology of communication issue in current and future nanometer-grade IC design for a period of time.
Currently, the network structure for the multi-core processor having been carried out mainly has mesh structures, torus structures, flat tree knot
Structure, loop configuration etc., more research institutions are mostly to use 2d mesh structures at present, and 2d mesh structures have significant special
Point：The coding of routing is simple, simple for structure.
Invention content
The technical problem to be solved by the present invention is to overcome the existing defects, and data interaction can efficiently be carried out by providing one kind
The system based on network-on-chip multicore architecture.
In order to solve the above technical problem, the present invention provides the following technical solutions：
A kind of system based on network-on-chip multicore architecture of the present invention, including network-on-chip multicore architecture ontology, piece online
Network multicore architecture ontology includes multiple computing units, router and network interface, and multiple computing units pass through router and network
Parallel data processing and data interaction are realized in interface connection, and one of computing unit is as master control core node, remaining calculating
Unit as operation core node, be responsible for transferring data to master control with the data exchange outside piece, operation core node by master control core node
Core node is completed and the data exchange outside piece by master control core node；Memory space in multiple computing units uses unified addressing,
The core in each computing unit is set to be able to access that the memory space in other any computing units.
Further, clock, reset and the dormant state of master control core node control operation core node, to without using operation
Core node, which is taken, closes clock and reset.
Further, master control core node includes the peripheral equipment being made of UART, High Speed Serial and external memory interface
And core, external memory interface include 64 internal bus interfaces and 32 external bus interfaces, core is using VLIW structures
The digital signal processor of the embedded system application of frame.
Further, data interaction, master control core node and fortune are carried out using packet switching protocol between multiple computing units
Core node is calculated using ahb bus agreement and the outer data interaction of piece, two kinds of agreements are exchanged with each other by network interface.
Further, network-on-chip multi-core architecture ontology uses the 2D-Mesh NOC frameworks of 3x3.
Beneficial effects of the present invention：
1, batch data transmits between the present invention can realize computing unit, moreover it is possible to realize that network interface carries data.
2, the present invention improves the resource utilization of network-on-chip, reduces the calculating that power consumption improves multiple-core processor systems simultaneously
Efficiency and network-on-chip performance.
Description of the drawings
Fig. 1 is the overall structure figure of common NOC multicore architectures；
Fig. 2 is the overall structure figure of the system based on NOC multicore architectures of the present invention；
Fig. 3 is the structure diagram of master control core node in the present invention；
Fig. 4 is the structure diagram of operation core node in the present invention；
Fig. 5 is the structure diagram of clock control system in the present invention.
Specific implementation mode
Embodiment cited by the present invention, is merely used to help understand the present invention, should not be construed as protecting model to the present invention
The restriction enclosed for those skilled in the art without departing from the inventive concept of the premise, can also be right
The present invention makes improvements and modifications, these improvement and modification are also fallen into the range of the claims in the present invention protection.
With RTL multi-core network design verification test platforms, the overall structure of the system of the invention based on NOC multicore architectures
Such as Fig. 2, using the 2D-Mesh NOC frameworks of 3x3, R represents router in figure, and what is connected on the router R of the upper left corner is master control core
Node, master control core node are a computing unit, and that connected on remaining multiple router R is multiple operation core nodes, Duo Geyun
Calculation core node is multiple computing units, and master control core node has been connected with operation core node with router R by network interface NI
Come.
Data interaction between realizing each computing unit using packet switching protocol based on the system of NOC multi-core architectures, it is main
Core node and operation core node are controlled using ahb bus agreement and the outer data interaction of piece, two kinds of agreements are mutual by network interface NI
It exchanges.
Memory space in multiple computing units uses unified addressing, and any computing unit can be with the packet header of configuration data packet
Destination address makes the core in each computing unit be able to access that the memory space in other any computing units, specific to address
Such as the following table 1, it is main use space that the address space of NOC multicore architectures 4G, which is divided into 6 sections, every section of 256Mb, therein section 7, from
70000000 start.
Table 1 mainly uses the addressing of memory space
In order to enable data to transmit in network-on-chip, need to address the router R of whole network, with level
Direction is that X-axis vertical direction is Y-axis, and to each router R addressings such as Fig. 2, the addresses master control core node corresponding router R are
(00,00), therefore, the first row are followed successively by (00,00) ... ..., and (11,00), the second row is followed successively by (00,01) ... ..., (11,
01), the third line is followed successively by (00,10) ... ..., and (11,10), fourth line is followed successively by (00,11) ... ..., (11,11).
As shown in figure 3, being connected on master control core node by UART, High Speed Serial GPIO and external memory interface EMI groups
At peripheral equipment and core, master control core node using ahb bus agreement be responsible for piece outside data exchange, master control core node conduct
Control module, data to be treated outside receiving sheet pass through DSP core work in packet switching protocol distribution and management operation core node
Make.
Its external memory interface EMI includes 64 internal bus interfaces, and 32 external bus interfaces are directly supported
16 or 32 SRAM need software to assist the support of 8 SRAM；It supports the data/address bus of multiplexing, also supports single
Only data and address bus provides the access parameter of flexible programming, provides the read and write access of different components different settings,
Programmable chip selection signal line supports the arbitration of external bus main device, and external bus frequency scalable can be by internal total
The frequency dividing of line 2,3 or 4 obtains, and supports highest 500MHz, supports reading and writing data caching；Its core is that a embedded system is answered
Low-power consumption, high speed, high-performance digital signal processor DSP, the processor use VLIW frameworks, maximum to support single clock
The transmitted in parallel of 5 instructions of period supports the decoding of 16/32 bit instruction, supports the operation of monocycle 32MAC, abundant DSP is supported to seek
Location pattern supports SIMD operation, supports basic floating-point operation, for work dominant frequency up to 800MHz, multiply-add operation ability is reachable
25GMACS is suitable for communication and the application of image procossing.
As shown in figure 4, operation core node will carry out data exchange outside with piece, data is needed to pass by ahb bus agreement
It is sent to network interface NI, master control core node is transmitted to by packet switching protocol, completes to hand over the data outside piece by master control core node
It changes.
The clock of master control core node control operation core node, reset and suspend mode are used in system based on NOC multicore architectures
State, to without using operation core node can take close clock and reset to play reduce power consumption purpose.
Electrification reset sequence in system based on NOC multicore architectures is as follows：When electrification reset, whole system, which is in, to be resetted
State, about 500 μ s of resetting time.External equipment, bus end first reset, and followed by router R, network interface NI terminate multiple
Position, followed by operation core (DSP core in operation core node) terminates to reset, and is finally the master control core (DSP in master control core node
Core) terminate to reset.Master control core in multicore architecture starts from external FLASH, and operation core starts from local IRAM.Reset terminates
Afterwards, master control core first from external FLASH start, startup program the program in external FLASH move in respectively master control core IRAM and
In the IRAM of operation core.When master control core removes program in the IRAM toward operation core, signal is controlled by the sleeping/waking of core
Runstall allows operation core, and program restarts operation core after having removed in a dormant state.
Each operation core node will enter suspend mode when not working, and can be controlled by runstall by master control core node
Operation core processed enters suspend mode；Or after the complete program of operation core node processing, in program termination plus dormancy instruction, by software side
Formula enters suspend mode.Operation core in suspend mode is waken up by master control core, and master control core node is interrupted by being sent to the operation core in suspend mode
Packet, triggering, which is interrupted, wakes up the operation core.
As shown in figure 5, clock control system mainly completes the frequency dividing selection of the switch and AHB apb clocks of each clock, branch
It holds and the clock of ccik1-cclk8 is supported individually to turn off, support 2/4 frequency dividing of hclk clocks, support 2/4 frequency dividing of pclk clocks.
In conclusion the system based on NOC multicore architectures of the present invention can not only realize batch data between computing unit
Transmission, moreover it is possible to realize that network interface carries data；The present invention improves the resource utilization of network-on-chip, reduces power consumption and improves simultaneously
The computational efficiency and network-on-chip performance of multiple-core processor systems.
Claims (4)
1. a kind of system based on network-on-chip multicore architecture, including network-on-chip multicore architecture ontology, network-on-chip multinuclear frame
Structure ontology includes multiple computing units, router and network interface, it is characterised in that：The multiple computing unit passes through router
Connected with network interface and realize parallel data processing and data interaction, one of computing unit as master control core node, remaining
Computing unit as operation core node, master control core node be responsible for the data exchange outside piece, operation core node is by data transmission
To master control core node, completed and the data exchange outside piece by master control core node；Memory space in the multiple computing unit is adopted
With unified addressing, the core node in each computing unit is made to be able to access that the memory space in other any computing units, it is described
Clock, reset and the dormant state of master control core node control operation core node, to without using operation core node take closing when
Clock and reset.
2. the system according to claim 1 based on network-on-chip multicore architecture, it is characterised in that：The master control core node
Include the peripheral equipment and core being made of UART, High Speed Serial and external memory interface, external memory interface includes 64
Internal bus interface and 32 external bus interfaces, core be using VLIW frameworks embedded system apply number
Signal processor.
3. the system according to claim 1 based on network-on-chip multicore architecture, it is characterised in that：The multiple calculating is single
Data interaction is carried out using packet switching protocol between member, master control core node and operation core node use ahb bus agreement and piece
Outer data interaction, two kinds of agreements are exchanged with each other by network interface.
4. the system according to claim 1 based on network-on-chip multicore architecture, it is characterised in that：The network-on-chip is more
Core framework ontology uses the 2D-Mesh NOC frameworks of 3x3.
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| US10353767B2 (en) * | 2017-09-14 | 2019-07-16 | Bae Systems Controls Inc. | Use of multicore processor to mitigate common mode computing faults |
| CN108038283B (en) * | 2017-11-30 | 2021-06-08 | 北京时代民芯科技有限公司 | Virtual clock synchronization's high-efficient high coverage rate SoC verifies platform |
| CN110297802A (en) * | 2019-06-09 | 2019-10-01 | 苏州长江睿芯电子科技有限公司 | Interconnection architecture between a kind of new types of processors |
| CN111427835B (en) * | 2020-03-13 | 2023-01-06 | 苏州浪潮智能科技有限公司 | Network-on-chip design method and device based on hybrid routing algorithm |
| CN113407479A (en) * | 2020-03-16 | 2021-09-17 | 北京灵汐科技有限公司 | Many-core architecture embedded with FPGA and data processing method thereof |
| CN112631982A (en) * | 2020-12-25 | 2021-04-09 | 清华大学 | Data exchange method and device based on many-core architecture |
| CN113923157A (en) * | 2021-10-14 | 2022-01-11 | 芯盟科技有限公司 | Multi-core system and processing method based on network on chip |
| CN114297097B (en) * | 2021-12-01 | 2023-04-14 | 北京时代民芯科技有限公司 | Many cores can define distributed shared storage structure |
| CN115665041B (en) * | 2022-11-18 | 2023-03-28 | 北京红山微电子技术有限公司 | Network-on-chip structure, data transmission method, electronic device, and storage medium |
| CN116306407B (en) * | 2023-05-19 | 2023-08-18 | 太初(无锡)电子科技有限公司 | Verification method, device, equipment and storage medium of Network On Chip (NOC) |
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