CN111427835B

CN111427835B - Network-on-chip design method and device based on hybrid routing algorithm

Info

Publication number: CN111427835B
Application number: CN202010173983.4A
Authority: CN
Inventors: 李拓
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2020-03-13
Filing date: 2020-03-13
Publication date: 2023-01-06
Anticipated expiration: 2040-03-13
Also published as: CN111427835A

Abstract

The invention provides a method and a device for designing a network on chip based on a hybrid routing algorithm, wherein the method comprises the following steps: dividing the nodes into controller nodes, data processing nodes, data exchange nodes and equipment nodes according to the functional characteristics of the nodes in the network on chip; arranging the nodes from the central position of the on-chip network to the periphery layer by layer according to the sequence of the controller nodes, the data processing nodes, the data exchange nodes and the equipment nodes; the controller node and the data processing node are used as one group, the data exchange node and the equipment node are used as another group, and adaptive routing is adopted among each group, and XY routing or YX routing is adopted among groups. Based on the data transmission characteristics and arrangement modes of different types of nodes, the invention realizes the data transmission among different nodes by using different routing algorithms, thereby improving the performance of the network on chip and the whole chip.

Description

Network-on-chip design method and device based on hybrid routing algorithm

Technical Field

The present invention relates to the field of computers, and more particularly, to a method and an apparatus for designing a network on chip based on a hybrid routing algorithm.

Background

With the development of chip technology and the continuous improvement of complexity of application scenes, for a complex function chip needing to deal with the complex scenes, the realization mode of a single framework causes too high dependence degree between the complexity and different functions, thereby greatly prolonging the research and development period and hardly meeting the application requirements. This type of chip (e.g., a cell phone chip, a general purpose processor chip, an AI chip, etc.) is beginning to widely adopt an architecture that integrates multiple cores with different functions — different core modules are dedicated to implementing and optimizing specific functions, and then communicate and cooperate in a bus manner to complete the complete chip function. The method has the advantages that firstly, each core module can be developed in parallel, and the development period is shortened; and secondly, the core module with single function can realize transplantation and reuse in multiple chips, and reduce the research and development investment of new chips. At present, most processors are designed and implemented in a modular/modularized manner.

The chip bus is an internal structure and is a common channel for transmitting information among modules and modules. Similar to a bus in a computer system, a bus inside a chip also needs to implement a set of unified bus protocol and architecture, so that each module and module in the chip can communicate with any other module and module through the bus, thereby cooperatively completing the complete functions of the chip. With the increasing complexity of chip structures, the research of networks on chip (NoC) is continuously advanced and practiced, and various network structures are proposed, and in general, most networks on chip still adopt a two-dimensional Mesh (2D Mesh) manner.

Each node of a two-dimensional grid (Mesh) network is connected with nodes in four directions of east, west, south and north of the two-dimensional grid network to form a grid structure, communication links between every two nodes can be multiple, and the most idle data path at present can be found through an efficient routing algorithm for communication in actual communication, so that the communication efficiency is improved, meanwhile, the expandability of the structure is high, the network of M x N nodes can be conveniently constructed, the shape of the network is very regular, and the realization of a hardware layout is facilitated, as shown in fig. 1.

Traditionally, in a 2D Mesh network, according to different actual needs, there are multiple different routing algorithms for module/module communication inside a chip, such as various shortest path routing algorithms focusing on data transmission speed, various load balancing algorithms focusing on avoiding data congestion, and deadlock-free algorithms focusing on avoiding deadlock. The most common of them are various algorithms with emphasis optimization based on basic XY algorithm. The basic XY algorithm assigns serial numbers to all nodes on the 2D Mesh according to two directions of an X axis (horizontal direction) and a Y axis (vertical direction), each node has a unique coordinate, and the coordinates are continuous. During data transmission, the data is transmitted along the X axis, reaches the same X axis coordinate of the destination node, and then is transmitted along the Y axis until the destination node is reached.

The basic XY algorithm has the advantages of simple logic, high transmission efficiency under ideal conditions, no deadlock, easiness in implementation and the like. But at the same time, the disadvantage is also obvious, and the algorithm is a general algorithm, is lack of optimization for a specific transmission path, and is easy to generate data congestion among nodes in a large amount of data exchange sets in practical application. Therefore, in an actual chip, optimization is often performed by adding a self-adaptive adjusting path or adding a priority to optimize a specific path according to application requirements.

To improve efficiency, many networks on chip have begun to employ various improved multi-path adaptive routing algorithms. That is, the selectable paths between two nodes are multiple, and according to the historical state or the current state of the network, which path should be selected is judged. In such a way, efficient data transmission may be locally formed, but if the scale of the network on chip is too large, on one hand, monitoring and collecting the state of the network on chip may bring large resource overhead, which affects the efficiency; on the other hand, a plurality of nodes make judgment according to the same state information, tend to the same path, and are likely to be congested.

With the development of application fields (such as scenarios like AI), in different application fields, the network on chip has more common characteristics and optimizable directions, and more importantly, each node in the network on chip is more and more specialized in function. For example, a conventional network on chip with multiple processing cores often has a symmetrical relationship, that is, different nodes are likely to have the same design and are only used for processing similar tasks in parallel, so as to achieve overall performance acceleration. And at present, more network-on-chip nodes are designed in a customized manner aiming at a certain function or a certain class of functions, so that the efficiency is improved, and the network-on-chip nodes are specially used for processing the functions. Meanwhile, in order to improve efficiency, a plurality of high-speed device interfaces are also directly hung on the network on chip as nodes (instead of the traditional method that all devices are hung on one control node for management). These changes, on the one hand, result in an increase in the size of the network on chip, and, on the other hand, result in different characteristics between different nodes for data transmission of the network on chip.

In the prior art, no matter a basic XY routing algorithm or a routing algorithm subjected to specific optimization is adopted, the whole network on chip is regarded as a unified whole, and the optimization under the thought is usually incapable of improving the efficiency of the whole when the large-scale asymmetric network on chip is subjected to non-uniform data transmission.

Disclosure of Invention

In view of this, an object of the embodiments of the present invention is to provide a method and an apparatus for designing a network on chip based on a hybrid routing algorithm, so as to rearrange network on chip nodes according to different data transmission distributions of the network on chip, directionally optimize data transmission, and improve overall performance of the network on chip.

Based on the above object, an aspect of the embodiments of the present invention provides a method for designing a network on chip based on a hybrid routing algorithm, including:

dividing the nodes into controller nodes, data processing nodes, data exchange nodes and equipment nodes according to the functional characteristics of the nodes in the network on chip;

arranging the nodes from the central position of the on-chip network to the periphery layer by layer according to the sequence of the controller nodes, the data processing nodes, the data exchange nodes and the equipment nodes;

the controller node and the data processing node are taken as one group, the data exchange node and the equipment node are taken as another group, and adaptive routing is adopted among each group, XY routing or YX routing is adopted among groups.

In some embodiments, the controller node is configured as a control core of the entire network-on-chip system, the data processing node is configured as a data processing module with a customized function in the system, and the data switching node is configured to implement a data switching function between nodes.

In some embodiments, dividing the nodes into a controller node, a data processing node, a data switching node, and a device node according to functional characteristics of the nodes in the network on chip comprises:

and configuring a register of a network port of a node in the network on chip to distinguish the type of the node connected with the network port.

In some embodiments, the registers of the network ports are configured 00 for a controller node, 01 for a data processing node, 10 for a data switching node, and 11 for a device node.

In some embodiments, the number of types of nodes in the network on chip is different from each other.

Another aspect of the embodiments of the present invention provides a device for designing a network on chip based on a hybrid routing algorithm, including:

at least one processor; and

a memory storing program code executable by the processor, the program code implementing the following steps when executed by the processor:

In some embodiments, the register configuration of the network port is represented by 00 as a controller node, 01 as a data processing node, 10 as a data switching node, and 11 as a device node.

The invention has the following beneficial technical effects: according to the method and the device for designing the network on chip based on the hybrid routing algorithm, provided by the embodiment of the invention, the network on chip nodes are divided into four different types according to the characteristics of the network on chip, the arrangement mode of the different nodes on the network on chip is optimized according to the types, and the data transmission between the different nodes is realized by using different routing algorithms based on the data transmission characteristics and the arrangement mode of the different nodes, so that the performance of the network on chip and the whole chip is improved by improving the high-priority data transmission efficiency and reducing the data congestion mode of the whole system.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

FIG. 1 is a schematic diagram of a network-on-chip in the form of a two-dimensional grid in the prior art;

FIG. 2 is a schematic diagram of a hybrid routing algorithm based network on chip design method according to the present invention;

fig. 3 is a schematic diagram of a hardware structure of a network-on-chip design device based on a hybrid routing algorithm according to the present invention.

Detailed Description

Embodiments of the present invention are described below. However, it is to be understood that the disclosed embodiments are merely examples and that other embodiments may take various and alternative forms. The figures are not necessarily to scale; certain features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. As one of ordinary skill in the art will appreciate, various features illustrated and described with reference to any one of the figures may be combined with features illustrated in one or more other figures to produce embodiments that are not explicitly illustrated or described. The combination of features shown provides a representative embodiment for a typical application. However, various combinations and modifications of the features consistent with the teachings of the present invention may be desired for certain specific applications or implementations.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

Based on the above object, an embodiment of the present invention provides a method for designing a network on chip based on a hybrid routing algorithm, as shown in fig. 2, including:

step S201: dividing the nodes into controller nodes, data processing nodes, data exchange nodes and equipment nodes according to the functional characteristics of the nodes in the network on chip;

step S202: arranging the nodes from the central position of the on-chip network to the periphery layer by layer according to the sequence of the controller nodes, the data processing nodes, the data exchange nodes and the equipment nodes;

step S203: the controller node and the data processing node are taken as one group, the data exchange node and the equipment node are taken as another group, and adaptive routing is adopted among each group, XY routing or YX routing is adopted among groups.

In some embodiments, the controller node is configured as a control core of the entire network-on-chip system, the data processing node is configured as a data processing module with a customization function in the system, and the data switching node is configured to implement a data switching function between nodes.

In some embodiments, the dividing the nodes into a controller node, a data processing node, a data switching node, and a device node according to functional characteristics of the nodes in the network on chip comprises: and configuring a register of a network port of a node in the network on chip to distinguish the type of the node connected with the network port.

In some embodiments, the number of types of nodes in the network on chip may be different.

In some embodiments, nodes are classified into four types according to their functional characteristics in the network on chip: a controller node, a data processing node, a data switching node and an equipment node. The controller node refers to a control core of the whole system, and has more data exchange with other nodes, and the data exchange priority is higher; data processing nodes refer to some customized and relatively single-function data processing modules in the system, such as convolution operation units in an AI chip, and the data exchange objects of the nodes are generally relatively fixed, most data transmission occurs between the nodes and a controller node, and a small amount of data transmission may occur between the nodes and the data exchange node; as the complexity of the system on chip increases, in order to reduce the load of the control core, many underlying data exchange functions (such as between devices, between data processing nodes and devices, etc.) are stripped from the control core to form a separate data control module (such as a DMA module), and data transmission of these data exchange nodes mostly occurs between devices; the device nodes, if there are data exchange nodes in the system, most of their data transmission only takes place between the data exchange nodes, and few device protocols can support direct data transmission between devices.

In some embodiments, in practical applications, the network ports of the nodes in the network on chip adopt a configurable design, and the type of the connected nodes is distinguished through the configuration of the registers with 2-bit width. For example, "00" represents a controller node, "01" represents a data processing node, "10" represents a data switching node, and "11" represents a device node. Besides the node type of each node is determined through register configuration, each node also needs to store a group of information for recording the types of all nodes in the whole network on chip.

In some embodiments, the number of the four types of nodes in the chip is different according to the actual chip (in an extreme case, the number of other nodes except the controller node may be 0), so that in the network on chip with different sizes, the arrangement of the different types of nodes does not have a fixed form. But may be arranged according to a uniform rule according to the characteristics of each type of node.

In some embodiments, the controller cores are arranged from a central location throughout the network-on-chip (e.g., in an N x N network-on-chip, starting with (N/2, N/2)), and, if there are multiple controller nodes, are arranged progressively to the periphery; and then arranging the nodes to the periphery layer by layer according to the sequence of the data processing nodes, the data exchange nodes and the equipment nodes. The final effect is that the appliance node is outermost, the data switching node is as close as possible to the appliance node, and the data processing node is as close as possible to the controller node. The benefit of this arrangement is that most of the data transmission occurs between nodes that are relatively close in distance.

In some embodiments, when data transmission occurs, the transmission routing mode of the data is determined according to the type of the node sending the data and the type of the destination node to be reached. According to the arrangement in the above embodiment, the controller node and the data processing node may be seen as one group which is closer, and the data switching node and the device node as another group. The relationship between node type and routing mode is shown in table 1.

TABLE 1

In some embodiments, as shown in table 1, different routing modes are defined in the present invention: adaptive routing, XY routing, and YX routing. The XY routing algorithm and the YX routing algorithm are basic routing algorithms, wherein the YX routing algorithm is similar to the XY routing algorithm, and only the transmission of the X axis is executed first, and the transmission of the Y axis is executed first. The two routing algorithms are applied between two types of nodes, and are distinguished by the two types of algorithms in order to alleviate data congestion as much as possible when data transmission of a certain node is high (for example, a controller node sends broadcast collection data to all nodes). And in the interior of two groups of type nodes, a self-adaptive routing algorithm is adopted. Different from the multi-path self-adaptive routing algorithm applied to the whole network on chip in the prior art, the self-adaptive routing algorithm only needs to monitor local network on chip information, namely only monitors the path information of the nodes in each group, so that the consumed resources are greatly reduced, and the number of the nodes initiating data transmission and selecting paths is reduced at the same time.

In some embodiments, obviously, although the adaptive routing algorithm is adopted for the type nodes in the groups of the two groups, the two types of nodes are different, and the greatest difference is that the monitoring state and the range of the selected path are different. In practical design, this point needs to be considered, and the design of the adaptive routing algorithm should adopt a configurable mode and be flexible to use.

This approach has a side effect that the same adaptive routing algorithm is used, but the data transmission efficiency in the group of the data switching node and the device node is lower than that in another group because the nodes are arranged at the periphery, and the adaptive routing is also performed at the peripheral node, and the actual transmission efficiency may be lower than that in the conventional XY algorithm. However, considering that the transmission of the data has a lower priority, even if the risk of efficiency reduction occurs, the overall performance will not be affected because the occupation of the core node data transmission path which may occur is avoided.

Where technically feasible, the technical features listed above for different embodiments may be combined with each other or changed, added, omitted, etc. to form further embodiments within the scope of the invention.

It can be seen from the foregoing embodiments that, in the method for designing a network on chip based on a hybrid routing algorithm provided in the embodiments of the present invention, the characteristics of the network on chip are considered, the network on chip nodes are divided into four different types, and the arrangement of the different nodes on the network on chip is optimized according to the types. Based on the data transmission characteristics and arrangement modes of different types of nodes, different routing algorithms are used for realizing data transmission among different nodes, so that the performance of the network on chip and the performance of the whole chip are improved by improving the high-priority data transmission efficiency and reducing the data congestion of the whole system.

In view of the above, another aspect of the embodiments of the present invention provides a device for designing a network on chip based on a hybrid routing algorithm, including:

at least one processor; and

the controller node and the data processing node are used as one group, the data exchange node and the equipment node are used as another group, and adaptive routing is adopted among each group, and XY routing or YX routing is adopted among groups.

Fig. 3 is a schematic diagram of a hardware structure of an embodiment of the device for designing a network on chip based on a hybrid routing algorithm according to the present invention.

Taking the computer apparatus shown in fig. 3 as an example, the computer apparatus includes a processor 301 and a memory 302, and may further include: an input device 303 and an output device 304.

The processor 301, the memory 302, the input device 303 and the output device 304 may be connected by a bus or other means, and fig. 3 illustrates the connection by a bus as an example.

The memory 302 is used as a non-volatile computer-readable storage medium, and can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the hybrid routing algorithm-based network on chip design method in the embodiments of the present application. The processor 301 executes various functional applications of the server and data processing by running nonvolatile software programs, instructions and modules stored in the memory 302, that is, implements the hybrid routing algorithm-based network-on-chip design method of the above-described method embodiment.

The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to a network-on-chip design method based on a hybrid routing algorithm, and the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 may optionally include memory located remotely from processor 301, which may be connected to local modules over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The input means 303 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the computer device based on the hybrid routing algorithm network-on-chip design method. The output means 304 may comprise a display device such as a display screen.

Program instructions/modules corresponding to the one or more hybrid routing algorithm-based network-on-chip design methods are stored in the memory 302, and when executed by the processor 301, perform the hybrid routing algorithm-based network-on-chip design method in any of the above-described method embodiments.

Any embodiment of the computer device executing the method for designing a network on chip based on a hybrid routing algorithm may achieve the same or similar effects as any corresponding embodiment of the method.

Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes in the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a Random Access Memory (RAM).

In addition, the apparatuses, devices and the like disclosed in the embodiments of the present invention may be various electronic terminal devices, such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer (PAD), a smart television and the like, or may be a large terminal device, such as a server and the like, and therefore the scope of protection disclosed in the embodiments of the present invention should not be limited to a specific type of apparatus, device. The client disclosed in the embodiment of the present invention may be applied to any one of the above electronic terminal devices in the form of electronic hardware, computer software, or a combination of both.

Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the functions defined above in the methods disclosed in the embodiments of the present invention.

Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.

Further, it should be appreciated that the computer-readable storage media (e.g., memories) described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions described herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the above embodiments of the present invention are merely for description, and do not represent the advantages or disadvantages of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disk, or the like.

The above-described embodiments are possible examples of implementations and are presented merely for a clear understanding of the principles of the invention. Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A network-on-chip design method based on a hybrid routing algorithm is characterized by comprising the following steps:

the controller node and the data processing node are used as one group, the data exchange node and the equipment node are used as another group, adaptive routing is adopted between the nodes in each group, and XY routing or YX routing is adopted between the nodes in each group and the nodes outside the group;

XY routing is adopted between the controller node and the nodes outside the group, and YX routing is adopted between the data processing node and the nodes outside the group.

2. The method according to claim 1, wherein the controller node is configured as a control core of the entire network-on-chip system, the data processing node is configured as a data processing module with a customized function in the system, and the data switching node is configured to implement a data switching function between nodes.

3. The method of claim 1, wherein dividing the nodes into controller nodes, data processing nodes, data switching nodes, and device nodes based on functional characteristics of the nodes in the network on chip comprises:

4. A method according to claim 3, characterized in that the registers of the network ports are configured 00 for a controller node, 01 for a data processing node, 10 for a data switching node and 11 for a device node.

5. The method according to claim 1, wherein the number of nodes of each type in the network on chip is different from each other.

6. A network-on-chip design device based on a hybrid routing algorithm is characterized by comprising:

at least one processor; and

a memory storing processor executable program code which when executed by the processor performs the steps of:

7. The apparatus according to claim 6, wherein the controller node is configured as a control core of the entire network-on-chip system, the data processing node is configured as a data processing module with a customized function in the system, and the data switching node is configured to implement a data switching function between nodes.

8. The apparatus of claim 6, wherein the dividing of the nodes into controller nodes, data processing nodes, data switching nodes, and device nodes according to the functional characteristics of the nodes in the network on chip comprises:

9. The apparatus according to claim 8, wherein the register configuration of the network port is represented by 00 as a controller node, 01 as a data processing node, 10 as a data switching node, and 11 as a device node.

10. The apparatus of claim 6, wherein the number of types of nodes in the network on chip is different from each other.