CN111177066A - Method, device and medium for improving efficiency of accessing off-chip memory - Google Patents
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Abstract
The invention discloses a method, equipment and a storage medium for improving the efficiency of accessing an off-chip memory, wherein the method comprises the following steps: configuring a corresponding cache and an off-chip memory for each single-core processor in a multi-core processor; setting corresponding cross caches between every two caches; responding to the received processing task, distributing the task to a corresponding single-core processor, and distributing the data of the task in the single-core processor to an off-chip memory corresponding to the single-core processor; and distributing shared information and/or interactive data among tasks of different single-core processors to corresponding cross caches. The method, the equipment and the medium for improving the efficiency of accessing the off-chip memory improve the communication efficiency through cross cache, and improve the efficiency of accessing the off-chip memory by the multi-core processor by setting the corresponding off-chip memory for each single-core processor.
Description
Technical Field
The present invention relates to the field of multi-core processors, and more particularly, to a method, computer device, and readable medium for improving efficiency of accessing an off-chip memory.
Background
The memory wall problem, i.e. the clock frequency and performance of the processor core, is growing at an extremely fast rate, but the access speed (DRAM) of the main memory is growing much slower, and the phenomena of the mismatch between the computing power, the memory capacity and the I/O speed are becoming more and more. Current computer architectures employ large amounts of on-chip RAM (random access memory) to alleviate the memory wall problem.
In contemporary microprocessors, a large amount of memory latency has been avoided by using on-chip memory, and many advanced techniques also help to eliminate or hide a small portion of the memory latency. The on-chip memory technology proposes that the processor and the memory are arranged on the same chip, so that the memory access delay is greatly reduced, and the memory bandwidth is increased by more than 50-100 times. However, in the case of the conventional logic process, the storage density of the DRAM unit can only reach 5-25% of the optimized DRAM process, which results in a large occupation of chip area. And the current off-chip memory access communication cost is high and the speed is low, so that the memory system becomes a main problem of system performance bottleneck.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method, a computer device, and a computer readable storage medium for improving efficiency of accessing an off-chip memory, which improve communication efficiency by cross-caching, and improve efficiency of accessing the off-chip memory by a multi-core processor by setting a corresponding off-chip memory for each single-core processor.
In view of the above, an aspect of the embodiments of the present invention provides a method for improving efficiency of accessing an off-chip memory, including the following steps: configuring a corresponding cache and an off-chip memory for each single-core processor in a multi-core processor; setting corresponding cross caches between every two caches; responding to the received processing task, distributing the task to a corresponding single-core processor, and distributing the data of the task in the single-core processor to an off-chip memory corresponding to the single-core processor; and distributing shared information and/or interactive data among tasks of different single-core processors to corresponding cross caches.
In some embodiments, configuring each of the multi-core processors with the corresponding cache and off-chip memory comprises: configuring an off-chip memory managed by the single-core processor for each single-core processor, and setting a cache between the single-core processor and the off-chip memory.
In some embodiments, the setting of the corresponding cross-cache between each two caches includes: sequentially judging whether cross caches exist between the two caches; and creating a cross-cache between the two caches in response to there not being a cross-cache between the two caches.
In some embodiments, the allocating data of the tasks in the single-core processor to the off-chip memories corresponding to the single-core processor comprises: and uniformly addressing the off-chip memory, and distributing the tasks to corresponding storage addresses according to variable types.
In some embodiments, the allocating shared information and/or interaction data between tasks of different single-core processors to corresponding cross-caches includes: distributing the shared information and/or the interactive data to the corresponding cache preset addresses based on the interactive objects; and loading the shared information and/or interaction data into the cross-cache in response to the task execution.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: configuring a corresponding cache and an off-chip memory for each single-core processor in a multi-core processor; setting corresponding cross caches between every two caches; responding to the received processing task, distributing the task to a corresponding single-core processor, and distributing the data of the task in the single-core processor to an off-chip memory corresponding to the single-core processor; and distributing shared information and/or interactive data among tasks of different single-core processors to corresponding cross caches.
In some embodiments, configuring each of the multi-core processors with the corresponding cache and off-chip memory comprises: configuring an off-chip memory managed by the single-core processor for each single-core processor, and setting a cache between the single-core processor and the off-chip memory.
In some embodiments, the setting of the corresponding cross-cache between each two caches includes: sequentially judging whether cross caches exist between the two caches; and creating a cross-cache between the two caches in response to there not being a cross-cache between the two caches.
In some embodiments, the allocating data of the tasks in the single-core processor to the off-chip memories corresponding to the single-core processor comprises: and uniformly addressing the off-chip memory, and distributing the tasks to corresponding storage addresses according to variable types.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: the communication efficiency is improved through the cross cache, and the efficiency of the multi-core processor for accessing the off-chip memory is improved through setting the corresponding off-chip memory for each single-core processor.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of an embodiment of a method for improving efficiency of accessing an off-chip memory according to the present invention;
FIG. 2 is a system diagram illustrating an embodiment of a method for improving efficiency of accessing an off-chip memory according to the present invention;
fig. 3 is a schematic hardware structure diagram of an embodiment of the method for improving efficiency of accessing an off-chip memory according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the above objects, a first aspect of embodiments of the present invention proposes an embodiment of a method for improving efficiency of accessing an off-chip memory. FIG. 1 is a schematic diagram illustrating an embodiment of a method for improving efficiency of accessing an off-chip memory provided by the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
s1, configuring corresponding cache and off-chip memory for each single-core processor in the multi-core processor;
s2, setting corresponding cross buffers between every two buffers;
s3, responding to the received processing task, distributing the task to the corresponding single-core processor, and distributing the data of the task in the single-core processor to the off-chip memory corresponding to the single-core processor; and
and S4, distributing the shared information and/or the interactive data among the tasks of different single-core processors to the corresponding cross caches.
And configuring a corresponding cache and an off-chip memory for each single-core processor in the multi-core processor. In some embodiments, configuring each of the multi-core processors with the corresponding cache and off-chip memory comprises: configuring an off-chip memory managed by the single-core processor for each single-core processor, and setting a cache between the single-core processor and the off-chip memory.
And a corresponding cross cache is arranged between every two caches. In some embodiments, the setting of the corresponding cross-cache between each two caches includes: sequentially judging whether cross caches exist between the two caches; and creating a cross-cache between the two caches in response to there not being a cross-cache between the two caches.
Fig. 2 is a system configuration diagram illustrating an embodiment of the method for improving efficiency of accessing the off-chip memory according to the present invention. As shown in fig. 2, the system 1 includes a plurality of RISC-V single- core processors 11, 12, 13, and 14, a plurality of off- chip memories 21, 22, 23, and 24, and a plurality of caches a, b, c, and d. The RISC-V single-core processor, the off-chip memory and the cache are all correspondingly arranged, for example, the RISC-V single-core processor 11 is correspondingly configured with the off-chip memory 21, and the cache a is arranged between the RISC-V single-core processor 11 and the off-chip memory 21. And a cross buffer ab is arranged between the buffer a and the buffer b, a cross buffer ac is arranged between the buffer a and the buffer c, and other cross buffers are also arranged similarly.
RISC-V single-core processors refer to single pipeline processors based on RISC-V instructions. The processor accesses off-chip DRAM and may employ a cache to temporarily store portions of the data in order to improve the efficiency of the access. The DRAM is main memory of the system and is used for storing programs and data during the operation of the system, each processor has a separate memory, and the memories are uniformly addressed. Data needing interaction between the caches is temporarily stored in the cross cache, and the cross cache can enable data interaction between tasks running on different processors.
And distributing the tasks to the corresponding single-core processors, and distributing the data of the tasks in the single-core processors to the off-chip memories corresponding to the single-core processors. In some embodiments, the allocating data of the tasks in the single-core processor to the off-chip memories corresponding to the single-core processor comprises: and uniformly addressing the off-chip memory, and distributing the tasks to corresponding storage addresses according to variable types.
And distributing the shared information and/or the interaction data among the tasks of different single-core processors to the corresponding cross caches. In some embodiments, the allocating shared information and/or interaction data between tasks of different single-core processors to corresponding cross-caches includes: distributing the shared information and/or the interactive data to the corresponding cache preset addresses based on the interactive objects; and loading the shared information and/or interaction data into the cross-cache in response to the task execution.
The RISC-V single-core processor 11 is taken as a main processor and is responsible for loading an operating system and starting other three single-core processors. After the system is prepared, the operating system is responsible for loading application programs, distributing tasks to each RISC-V single-core processor according to program characteristics, distributing data required by each task to a DRAM managed by the processor, and distributing shared information or interactive data among the tasks to cross caches connected with the caches of each RISC-V single-core processor according to mutual relations.
The RISC-V single-core processor in the embodiment of the invention can directly adopt the corresponding cache and the off-chip memory when executing the task, and can directly interact with other processors or caches through the cross cache if meeting the situation that the interaction with other processors or caches is needed, thereby greatly improving the interaction efficiency.
It should be particularly noted that, the steps in the embodiments of the method for improving the efficiency of accessing the off-chip memory described above can be interleaved, replaced, added, or deleted, so that these methods for improving the efficiency of accessing the off-chip memory by reasonable permutation and combination conversion also belong to the scope of the present invention, and the scope of the present invention should not be limited to the embodiments.
In view of the above object, a second aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, configuring corresponding cache and off-chip memory for each single-core processor in the multi-core processor; s2, setting corresponding cross buffers between every two buffers; s3, responding to the received processing task, distributing the task to the corresponding single-core processor, and distributing the data of the task in the single-core processor to the off-chip memory corresponding to the single-core processor; and S4, distributing the shared information and/or the interaction data among the tasks of different single-core processors to the corresponding cross caches.
In some embodiments, configuring each of the multi-core processors with the corresponding cache and off-chip memory comprises: configuring an off-chip memory managed by the single-core processor for each single-core processor, and setting a cache between the single-core processor and the off-chip memory.
In some embodiments, the setting of the corresponding cross-cache between each two caches includes: sequentially judging whether cross caches exist between the two caches; and creating a cross-cache between the two caches in response to there not being a cross-cache between the two caches.
In some embodiments, the allocating data of the tasks in the single-core processor to the off-chip memories corresponding to the single-core processor comprises: and uniformly addressing the off-chip memory, and distributing the tasks to corresponding storage addresses according to variable types.
In some embodiments, the allocating shared information and/or interaction data between tasks of different single-core processors to corresponding cross-caches includes: distributing the shared information and/or the interactive data to the corresponding cache preset addresses based on the interactive objects; and loading the shared information and/or interaction data into the cross-cache in response to the task execution.
Fig. 3 is a schematic hardware structure diagram of an embodiment of the method for improving efficiency of accessing the off-chip memory according to the present invention.
Taking the apparatus shown in fig. 3 as an example, the apparatus includes a processor 301 and a memory 302, and may further include: an input device 303 and an output device 304.
The processor 301, the memory 302, the input device 303 and the output device 304 may be connected by a bus or other means, and fig. 3 illustrates the connection by a bus as an example.
The memory 302, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the method for improving efficiency of accessing off-chip memory in the embodiments of the present application. The processor 301 executes various functional applications of the server and data processing by running the non-volatile software programs, instructions and modules stored in the memory 302, i.e. implements the method of the above method embodiment for improving efficiency of accessing the off-chip memory.
The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to use of a method of improving efficiency of accessing the off-chip memory, and the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 303 may receive information such as a user name and a password that are input. The output means 304 may comprise a display device such as a display screen.
Program instructions/modules corresponding to one or more methods of increasing the efficiency of accessing off-chip memory are stored in memory 302 and, when executed by processor 301, perform the method of increasing the efficiency of accessing off-chip memory of any of the above-described method embodiments.
Any embodiment of a computer device that performs the above method for increasing efficiency of accessing off-chip memory may achieve the same or similar effects as any of the preceding method embodiments to which it corresponds.
The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for improving efficiency of accessing an off-chip memory can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM may be available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method for increasing efficiency of accessing off-chip memory, comprising the steps of:
configuring a corresponding cache and an off-chip memory for each single-core processor in a multi-core processor;
setting corresponding cross caches between every two caches;
responding to the received processing task, distributing the task to a corresponding single-core processor, and distributing the data of the task in the single-core processor to an off-chip memory corresponding to the single-core processor; and
and distributing the shared information and/or the interaction data among the tasks of different single-core processors to the corresponding cross caches.
2. The method of claim 1, wherein configuring each of the multi-core processors with the corresponding cache and off-chip memory comprises:
configuring an off-chip memory managed by the single-core processor for each single-core processor, and setting a cache between the single-core processor and the off-chip memory.
3. The method of claim 1, wherein the setting a corresponding cross buffer between each two buffers comprises:
sequentially judging whether cross caches exist between the two caches; and
creating a cross-cache between the two caches in response to there not being a cross-cache between the two caches.
4. The method of claim 1, wherein distributing data of tasks in the single-core processor to an off-chip memory corresponding to the single-core processor comprises:
and uniformly addressing the off-chip memory, and distributing the tasks to corresponding storage addresses according to variable types.
5. The method of claim 1, wherein the allocating shared information and/or interaction data among tasks of different single-core processors into corresponding cross-caches comprises:
distributing the shared information and/or the interactive data to the corresponding cache preset addresses based on the interactive objects; and
in response to the task execution, loading the shared information and/or interaction data into the cross-cache.
6. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of:
configuring a corresponding cache and an off-chip memory for each single-core processor in a multi-core processor;
setting corresponding cross caches between every two caches;
responding to the received processing task, distributing the task to a corresponding single-core processor, and distributing the data of the task in the single-core processor to an off-chip memory corresponding to the single-core processor; and
and distributing the shared information and/or the interaction data among the tasks of different single-core processors to the corresponding cross caches.
7. The computer device of claim 6, wherein configuring each of the multi-core processors with the corresponding cache and off-chip memory comprises:
configuring an off-chip memory managed by the single-core processor for each single-core processor, and setting a cache between the single-core processor and the off-chip memory.
8. The computer device of claim 6, wherein the setting a corresponding cross-buffer between each two buffers comprises:
sequentially judging whether cross caches exist between the two caches; and
creating a cross-cache between the two caches in response to there not being a cross-cache between the two caches.
9. The computer device of claim 6, wherein the allocating data of the tasks in the single-core processor to the off-chip memory corresponding to the single-core processor comprises:
and uniformly addressing the off-chip memory, and distributing the tasks to corresponding storage addresses according to variable types.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.
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| CN114265812A (en) * | 2021-11-29 | 2022-04-01 | 山东云海国创云计算装备产业创新中心有限公司 | Method, device, equipment and medium for reducing access delay of RISC-V vector processor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101859259A (en) * | 2009-03-20 | 2010-10-13 | 西斯迪尔科学公司 | Has the multiprocessor cache prefetch that the outer bandwidth of sheet is distributed |
| CN105630736A (en) * | 2015-12-29 | 2016-06-01 | 东南大学—无锡集成电路技术研究所 | Data macroblock prediction access device and method for memory system of reconfigurable system |
| CN107734499A (en) * | 2017-07-28 | 2018-02-23 | 国网信通亿力科技有限责任公司 | Suitable for the wireless isolation base station of the transregional Integrated services access of electric power |
-
2019
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101859259A (en) * | 2009-03-20 | 2010-10-13 | 西斯迪尔科学公司 | Has the multiprocessor cache prefetch that the outer bandwidth of sheet is distributed |
| CN105630736A (en) * | 2015-12-29 | 2016-06-01 | 东南大学—无锡集成电路技术研究所 | Data macroblock prediction access device and method for memory system of reconfigurable system |
| CN107734499A (en) * | 2017-07-28 | 2018-02-23 | 国网信通亿力科技有限责任公司 | Suitable for the wireless isolation base station of the transregional Integrated services access of electric power |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114265812A (en) * | 2021-11-29 | 2022-04-01 | 山东云海国创云计算装备产业创新中心有限公司 | Method, device, equipment and medium for reducing access delay of RISC-V vector processor |
| CN114265812B (en) * | 2021-11-29 | 2024-02-02 | 山东云海国创云计算装备产业创新中心有限公司 | Method, device, equipment and medium for reducing access delay of RISC-V vector processor |
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