CN108108324B - PCIE (peripheral component interface express) expansion method and device - Google Patents
PCIE (peripheral component interface express) expansion method and device Download PDFInfo
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- CN108108324B CN108108324B CN201810174592.7A CN201810174592A CN108108324B CN 108108324 B CN108108324 B CN 108108324B CN 201810174592 A CN201810174592 A CN 201810174592A CN 108108324 B CN108108324 B CN 108108324B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F2213/0026—PCI express
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Abstract
The invention discloses a PCIE expansion method and a device, comprising the following steps: the switch is respectively connected to the high-speed bus switching chip and the embedded controller, and the high-speed bus switching chip is connected to an x8 slot of the PCIE; when the switch is set to be connected by using a single x16 bus, the embedded controller controls the PCIE bridge chip to transmit an x16 signal to be transmitted out through the x16 slot, and the high-speed bus switching chip does not work; when the switch is set to be connected by using two x8 buses, the embedded controller controls the PCIE bridge chip to configure x16 signals to be transmitted into two groups of x8 signals, the PCIE bridge chip transmits one group of x8 signals through an x16 slot, meanwhile, the PCIE bridge chip transmits the other group of x8 signals to the high-speed bus switching chip, and the high-speed bus switching chip transmits the other group of x8 signals through an x8 slot. The invention can perform expansion switching according to the requirement aiming at the PCIE slots or the PCIE slots of different types, and has lower cost.
Description
Technical Field
The present invention relates to the field of computers, and in particular, to a PCIE expansion method and apparatus.
Background
In the design of a general computing platform, particularly a domestic computer platform, when resources of a PCIE slot and a bus LINE are allocated and used, the resources are in shortage. For example, platforms sometimes use one x16 slot and sometimes two x8 slots. If two motherboards or PCIE conversion chips are required for both cases, both costs are high. Aiming at the problem of high cost of hot-switch PCIE in the prior art, no effective solution is provided at present.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a PCIE expansion method and apparatus, which can perform expansion switching as needed for PCIE slots or PCIE slots of different types, and have lower cost.
Based on the above object, an aspect of the embodiments of the present invention provides a PCIE expansion method, including the following steps:
the switch is respectively connected to the high-speed bus switching chip and the embedded controller, and the high-speed bus switching chip is connected to an x8 slot of the PCIE;
when the switch is set to be connected by using a single x16 bus, the embedded controller controls the PCIE bridge chip to transmit an x16 signal to be transmitted out through the x16 slot, and the high-speed bus switching chip does not work;
when the switch is set to be connected by using two x8 buses, the embedded controller controls the PCIE bridge chip to configure x16 signals to be transmitted into two groups of x8 signals, the PCIE bridge chip transmits one group of x8 signals through an x16 slot, meanwhile, the PCIE bridge chip transmits the other group of x8 signals to the high-speed bus switching chip, and the high-speed bus switching chip transmits the other group of x8 signals through an x8 slot.
In some embodiments, a PCIE bridge chip configures x16 signals to be transmitted as two groups of x8 signals, configures x0-7 bits of x16 signals to be transmitted as one group of x8 signals, and configures x8-15 bits of x16 signals to be transmitted as another group of x8 signals; or the PCIE bridge chip configures the x8-15 bits of the x16 signal to be transmitted into one group of x8 signals and configures the x0-7 bits of the x16 signal to be transmitted into another group of x8 signals.
In some embodiments, a PCIE bridge die transmits a set of x8 signals out through x16 slots, a set of x8 signals out through x0-7 bits of x16 slots for a PCIE bridge die, or a set of x8 signals out through x8-15 bits of x16 slots for a PCIE bridge die
In some embodiments, when the switch is configured to use two x8 buses, the PCIE bridge chip and the high speed bus switch chip perform synchronous transmission or asynchronous transmission.
In some embodiments, the switch is connected to a GPIO pin of the embedded controller, outputting a high level when the switch is set to use a single x16 bus and outputting a low level when the switch is set to use two x8 buses; the embedded controller is connected to the STRIP pin of the PCIE bridge chip.
In some embodiments, bits x0-7 and bits x8-15 may be logically positive, logically negative, or a pre-specified non-logically sequential order of slots or pins.
In another aspect of the embodiments of the present invention, a PCIE expansion apparatus is further provided, including:
a high-speed bus switching chip connected to the x8 slot;
the PCIE bridge chip is connected to the high-speed bus switching chip and the x16 slot;
the embedded controller is connected to the PCIE bridge chip;
the switch is connected to the high-speed bus switching chip and the embedded controller and used for configuring the connection by using a single x16 bus or two x8 buses;
the PCIE expansion device uses the method.
In another aspect of the embodiments of the present invention, there is also provided a computer device including a memory, at least one processor, and a computer program stored on the memory and executable on the processor, the processor executing the program to perform the method described above.
In another aspect of the embodiments of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, and the computer program is executed by a processor to perform the above method.
In another aspect of the embodiments of the present invention, there is also provided a computer program product including a computer program stored on a computer-readable storage medium, the computer program including instructions which, when executed by a computer, cause the computer to perform the above method.
The invention has the following beneficial technical effects: according to the PCIE expansion method and the device provided by the embodiment of the invention, the switch is respectively connected to the high-speed bus switching chip and the embedded controller, and the high-speed bus switching chip is connected to the x8 slot of the PCIE, when the switch is set to be connected by using a single x16 bus and is set to be connected by using two x8 buses, the embedded controller respectively uses different control modes to control the PCIE bridge piece to work and transmit signals out through the x8 slot or the x16 slot, the PCIE slot or the PCIE slots of different types can be subjected to expansion switching as required, and the cost is effectively reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a PCIE expansion method provided in the present invention;
fig. 2 is a schematic structural diagram of a PCIE expansion device provided in the present invention;
fig. 3 is a schematic hardware structure diagram of an embodiment of a computer device for executing the PCIE expansion method provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
Based on the above object, a first aspect of the embodiment of the present invention provides a PCIE expansion method. Fig. 1 is a schematic flow chart of a PCIE expansion method provided in the present invention.
The PCIE expansion method comprises the following steps:
step S101, respectively connecting a switch to a high-speed bus switching chip and an embedded controller, and connecting the high-speed bus switching chip to an x8 slot of PCIE;
step S103, when the switch is set to be connected by using a single x16 bus, the embedded controller controls the PCIE bridge chip to transmit an x16 signal to be transmitted out through the x16 slot, and the high-speed bus switching chip does not work;
step S105, when the switch is set to be connected by using two x8 buses, the embedded controller controls the PCIE bridge chip to configure x16 signals to be sent into two sets of x8 signals, and the PCIE bridge chip transmits one set of x8 signals through the x16 slot, and simultaneously the PCIE bridge chip sends the other set of x8 signals to the high-speed bus switching chip, and the high-speed bus switching chip transmits the other set of x8 signals through the x8 slot.
In some embodiments, a PCIE bridge chip configures x16 signals to be transmitted as two groups of x8 signals, configures x0-7 bits of x16 signals to be transmitted as one group of x8 signals, and configures x8-15 bits of x16 signals to be transmitted as another group of x8 signals; or the PCIE bridge chip configures the x8-15 bits of the x16 signal to be transmitted into one group of x8 signals and configures the x0-7 bits of the x16 signal to be transmitted into another group of x8 signals.
The original x16 slot can transmit x0-7 bits or x8-15 bits as required, so as to improve the flexibility of the PCIE expansion method and to be compatible with more special requirements.
In some embodiments, a PCIE bridge die transmits a set of x8 signals out through x16 slots, a set of x8 signals out through x0-7 bits of x16 slots for a PCIE bridge die, or a set of x8 signals out through x8-15 bits of x16 slots for a PCIE bridge die
The original x16 slot can be launched at x0-7 bits or x8-15 bits as required, so as to improve the flexibility of the PCIE expansion method and to be compatible with more special requirements.
In some embodiments, when the switch is configured to use two x8 buses, the PCIE bridge chip and the high speed bus switch chip perform synchronous transmission or asynchronous transmission.
In some embodiments, the switch is connected to a GPIO pin of the embedded controller, outputting a high level when the switch is set to use a single x16 bus and outputting a low level when the switch is set to use two x8 buses; the embedded controller is connected to the STRIP pin of the PCIE bridge chip.
Alternatively, the high and low levels may be represented by states of the dial switch, for example, the dial switch outputs a high level in a state of 1 and outputs a low level in a state of 0.
In some embodiments, bits x0-7 and bits x8-15 may be logically positive, logically negative, or a pre-specified non-logically sequential order of slots or pins.
It can be seen from the foregoing embodiments that, in the PCIE expansion method provided in the embodiments of the present invention, the switches are respectively connected to the high-speed bus switching chip and the embedded controller, and the high-speed bus switching chip is connected to the x8 slot of the PCIE, when the switches are set to be connected using a single x16 bus and set to be connected using two x8 buses, the embedded controller respectively uses different control methods to control the PCIE bridge chip to operate and transmit signals through the x8 slot or the x16 slot, so that the PCIE slots or different types of PCIE slots can be expanded and switched as needed, and the cost is effectively reduced.
It should be particularly noted that, all the steps in the embodiments of the PCIE expansion method described above may be intersected, replaced, added, or deleted, and therefore, the PCIE expansion method based on these reasonable permutation and combination transformations shall also belong to the protection scope of the present invention, and the protection scope of the present invention shall not be limited to the embodiments.
In view of the above, a second aspect of the embodiment of the present invention provides a PCIE expansion device. Fig. 2 is a schematic block diagram of a PCIE expansion apparatus provided in the present invention.
The PCIE expansion device comprises:
a high-speed bus switching chip connected to the x8 slot;
the PCIE bridge chip is connected to the high-speed bus switching chip and the x16 slot;
the embedded controller is connected to the PCIE bridge chip;
the switch is connected to the high-speed bus switching chip and the embedded controller and used for configuring the connection by using a single x16 bus or two x8 buses;
the PCIE expansion device uses the PCIE expansion method.
It can be seen from the foregoing embodiments that, in the PCIE expansion device provided in the embodiments of the present invention, the switches are respectively connected to the high-speed bus switching chip and the embedded controller, and the high-speed bus switching chip is connected to the x8 slot of the PCIE, when the switches are set to be connected by using a single x16 bus and are set to be connected by using two x8 buses, the embedded controller respectively uses different control methods to control the PCIE bridge chip to operate and transmit signals through the x8 slot or the x16 slot, so that the PCIE slots or the PCIE slots of different types can be expanded and switched as needed, and the cost is effectively reduced.
It should be particularly noted that, the above embodiment of the PCIE expansion apparatus employs the embodiment of the PCIE expansion method to specifically describe the working process of each module, and those skilled in the art can easily think that these modules are applied to other embodiments of the PCIE expansion method. Of course, since each step in the PCIE expansion method embodiment may be intersected, replaced, added, or deleted, these PCIE expansion devices that are reasonably arranged, combined, and transformed also belong to the protection scope of the present invention, and the protection scope of the present invention should not be limited to the embodiment.
In view of the above object, a third aspect of the embodiments of the present invention provides an embodiment of a computer device for executing the PCIE expansion method.
The computer device for executing the PCIE expansion method includes a memory, at least one processor, and a computer program that is stored in the memory and can be run on the processor, and when the processor executes the computer program, the processor executes any one of the above methods.
Fig. 3 is a schematic diagram of a hardware structure of an embodiment of a computer device for executing the PCIE expansion method provided in the present invention.
Taking the computer device shown in fig. 3 as an example, the computer device includes a processor 301 and a memory 302, and may further include: an input device 303 and an output device 304.
The processor 301, the memory 302, the input device 303 and the output device 304 may be connected by a bus or other means, and fig. 3 illustrates the connection by a bus as an example.
The memory 302 is a non-volatile computer-readable storage medium, and can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the PCIE expansion method in the embodiment of the present application. The processor 301 executes various functional applications and data processing of the server by running the nonvolatile software programs, instructions, and modules stored in the memory 302, that is, implements the PCIE extension method of the foregoing method embodiment.
The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the PCIE expansion device, and the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 303 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the PCIE expansion device. The output means 304 may comprise a display device such as a display screen.
The program instructions/modules corresponding to the one or more PCIE expansion methods are stored in the memory 302, and when executed by the processor 301, the PCIE expansion method in any method embodiment described above is executed.
Any embodiment of the computer device executing the PCIE expansion method may achieve the same or similar effects as any corresponding method embodiment described above.
In view of the foregoing, a fourth aspect of the embodiments of the present invention provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program may execute a PCIE expansion method in any of the above-mentioned method embodiments and a PCIE expansion device/system implementing any of the above-mentioned device/system embodiments. Embodiments of the computer-readable storage medium may achieve the same or similar effects as any of the aforementioned method and apparatus/system embodiments corresponding thereto.
In view of the above object, a fifth aspect of the embodiments of the present invention provides a computer program product, where the computer program product includes a computer program stored on a computer-readable storage medium, where the computer program includes instructions, and when the instructions are executed by a computer, the computer is caused to execute the PCIE expansion method in any method embodiment and the PCIE expansion apparatus/system in any apparatus/system embodiment. Embodiments of the computer program product may achieve the same or similar effects as any of the aforementioned method and apparatus/system embodiments corresponding thereto.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like. Embodiments of the computer program may achieve the same or similar effects as any of the preceding method embodiments to which it corresponds.
In addition, the apparatuses, devices and the like disclosed in the embodiments of the present invention may be various electronic terminal devices, such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer (PAD), a smart television and the like, or may be a large terminal device, such as a server and the like, and therefore the scope of protection disclosed in the embodiments of the present invention should not be limited to a specific type of apparatus, device. The client disclosed in the embodiment of the present invention may be applied to any one of the above electronic terminal devices in the form of electronic hardware, computer software, or a combination of both.
Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions described herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a," "an," "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (7)
1. A PCIE expansion method is characterized by comprising the following steps:
respectively connecting a switch to a high-speed bus switching chip and an embedded controller, and connecting the high-speed bus switching chip to an x8 slot of PCIE; wherein the switch is connected to a GPIO pin of the embedded controller, outputs a high level when the switch is set to use a single x16 bus, and outputs a low level when the switch is set to use two x8 buses; the embedded controller is connected to a STRIP pin of the PCIE bridge piece, the high and low levels are represented by the state of a dial switch, the dial switch outputs the high level in the state of 1, and outputs the low level in the state of 0;
when the switch is set to be connected by using a single x16 bus, the embedded controller controls the PCIE bridge chip to transmit an x16 signal to be transmitted out through an x16 slot, and the high-speed bus switching chip does not work;
when the switch is set to be connected by using two x8 buses, the embedded controller controls the PCIE bridge chip to configure the x16 signals to be sent as two sets of x8 signals, configure x0-7 bits of the x16 signals to be sent as the one set of x8 signals, and configure x8-15 bits of the x16 signals to be sent as the other set of x8 signals; or the PCIE bridge chip configures x8-15 bits of the x16 signal to be transmitted as the group of x8 signals, and configures x0-7 bits of the x16 signal to be transmitted as the other group of x8 signals;
the PCIE bridge chip transmits the group of x8 signals through an x16 slot, transmits the group of x8 signals through x0-7 bits of an x16 slot for the PCIE bridge chip, or transmits the group of x8 signals through x8-15 bits of an x16 slot for the PCIE bridge chip.
2. The method of claim 1, wherein when the switch is configured to use two x8 buses, the PCIE bridge chip and the high-speed bus switch chip perform synchronous transmission or asynchronous transmission.
3. The method of claim 1 or 2, wherein the x0-7 bits and the x8-15 bits are logically positive order bits, logically negative order bits, or pre-designated non-logically sequential order bits of a slot or pin.
4. A PCIE expansion apparatus, comprising:
a high-speed bus switching chip connected to the x8 slot;
the PCIE bridge chip is connected to the high-speed bus switching chip and the x16 slot;
the embedded controller is connected to the PCIE bridge chip;
a switch connected to the high speed bus switch chip and the embedded controller for configuring either a single x16 bus connection or two x8 bus connections;
the PCIE expansion device uses the method of any one of claims 1-3.
5. A computer device comprising a memory, at least one processor and a computer program stored on the memory and executable on the processor, characterized in that the processor performs the method according to any of claims 1-3 when executing the program.
6. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the method of any one of claims 1 to 3.
7. A computer program product, characterized in that the computer program product comprises a computer program stored on a computer-readable storage medium, the computer program comprising instructions which, when executed by a computer, cause the computer to carry out the method of any one of claims 1-3.
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| CN108897710B (en) * | 2018-07-06 | 2021-04-06 | 郑州云海信息技术有限公司 | System for automatically switching system management bus |
| CN110780932A (en) * | 2019-09-26 | 2020-02-11 | 苏州浪潮智能科技有限公司 | Working mode switching method and device of PCIE switching chip |
| CN113342714B (en) * | 2020-03-02 | 2023-07-25 | 群联电子股份有限公司 | Memory storage device and management method thereof |
| CN111858431B (en) * | 2020-07-09 | 2022-08-02 | 苏州浪潮智能科技有限公司 | PCIE (peripheral component interface express) -based extension cabinet hot plug method, device, equipment and medium |
| CN111935707A (en) * | 2020-07-29 | 2020-11-13 | 北京三未信安科技发展有限公司 | Cipher device and cipher equipment |
| CN112416828A (en) * | 2020-11-20 | 2021-02-26 | 苏州浪潮智能科技有限公司 | Method, system, device and medium for maintaining PCIE signal connection by using in-place signal |
| CN114281732B (en) * | 2021-11-26 | 2023-08-04 | 苏州浪潮智能科技有限公司 | UPI-PCIE conversion method and device and electronic equipment |
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| US20150324311A1 (en) * | 2014-05-08 | 2015-11-12 | International Business Machines Corporation | Allocating lanes of a serial computer expansion bus among installed devices |
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| CN201152973Y (en) * | 2008-01-10 | 2008-11-19 | 佛山市顺德区顺达电脑厂有限公司 | Extension card |
| CN203178870U (en) * | 2013-03-14 | 2013-09-04 | 北京立华莱康平台科技有限公司 | Internet access switching card |
| CN203241876U (en) * | 2013-05-09 | 2013-10-16 | 浪潮电子信息产业股份有限公司 | Self-adaptive configuration PCIE expansion box |
| CN104181985A (en) * | 2013-05-27 | 2014-12-03 | 鸿富锦精密电子(天津)有限公司 | Computer mainboard |
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