CN110750489A

CN110750489A - Method, device and medium for deploying operators in FPGA

Info

Publication number: CN110750489A
Application number: CN201910921893.6A
Authority: CN
Inventors: 张静东; 王峰
Original assignee: Suzhou Wave Intelligent Technology Co Ltd
Current assignee: Suzhou Wave Intelligent Technology Co Ltd
Priority date: 2019-09-27
Filing date: 2019-09-27
Publication date: 2020-02-04

Abstract

The invention discloses a method for deploying operators in an FPGA (field programmable gate array), which comprises the following steps of: setting a configuration file comprising a plurality of primary part reconfiguration areas and corresponding secondary part reconfiguration areas; receiving and analyzing a part of reconfiguration files; matching a primary partial reconfiguration region with a corresponding size in the configuration file according to resources required by the partial reconfiguration file, and loading the primary partial reconfiguration region in the FPGA; and matching the combination of the corresponding secondary part reconfiguration regions in the primary part reconfiguration region of the configuration file according to the number of operators in the part reconfiguration file and the combination of resources required by each operator, and loading the corresponding secondary part reconfiguration regions in the FPGA. The invention also discloses a computer device and a readable storage medium. According to the scheme, the two-stage partial reconfiguration region is designed, so that the dependency relationship of different kernel algorithms when the different kernel algorithms are simultaneously realized in the FPGA can be reduced, and the utilization rate of hardware resources in the FPGA is improved.

Description

Method, device and medium for deploying operators in FPGA

Technical Field

The present invention relates to the field of FPGAs, and more particularly, to a method, an apparatus, and a readable medium for deploying an operator in an FPGA.

Background

The existing heterogeneous computing system based on the FPGA has two modes of configuring the FPGA, namely, configuring a whole FPGA chip area to change an acceleration algorithm realized in the FPGA, and configuring partial FPGA chip area resources to change a kernel acceleration algorithm realized in the FPGA. The first method needs to load the whole configuration file of the FPGA into the FPGA by using a JTAG line, or convert the configuration file of the FPGA into a burning file of a FLASH storage device which is not lost when power is off, then burn the burning file into FLASH, and electrify the board card again or execute a reload command to load a new configuration file from the FLASH into an FPGA chip. The second method utilizes a Partial Reconfiguration (PR) technology of the FPGA, and when an acceleration algorithm implemented in the FPGA is updated each time, only a Partial Reconfiguration region occupied by a kernel in the FPGA chip is updated, and configuration files such as a PCIe interface, a DDR interface, an optical module interface driver and the like are reserved.

For the mode of updating the FPGA acceleration algorithm by adopting the first method, loading part of the reconfiguration files by using the JTAG line needs to use a JTAG cable to connect the programming pins of the chip, is only suitable for engineering development and debugging and testing stages, and does not have the feasibility of large-scale deployment. After the engineering development is completed, the FPGA configuration file containing the acceleration algorithm needs to be burned into a storage device, such as Flash, which is not lost when power is down, the size of the Flash is required, the security of the core algorithm is considered, the FPGA configuration file needs to be properly encrypted and protected, an additional encryption circuit is required for support, and the system development cost is increased. By adopting the second partial reconfiguration technology, in the stage of FPGA engineering design, the number of partial reconfiguration regions in an FPGA chip and the size of each reconfiguration region need to be determined, and when a user wants to change another algorithm which occupies more or less resources, the size of the partial reconfiguration region cannot be adjusted according to the actual hardware resources occupied by each algorithm, so that shortage and waste of hardware resources are easily caused when a larger or smaller kernel algorithm is realized in the established partial reconfiguration region. Therefore, the existing reconfiguration method for the FPGA part cannot flexibly and fully utilize hardware resources in the FPGA aiming at different acceleration operators.

Disclosure of Invention

In view of this, embodiments of the present invention provide a method, a device, and a medium for deploying operators in an FPGA, and by designing two stages of PR regions, multiple kernel algorithms can be deployed in the FPGA without changing a static region design of an FPGA chip, so that a dependency relationship between different kernel algorithms when the kernel algorithms are simultaneously implemented in the FPGA can be reduced, a utilization rate of hardware resources in the FPGA can be improved, and power consumption of the entire FPGA heterogeneous computing system can be further reduced.

Based on the above object, an aspect of the embodiments of the present invention provides a method for deploying an operator in an FPGA, including the following steps: setting a configuration file comprising a plurality of primary part reconfiguration areas and corresponding secondary part reconfiguration areas; receiving and analyzing a part of reconfiguration files; matching a primary partial reconfiguration region with a corresponding size in the configuration file according to resources required by the partial reconfiguration file, and loading the primary partial reconfiguration region in the FPGA; and according to the number of operators in the partial reconfiguration file and the combination of resources required by each operator, matching the combination of the number and the size of the corresponding secondary partial reconfiguration region in the primary partial reconfiguration region of the configuration file, and loading the corresponding secondary partial reconfiguration region in the FPGA.

In some embodiments, setting a profile that includes a plurality of primary partial reconfiguration regions and corresponding secondary partial reconfiguration regions includes: setting a plurality of primary partial reconfiguration areas with different sizes; respectively setting a plurality of secondary part reconfiguration areas for each primary part reconfiguration area according to the size of the primary part reconfiguration area; and writing the primary part reconfiguration region and the secondary part reconfiguration region to a configuration file.

In some embodiments, the setting, for each primary partial reconfiguration region, a plurality of secondary partial reconfiguration regions according to the size of the primary partial reconfiguration region respectively comprises: and forming a plurality of primary part reconfiguration regions with the same size in a manner of combining mutually different secondary part reconfiguration regions.

In some embodiments, matching, in the primary partial reconfiguration region of the configuration file, a combination of a number and a size of corresponding secondary partial reconfiguration regions, based on a combination of a number of operators in the partial reconfiguration file and resources required by each operator, comprises: judging whether a combination of two-level part reconfiguration regions of the adaptation part reconfiguration file exists in the configuration file; and in response to the combination of the secondary part reconfiguration regions of the adaptation part reconfiguration file not existing in the configuration file, writing the new combination into the configuration file.

In some embodiments, determining whether a combination of secondary portion reconfiguration regions of the adaptation portion reconfiguration file exists in the configuration file comprises: and judging whether the matching time exceeds a threshold value.

In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: setting a configuration file comprising a plurality of primary part reconfiguration areas and corresponding secondary part reconfiguration areas; receiving and analyzing a part of reconfiguration files; matching a primary partial reconfiguration region with a corresponding size in the configuration file according to resources required by the partial reconfiguration file, and loading the primary partial reconfiguration region in the FPGA; and according to the number of operators in the partial reconfiguration file and the combination of resources required by each operator, matching the combination of the number and the size of the corresponding secondary partial reconfiguration region in the primary partial reconfiguration region of the configuration file, and loading the corresponding secondary partial reconfiguration region in the FPGA.

In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.

The invention has the following beneficial technical effects: by designing the two stages of PR regions, multiple kernel algorithms can be simultaneously deployed in the FPGA on the premise of not changing the static region design of the FPGA chip, so that the dependency relationship of different kernel algorithms when being simultaneously realized in the FPGA can be reduced, the utilization rate of hardware resources in the FPGA is improved, and the power consumption of the whole FPGA heterogeneous computing system is further reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of a method for deploying operators in an FPGA according to the present invention;

fig. 2 is a flowchart of an embodiment of a method for deploying an operator in an FPGA according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

Based on the above purpose, a first aspect of the embodiments of the present invention provides an embodiment of a method for deploying an operator in an FPGA. Fig. 1 is a schematic diagram illustrating an embodiment of a method for deploying an operator in an FPGA according to the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:

s1, setting a configuration file comprising a plurality of primary part reconfiguration areas and corresponding secondary part reconfiguration areas;

s2, receiving and analyzing part of the reconfiguration file;

s3, matching a primary partial reconfiguration region with a corresponding size in the configuration file according to the resources required by the partial reconfiguration file, and loading the primary partial reconfiguration region in the FPGA; and

s4, according to the number of operators in the partial reconfiguration file and the combination of resources required by each operator, matching the combination of the number and size of the corresponding secondary partial reconfiguration region in the primary partial reconfiguration region of the configuration file, and loading the corresponding secondary partial reconfiguration region in the FPGA.

Heterogeneous computing refers to the use of different computing chips in a computing system or the use of different system architecture forms for the same chip. Most of the traditional computing methods adopt homogeneous computing systems, for example, a CPU is used as a single computing chip in one computing system, and the system adopts centralized local computing, which is the traditional homogeneous computing system. When the CPU and the FPGA accelerator are adopted for calculation, the system belongs to a heterogeneous computing system. Heterogeneous computing systems that employ FPGA accelerator cards for accelerated computing, the FPGA accelerators typically exist in the form of PCIe peripheral cards. The FPGA has natural parallel computing capability, is particularly suitable for processing data stream with large bit width, makes up the defects of CPU parallel computing, shares the computing pressure of the CPU, improves the performance of the whole computing system and reduces the power consumption of the system.

The FPGA partial reconfiguration is a loading technology capable of dynamically reconfiguring a local area in the FPGA, and by utilizing the technology, the configuration file of the partial reconfiguration area can be downloaded again under the condition that the normal work of other areas is not influenced, so that the function of switching different services is realized. The technology is very suitable for a complex system which realizes different functions by time division multiplexing FPGA internal hardware resources, and can effectively reduce the hardware resource overhead of system realization.

In order to implement a plurality of functions of dynamically adjusting the size of the partial reconfiguration region, the following operations may be performed:

setting a configuration file comprising a plurality of primary partial reconfiguration regions and corresponding secondary partial reconfiguration regions. In some embodiments, setting a profile that includes a plurality of primary partial reconfiguration regions and corresponding secondary partial reconfiguration regions includes: setting a plurality of primary partial reconfiguration areas with different sizes; respectively setting a plurality of secondary part reconfiguration areas for each primary part reconfiguration area according to the size of the primary part reconfiguration area; and writing the primary part reconfiguration region and the secondary part reconfiguration region to a configuration file. For example, if the system allows, a plurality of primary partial reconfiguration regions with sizes of 9, 10, 11, 12, and 13 are set, a plurality of secondary partial reconfiguration regions, for example, 2, 3, and 4, may be included in the primary partial reconfiguration region with size of 9, and similarly, the primary partial reconfiguration regions with sizes of 10, 11, 12, and 13 are written into the configuration file, and then the primary partial reconfiguration regions and the corresponding secondary partial reconfiguration regions are written into the configuration file.

In some embodiments, the setting, for each primary partial reconfiguration region, a plurality of secondary partial reconfiguration regions according to the size of the primary partial reconfiguration region respectively comprises: and forming a plurality of primary part reconfiguration regions with the same size in a manner of combining mutually different secondary part reconfiguration regions. Continuing with the above example, the primary partial reconfiguration region with the size of 9 may include 3 secondary partial reconfiguration regions, where the combination of one is 1, 2, and 6, and the combination of two is 2, 3, and 4, which is just an example of the combination manner, and the specific combination manner may also include many other combinations.

And receiving and analyzing a part of the reconfiguration file. And transmitting part of the reconfiguration files downwards from the Host computer to the FPGA chip through PCIe (peripheral component interface express), network or JTAG (joint test action group) channels and other modes, and analyzing the received reconfiguration files by a reconfiguration module in the FPGA to obtain resources required by the part of the reconfiguration files, the number of operators and the resources required by each operator.

And matching a primary partial reconfiguration region with a corresponding size in the configuration file according to resources required by the partial reconfiguration file, and loading the primary partial reconfiguration region in the FPGA. For example, the resource required for the partial reconfiguration file is 10, and then a primary partial reconfiguration region of size 10 is matched in the configuration file. And loading the primary partial reconfiguration region after matching to the corresponding primary partial reconfiguration region.

And matching the number and size combination of the corresponding secondary part reconfiguration regions in the primary part reconfiguration region of the configuration file according to the number of operators in the part reconfiguration file and the combination of resources required by each operator, and loading the secondary part reconfiguration regions in the FPGA. Continuing with the above example, the number of operators in the partial reconfiguration file is 3, the resources required by each operator are 1, 2, and 7, respectively, the matching number in the primary partial reconfiguration region with the size of 10 is 3, and the sizes are the combined secondary partial reconfiguration regions of 1, 2, and 7, respectively.

In some embodiments, matching, in the primary partial reconfiguration region of the configuration file, a combination of a number and a size of corresponding secondary partial reconfiguration regions, based on a combination of a number of operators in the partial reconfiguration file and resources required by each operator, comprises: judging whether a combination of two-level part reconfiguration regions of the adaptation part reconfiguration file exists in the configuration file; and in response to the combination of the secondary part reconfiguration regions of the adaptation part reconfiguration file not existing in the configuration file, writing the new combination into the configuration file. Continuing with the above example, if there are no secondary partial reconfiguration regions matching a number of 3 and having a size of 1, 2, 7, respectively, in a primary partial reconfiguration region of size 10, then one such combination may be newly created and written to the configuration file. A similar approach may also be used when matching primary partial reconfiguration regions.

In some embodiments, determining whether a combination of secondary portion reconfiguration regions of the adaptation portion reconfiguration file exists in the configuration file comprises: and judging whether the matching time exceeds a threshold value. A time threshold may be set, for example, 0.1 second, and if the matching time exceeds 0.1 second and the corresponding secondary portion reconfiguration region is not matched yet, the combination of the secondary portion reconfiguration regions in which the adaptation portion reconfiguration file does not exist in the configuration file is considered.

The main advantages of the embodiments of the present invention are at least the following:

1. the convenience brought by the original partial reconfiguration technology is reserved, for example, partial reconfiguration regions can be loaded in various modes, the function of a kernel algorithm is changed, the safety of a core algorithm is improved, and the development cost of the whole system is reduced;

2. part of the reconfiguration region can be loaded without relying on JTAG cables and other off-chip memory chips;

3. on the premise of not changing the static region, the size of the reconfiguration region of the kernel part can be changed according to the number of hardware resources consumed by the actual kernel algorithm, so that the hardware resources are saved for other acceleration algorithms;

4. by adopting the improved on-line partial reconfiguration technology, partial reconfiguration files with specific sizes can be loaded according to actual needs, so that the system development time is reduced, and the time for loading programs on the system is also reduced.

Fig. 2 is a flowchart illustrating an embodiment of a method for deploying operators in an FPGA according to the present invention. As shown in FIG. 2, beginning at block 101 and proceeding to block 102, a configuration file is set; continuing to block 103, receiving and parsing a portion of the reconfiguration file; then, proceeding to block 104, matching the primary partial reconfiguration region of the corresponding size in the configuration file according to the resources required by the partial reconfiguration file; proceeding to block 105, load the level one partial reconfiguration region in the FPGA; proceeding to block 106, matching a combination of the number and size of the corresponding secondary partial reconfiguration regions in the primary partial reconfiguration region according to the number of operators in the partial reconfiguration file and a combination of resources required by each operator; then proceed to block 107, load the secondary partial reconfiguration region in the FPGA; and then proceeds to end at block 108.

It should be particularly noted that, the steps in the embodiments of the method for deploying an operator in an FPGA can be mutually intersected, replaced, added, and deleted, so that these methods for deploying an operator in an FPGA through reasonable permutation and combination transformation also belong to the scope of the present invention, and the scope of the present invention should not be limited to the embodiments.

In view of the above object, a second aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, setting a configuration file comprising a plurality of primary part reconfiguration areas and corresponding secondary part reconfiguration areas; s2, receiving and analyzing part of the reconfiguration file; s3, matching a primary partial reconfiguration region with a corresponding size in the configuration file according to the resources required by the partial reconfiguration file, and loading the primary partial reconfiguration region in the FPGA; and S4, matching the combination of the number and size of the corresponding secondary part reconfiguration region in the primary part reconfiguration region of the configuration file according to the number of operators in the partial reconfiguration file and the combination of resources required by each operator, and loading the corresponding secondary part reconfiguration region in the FPGA.

The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.

Finally, it should be noted that, as one of ordinary skill in the art can appreciate, all or part of the processes in the methods of the above embodiments may be implemented by instructing relevant hardware through a computer program, and the program of the method for deploying operators in an FPGA may be stored in a computer readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.

Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.

Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.

Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A method for deploying operators in an FPGA is characterized by comprising the following steps:

setting a configuration file comprising a plurality of primary part reconfiguration areas and corresponding secondary part reconfiguration areas;

receiving and analyzing a part of reconfiguration files;

matching a primary partial reconfiguration region with a corresponding size in the configuration file according to resources required by the partial reconfiguration file, and loading the primary partial reconfiguration region in the FPGA; and

and matching the number and size combination of the corresponding secondary part reconfiguration regions in the primary part reconfiguration region of the configuration file according to the number of operators in the part reconfiguration file and the combination of resources required by each operator, and loading the corresponding secondary part reconfiguration regions in the FPGA.

2. The method of claim 1, wherein setting a profile that includes a plurality of primary partial reconfiguration regions and corresponding secondary partial reconfiguration regions comprises:

setting a plurality of primary partial reconfiguration areas with different sizes;

respectively setting a plurality of secondary partial reconfiguration areas for each primary partial reconfiguration area according to the size of the primary partial reconfiguration area; and

and writing the primary part reconfiguration region and the secondary part reconfiguration region into a configuration file.

3. The method of claim 2, wherein the setting a plurality of secondary partial reconfiguration regions for each primary partial reconfiguration region according to the size of the primary partial reconfiguration region comprises:

and forming a plurality of primary part reconfiguration regions with the same size in a manner of combining mutually different secondary part reconfiguration regions.

4. The method of claim 1, wherein matching a combination of the number and size of corresponding secondary partial reconfiguration regions in the primary partial reconfiguration region of the configuration file, based on a combination of the number of operators in the partial reconfiguration file and the resources required by each operator, comprises:

judging whether a combination of two-level partial reconfiguration regions which are adapted to the partial reconfiguration file exists in the configuration file; and

in response to there being no combination of secondary partial reconfiguration regions in the configuration file that fit the partial reconfiguration file, writing a new combination into the configuration file.

5. The method of claim 4, wherein the determining whether a combination of secondary partial reconfiguration regions that fit the partial reconfiguration file exists in the configuration file comprises:

and judging whether the matching time exceeds a threshold value.

6. A computer device, comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of:

receiving and analyzing a part of reconfiguration files;

7. The computer device of claim 6, wherein setting a profile that includes a plurality of primary partial reconfiguration regions and corresponding secondary partial reconfiguration regions comprises:

8. The computer device of claim 7, wherein said setting a plurality of secondary partial reconfiguration regions for each of the primary partial reconfiguration regions according to the size of the primary partial reconfiguration region comprises:

9. The computer device of claim 6, wherein said matching, in the primary partial reconfiguration region of the configuration file, a combination of a number and a size of corresponding secondary partial reconfiguration regions according to a combination of a number of operators in the partial reconfiguration file and resources required by each operator comprises:

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.