CN110764799A

CN110764799A - Method, equipment and medium for optimizing and remotely updating FPGA (field programmable Gate array) accelerator card

Info

Publication number: CN110764799A
Application number: CN201910921895.5A
Authority: CN
Inventors: 李振辉; 阚宏伟; 王彦伟
Original assignee: Suzhou Wave Intelligent Technology Co Ltd
Current assignee: Suzhou Wave Intelligent Technology Co Ltd
Priority date: 2019-09-27
Filing date: 2019-09-27
Publication date: 2020-02-07

Abstract

The invention discloses a method for optimizing and remotely updating an FPGA accelerator card, which comprises the following steps: stopping all system activities and creating a memory snapshot mirror image to write into a disk in response to receiving information that updating sent by the FPGA accelerator card is completed; powering off and informing the server; responding to a received startup awakening command sent by a server, acquiring the memory snapshot mirror image from a disk and loading the memory snapshot mirror image into a memory; and rescanning a PCIE configuration space based on the memory snapshot mirror image to obtain the updated function of the FPGA accelerator card. The invention also discloses a computer device and a readable storage medium. The method, the equipment and the medium for optimizing the remote updating of the FPGA accelerator card provided by the invention backup the system by establishing the system memory snapshot mirror image, avoid the damage of restart operation to system resources, perfect the remote updating process and increase the stability of the system.

Description

Method, equipment and medium for optimizing and remotely updating FPGA (field programmable Gate array) accelerator card

Technical Field

The present invention relates to the field of FPGA accelerator cards, and more particularly, to a method, an apparatus, and a readable medium for optimizing a remote update of an FPGA accelerator card.

Background

An FPGA (Field Programmable Gate Array) is a circuit logic device, and has the characteristics of static repeatable programming and online dynamic reconfiguration, and the circuit functions are represented as hardware, but can be modified in a programming manner like software, so that the universality and design flexibility of an electronic system are greatly improved. The nature of the FPGA makes it widely used in heterogeneous acceleration systems.

With the increasingly widespread application of heterogeneous acceleration, the accelerator card based on the FPGA is also in a rapid development process. In specific application, the FPGA accelerator card is connected with a host of a client through a PCIE (Peripheral Component Interconnect Express) interface, a server side can communicate with the FPGA accelerator card through a network interface to complete remote updating operation of the FPGA accelerator card, the upgrading process adopting remote updating greatly facilitates developers of the FPGA, programming is not needed through a special emulator through a special JTAG socket in a special software simulation environment, and the developers are not needed to develop and debug on site.

However, in the process of such remote updating, the newly added function module of the FPGA accelerator card is often inherited from the original function of the FPGA accelerator card, usually the signal line of the PCIE interface is determined in advance and cannot be changed, but for the update of the specific function, the FPGA accelerator card often changes the configuration space of the PCIE, and due to the change of the PCIE configuration space, the Linux operating system must scan the configuration space of the PCIE again, so that the system can identify the new function of the FPGA accelerator card, and for the rescan of the system, the Linux operating system often needs to be restarted, but such a restart operation at a system level inevitably destroys the function module in the system kernel and the data in the memory, further affecting the stability of the system, and thus a solution is urgently needed for the above problems.

Disclosure of Invention

In view of this, embodiments of the present invention provide a method, a device, and a medium for optimizing a remote update FPGA accelerator card, where a system is backed up by creating a system memory snapshot mirror, so as to avoid damage to system resources due to a restart operation, improve a remote update process, and increase system stability.

Based on the above object, an aspect of the embodiments of the present invention provides a method for optimizing a remote update FPGA accelerator card, including the following steps: stopping all system activities and creating a memory snapshot mirror image to write into a disk in response to receiving information that updating sent by the FPGA accelerator card is completed; powering off and informing the server; responding to a received startup awakening command sent by a server, acquiring the memory snapshot mirror image from a disk and loading the memory snapshot mirror image into a memory; and rescanning a PCIE configuration space based on the memory snapshot mirror image to obtain the updated function of the FPGA accelerator card.

In some embodiments, in response to receiving information that the update sent by the FPGA accelerator card is completed, stopping all system activities and creating a memory snapshot image to write to the disk includes: and judging whether to trigger the creation of a memory snapshot mirror image mechanism or not in response to receiving an interrupt sent by the FPGA accelerator card.

In some embodiments, determining whether to trigger the creation of the memory snapshot mirroring mechanism comprises: judging whether the remote updating needs to be restarted or not; and triggering the memory snapshot mirroring establishment mechanism in response to the fact that the remote updating does not need to be restarted.

In some embodiments, further comprising: and the server side sends a remote updating command to the FPGA accelerator card from the local network card in a socket mode.

In some embodiments, further comprising: and in response to the FPGA accelerator card receiving the remote updating command, burning the remotely updated data file into the FLASH of the FPGA accelerator card.

In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: stopping all system activities and creating a memory snapshot mirror image to write into a disk in response to receiving information that updating sent by the FPGA accelerator card is completed; powering off and informing the server; responding to a received startup awakening command sent by a server, acquiring the memory snapshot mirror image from a disk and loading the memory snapshot mirror image into a memory; and rescanning a PCIE configuration space based on the memory snapshot mirror image to obtain the updated function of the FPGA accelerator card.

In some embodiments, the steps further comprise: and the server side sends a remote updating command to the FPGA accelerator card from the local network card in a socket mode.

In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.

The invention has the following beneficial technical effects:

(1) an interrupt processing flow of a linux kernel is bypassed in an UIO (unified input output) architecture mode, so that the interaction delay between application software and a kernel driver is greatly shortened;

(2) the damage of the restart operation to the system resources is protected in a mode of backing up the system memory mirror image;

(3) the remote updating process mechanism is perfected, and the stability of the system is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of a method for optimizing a remote update FPGA accelerator card according to the present invention;

fig. 2 is a flowchart of an embodiment of a method for optimizing a remote update of an FPGA accelerator card according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

Based on the above purpose, the first aspect of the embodiments of the present invention provides an embodiment of a method for optimizing a remote update of an FPGA accelerator card. Fig. 1 is a schematic diagram illustrating an embodiment of the method for optimizing a remote update FPGA accelerator card according to the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:

s1, in response to receiving the information that the updating sent by the FPGA accelerator card is completed, stopping all system activities and creating a memory snapshot mirror image to write in a disk;

s2, powering off and informing the server;

s3, responding to a received startup awakening command sent by a server, acquiring the memory snapshot mirror image from a disk and loading the memory snapshot mirror image into a memory; and

and S4, rescanning the PCIE configuration space based on the memory snapshot mirror image, and acquiring the updated function of the FPGA accelerator card.

A daemon process exists at a client side and is used for communicating with an FPGA acceleration card, an SMI hardware interrupt trigger mechanism is adopted in communication interaction, and an UIO framework is adopted at an application software side and is used for bypassing delay loss caused by an Linux kernel interrupt processing flow, so that system flow delay is greatly optimized. In some embodiments, further comprising: and the server side sends a remote updating command to the FPGA accelerator card from the local network card in a socket mode. When the server sends a remote update command, the FPGA accelerator card receives the remote update command through a Media Access Control (MAC), in some embodiments, the method further includes: and in response to the FPGA accelerator card receiving a remote updating command, burning the remotely updated data file into the FLASH of the FPGA. After a series of remote update commands are executed, the FPGA acceleration card completes the update of the internal FLASH, and then the FPGA acceleration card notifies the daemon (daemon process) of the client end that the FLASH of the FPGA acceleration card is updated through SMI interruption.

In some embodiments, in response to receiving information that the update sent by the FPGA accelerator card is completed, stopping all system activities and creating a memory snapshot image to write to the disk includes: and judging whether to trigger the creation of a memory snapshot mirror image mechanism or not in response to receiving an interrupt sent by the FPGA accelerator card. In some embodiments, determining whether to trigger the creation of the memory snapshot mirroring mechanism comprises: judging whether the remote updating needs to be restarted or not; and triggering the memory snapshot mirroring establishment mechanism in response to the fact that the remote updating does not need to be restarted. And (3) daemon execution stops all system activities of a kernel and creates a memory snapshot to be written into a disk, then the system runs to a state that a snapshot image can be stored, the image is written, finally the system enters a target low-power-consumption state (except some awakening devices, almost all hardware components including the memory are powered off), and meanwhile, a client sends a command to inform a server that the power off is completed.

After receiving the command, the server executes a client startup wake-up operation through an Intelligent Platform Management Interface (IPMI). The wake-up operation finds the memory image and loads it to memory through a director, restores all quiesce activity, restores to a pre-memory snapshot backup state and allows the user space program to be run again. In the awakening process, the system can rescan the PCIE configuration space to acquire the latest FPGA accelerator card function. The method adopts an UIO architecture mode to bypass the interrupt processing flow of the linux kernel, and greatly shortens the interaction delay between the application software and the kernel driver. The method has the advantages that the damage of the restart operation to the system resources is protected in a mode of backing up the system memory mirror image. The remote updating process mechanism is perfected, and the stability of the system is improved.

In order to further explain the whole updating method, the whole method is divided into four parts of remote updating, daemon execution, memory snapshot backup and memory snapshot restoration for detailed description.

The remote updating process comprises the following steps: the FPGA accelerator card obtains an IP address from a server side through a DHCP (Dynamic Host configuration protocol) command, and records the IP address into a DDR (Double Data Rate Synchronous Random access memory, Double Data Synchronous Dynamic Random access memory) of the FPGA board; the server side acquires the IP address and the MAC address of the FPGA accelerator card through the service configuration file of the DHCP; the server configures the acquired IP address and the MAC address into a routing table by modifying the routing table; the server sends a remote updating command to the FPGA board card from the local network card in a socket mode; after receiving the remote updating command, the FPGA board card burns a remote updating data file (such as an rpd file) into the FLASH of the FPGA to complete the remote updating operation; and the FPGA accelerator card generates an SMI interrupt and stores the updated state into a state register provided by the BAR address.

The daemon execution process includes: a client Linux system background starts daemon (daemon process) for finishing subsequent operations such as state judgment, command execution and the like; polling read/dev/uioX equipment nodes by daemon (daemon process), bypassing an interrupt processing flow of a linux kernel by adopting a UIO architecture mode, and judging whether SMI interrupt of PCIE is generated; if SMI interruption is generated, continuously reading a status register provided by PCIE through a BAR address, judging whether the remote updating operation needs to restart the Linux operating system or not, if the remote updating operation does not need to be restarted, quitting continuous round training to judge the next SMI interruption, sending an FPGA acceleration card updating completion command to the server side, and if the remote updating operation needs to be restarted, informing the system to enter a memory snapshot backup process through a signal mechanism.

The memory snapshot backup process comprises the following steps: through the signal mechanism processing flow of the system, the system acquires a command for entering the memory snapshot backup process; the system enters the memory snapshot backup process by writing disk commands into the file/sys/power/state; when the memory snapshot backup process is triggered, the kernel stops all system activities and creates a memory snapshot mirror image to be written into a disk; next, when the system runs to a state that the snapshot image can be saved, the image is written, and finally the system enters a target low-power consumption state (except some awakening devices, almost all hardware components including the memory are powered off); and sending a memory snapshot backup process completion command to the server through the Ethernet.

The memory snapshot recovery process comprises the following steps: receiving a signal fed back by a client in a socket mode, judging whether the received data is an update completion command or a memory snapshot backup process completion command, if the received data is the update completion command, directly quitting the blocking state of the socket, and if the received data is the memory snapshot backup process completion command, performing a memory snapshot recovery process; the server side starts a memory snapshot recovery process by sending a command 'ipmitool-I lan-H172.168.6.3-U root-P password power on' to a BMC chip of the client side; the client receives a memory snapshot recovery process starting command, control is given to platform firmware running a starting director (starting a brand-new kernel instance), the new kernel instance (also called a recovery kernel) searches a snapshot mirror image in a disk, and if the snapshot mirror image is found, the mirror image is loaded into the memory; next, the kernel is overwritten with the mirrored content and jumps to the special trampoline area where the original kernel (also called the mirrored kernel) stored in the mirror is located, which is the area where the special architecture related low level code is provided, and finally the mirrored kernel restores the system to the state before the snapshot backup and allows the user space program to be run again; and in the awakening process, the system rescans the PCIE configuration space to acquire the latest FPGA accelerator card function.

Fig. 2 is a flowchart illustrating an embodiment of a method for optimizing a remote update FPGA accelerator card according to the present invention. As shown in fig. 2, beginning at block 101 and proceeding to block 102, the server side sends a remote update command to the FPGA accelerator card; proceeding to block 103, burning the remotely updated data file into the FLASH of the FPGA acceleration card; then, proceeding to block 104, the FPGA accelerator card sends the updated information to the client; then, proceeding to block 105, the client stops all system activities and creates a memory snapshot mirror image to be written into the disk; then proceeding to block 106, the client notifies the server that the power down is complete; then, proceeding to block 107, the server sends a power-on wake-up command to the client; then, proceeding to block 108, the client finds a memory snapshot mirror image and loads the memory snapshot mirror image into the memory; then, the process proceeds to block 109, rescans the PCIE configuration space, obtains the updated function of the FPGA accelerator card, and then proceeds to block 110, where the process ends.

It should be particularly noted that, the steps in the embodiments of the method for optimizing the remote update FPGA accelerator card may be mutually intersected, replaced, added, and deleted, so that these reasonable permutation and combination transformations to the method for optimizing the remote update FPGA accelerator card also belong to the scope of the present invention, and should not limit the scope of the present invention to the embodiments.

In view of the above object, a second aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, in response to receiving the information that the updating sent by the FPGA accelerator card is completed, stopping all system activities and creating a memory snapshot mirror image to write in a disk; s2, powering off and informing the server; s3, responding to a received startup awakening command sent by a server, acquiring the memory snapshot mirror image from a disk and loading the memory snapshot mirror image into a memory; and S4, re-scanning PCIE configuration space based on the memory snapshot mirror image, and acquiring the updated function of the FPGA accelerator card.

In some embodiments, further comprising: and in response to the FPGA accelerator card receiving a remote updating command, burning the remotely updated data file into the FLASH of the FPGA.

The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.

Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by instructing relevant hardware through a computer program, and the program for optimizing the method for remotely updating the FPGA accelerator card can be stored in a computer-readable storage medium, and when executed, the program can include the processes of the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.

Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.

Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.

Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A method for optimizing and remotely updating an FPGA accelerator card is characterized by comprising the following steps:

stopping all system activities and creating a memory snapshot mirror image to write into a disk in response to receiving information that updating sent by the FPGA accelerator card is completed;

powering off and informing the server;

responding to a received startup awakening command sent by a server, acquiring the memory snapshot mirror image from the disk and loading the memory snapshot mirror image into a memory; and

and rescanning a PCIE configuration space based on the memory snapshot mirror image to obtain the updated function of the FPGA accelerator card.

2. The method of claim 1, wherein stopping all system activities and creating a memory snapshot image to write to disk in response to receiving information that the update from the FPGA accelerator card is complete comprises:

and judging whether to trigger the creation of a memory snapshot mirror image mechanism or not in response to receiving an interrupt sent by the FPGA accelerator card.

3. The method of claim 2, wherein determining whether to trigger creation of the memory snapshot mirroring mechanism comprises:

judging whether the remote updating needs to be restarted or not; and

and triggering the memory snapshot mirroring establishment mechanism in response to the fact that the remote updating does not need to be restarted.

4. The method of claim 1, further comprising:

and the server side sends a remote updating command to the FPGA accelerator card from the local network card in a socket mode.

5. The method of claim 4, further comprising:

and in response to the FPGA accelerator card receiving the remote updating command, burning the remotely updated data file into the FLASH of the FPGA accelerator card.

6. A computer device, comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of:

powering off and informing the server;

7. The computer device of claim 6, wherein in response to receiving information that the update from the FPGA accelerator card is complete, stopping all system activities and creating a memory snapshot image to write to disk comprises:

8. The computer device of claim 7, wherein determining whether to trigger creation of the memory snapshot mirroring mechanism comprises:

judging whether the remote updating needs to be restarted or not; and

9. The computer device of claim 6, wherein the steps further comprise:

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.