CN114281732B

CN114281732B - UPI-PCIE conversion method and device and electronic equipment

Info

Publication number: CN114281732B
Application number: CN202111425431.9A
Authority: CN
Inventors: 李希栓
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2021-11-26
Filing date: 2021-11-26
Publication date: 2023-08-04
Anticipated expiration: 2041-11-26
Also published as: CN114281732A

Abstract

The embodiment of the application discloses a conversion method from UPI to PCIE, comprising the following steps: taking x16 data signals from the UPI connector, and configuring PCIE control signals in the MCIO connector; connecting the x16 data signals with the PCIE control signals, and directly or indirectly connecting the connected signals to a PCIE adapter; and connecting the SMBUS control signal to the PCIE adapter through the SMB AUX connector, and outputting the PCIE signal by the PCIE adapter. According to the method, when the UPI connector of the single-path system is idle, the UPI signal is converted into the PCIE signal through configuration control signals, so that the UPI bus is temporarily used as the PCIE bus, the resource utilization rate is improved, and the problem of PCIE bus resource shortage is solved. The application also discloses a conversion device from UPI to PCIE and electronic equipment, which have the beneficial effects.

Description

UPI-PCIE conversion method and device and electronic equipment

Technical Field

The invention relates to the technical field of board card design, in particular to a method and a device for converting UPI to PCIE and electronic equipment.

Background

The existing server mainly takes multiple paths such as two paths, four paths and the like as main paths, and all CPUs are directly connected by adopting a UPI bus. As shown in fig. 1, the UPI and PCIE buses of the two servers are configured as a schematic diagram, and the CPUs 0 and 1 of the two servers are interconnected through a UPI bus of 6 paths x24, and generally adopt direct connection, and the middle is free of connectors. In the above server, the UPI and PCIE are two completely different bus signals, and one CPU outputs 6 x16 PCIE signals, and the number of PCIE is limited due to the interface limitation of the CPU.

In practical application, due to technical verification or other needs, the two-way system or the multi-way system is sometimes required to be split into a single-way system, and because the split two single-way system CPUs are connected by a UPI bus, when the split single-way system of the main CPU0 operates independently, the UPI bus is idle because of no interconnection of the CPUs 1, so that UPI bus resource waste is caused.

Therefore, in order to solve the problem of idle resources of the UPI bus of the single-path system, a conversion method from UPI to PCIE is provided, so that the UPI bus is temporarily used as the PCIE bus, and the resource utilization rate is improved.

Disclosure of Invention

The invention aims to provide a method and a device for converting UPI into PCIE and electronic equipment, which temporarily convert a UPI bus into a PCIE bus through circuit design, thereby relieving the problem of PCIE bus resource shortage and improving the resource configuration capability.

In order to achieve the above purpose, the invention discloses the following technical scheme:

in one aspect, the present invention provides a method for converting a UPI to a PCIE, where the method includes:

taking x16 data signals from the UPI connector, and configuring PCIE control signals in the MCIO connector;

connecting the x16 data signals with the PCIE control signals, and directly or indirectly connecting the connected signals to a PCIE adapter;

and connecting the SMBUS control signal to the PCIE adapter through the SMB AUX connector, and outputting the PCIE signal by the PCIE adapter.

In the conversion method from UPI to PCIE, further, PCIE control signals are configured in the MCIO connector, where the PCIE control signals include a clock control signal CLK, a reset control signal RST, and an in-place control signal PESNT.

Further, the x16 data signal is connected to the PCIE control signal, and the connected signal is indirectly connected to the PCIE adapter, including the following steps:

the x16 data signals are distributed into four groups of x4 data signals, and each group of x4 data signals is correspondingly connected with the PCIE control signals respectively;

respectively connecting the four groups of x4 data signals and PCIE control signals to four x4 MCIO ports;

and respectively connecting signals output by the four x4 MCIO ports to the PCIE adapter.

Further, the PCIE adapter is provided with four groups of x4 MCIO adapting ports, signals output by the four groups of x4 MCIO adapting ports are correspondingly connected to the four groups of x4 MCIO adapting ports respectively, each group of x4 MCIO adapting ports is correspondingly connected to one AIC, and four x4 MCIO interfaces of the AIC output PCIE signals in a matching mode.

Further, the x16 data signal is connected with the PCIE control signal, the connected signal is directly connected to a PCIE adapter, the PCIE adapter is provided with a PCIE slot of x16, and a PCIE signal is output.

Further, the MCIO connector is an MCIO connector with a size of x4, and the UPI connector, the MCIO connector and the SMB AUX connector are disposed on the motherboard.

Another aspect of the present invention provides a device for converting UPI to PCIE, the device including a motherboard, on which a UPI connector, an MCIO connector, and an SMB AUX connector are disposed,

and taking x16 data signals from the UPI connector, configuring PCIE control signals in the MCIO connector, wherein the PCIE control signals comprise a clock control signal CLK, a reset control signal RST and an in-place control signal PESNT, connecting the x16 data signals with the PCIE control signals, directly or indirectly connecting the connected signals to a PCIE adapter, and connecting the SMBUS control signals to the PCIE adapter through the SMB AUX connector to realize conversion from UPI to PCIE signals.

The device for converting UPI to PCIE further connects the x16 data signal with a PCIE control signal, and the connected signal is indirectly connected to a PCIE adapter, which specifically includes:

the method comprises the steps that x16 data signals are distributed into four groups of x4 data signals, each group of x4 data signals is correspondingly connected with PCIE control signals, the four groups of x4 data signals and the PCIE control signals are respectively connected to four x4 MCIO ports, the PCIE adapter is provided with four groups of x4 MCIO adaptive ports, signals output by the four groups of x4 MCIO ports are correspondingly connected to the four groups of x4 MCIO adaptive ports, each group of x4 MCIO adaptive ports is correspondingly connected with an AIC, and the four x4 MCIO interfaces of the AIC are matched to output PCIE signals.

Further, the x16 data signal is connected to the PCIE control signal, and the signal after connection is directly connected to the PCIE adapter, specifically including:

and connecting the x16 data signals with the PCIE control signals, directly connecting the connected signals to a PCIE adapter, wherein the PCIE adapter is provided with a x16 PCIE slot, and outputting PCIE signals.

In addition, the invention also provides electronic equipment, which comprises: at least one processor, and at least one memory communicatively coupled to the processor;

the memory stores program instructions executable on the processor;

the processor invokes the program instructions to perform the steps of the UPI to PCIE conversion method as described above.

The effects provided in the summary of the invention are merely effects of embodiments, not all effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:

in the embodiment of the application, when the UPI connector of the single-path system is idle, the clock control signal CLK, the reset control signal RST, the in-place control signal PESNT and the SMBUS control signal are configured to convert the UPI signal into the PCIE signal, so that the UPI bus is temporarily used as the PCIE bus, the resource utilization rate is improved, and the problem of resource shortage of the PCIE bus is alleviated.

In addition, according to the embodiment of the present application, the x16 data signal and the PCIE control signal may be connected in a packet manner according to different data information, and then indirectly connected to the PCIE adapter through the MCIO port, so that the embodiment of the present application has flexible resource allocation capability.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic diagram of UPI and PCIE bus configuration of a conventional two-way server;

fig. 2 is a flowchart of a method for converting a UPI to a PCIE according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a conversion device from UPI to PCIE according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a conversion device from UPI to PCIE according to another embodiment of the present application;

fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

It should be noted that references in the specification to "one embodiment," "an example embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases are not intended to refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Furthermore, certain terms are used throughout the specification and the claims that follow to refer to particular components or parts, and it will be understood by those of ordinary skill in the art that manufacturers may refer to a component or part by different terms or terminology. The present specification and the following claims do not take the form of an element or component with the difference in name, but rather take the form of an element or component with the difference in function as a criterion for distinguishing. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. The term "coupled," as used herein, includes any direct or indirect electrical connection. Indirect electrical connection means include connection via other devices.

Referring to fig. 2, fig. 2 shows a flowchart of a method for converting a UPI to a PCIE according to an embodiment of the present invention, including the following steps:

s21, taking x16 data signals from a UPI connector, and configuring PCIE control signals in an MCIO connector;

s22, connecting the x16 data signals with the PCIE control signals, and directly or indirectly connecting the connected signals to a PCIE adapter;

s23, connecting the SMBUS control signal to the PCIE adapter through the SMB AUX connector, and outputting a PCIE signal by the PCIE adapter.

Specifically, in the above embodiment, the PCIE control signal is configured in the MCIO connector, where the PCIE control signal may include a clock control signal CLK, a reset control signal RST, and an in-place control signal PESNT. Preferably, the MCIO connector may be an x4 MCIO connector, and the UPI connector, the MCIO connector, and the SMB AUX connector are disposed on the motherboard.

In some embodiments, in step S22, the x16 data signal is connected to the PCIE control signal, and the connected signal is indirectly connected to the PCIE adapter, which may include the following steps:

As one preferable option, the PCIE adapter is provided with four groups of x4 MCIO adapting ports, signals output by the four groups of x4 MCIO adapting ports are respectively and correspondingly connected to the four groups of x4 MCIO adapting ports, each group of x4 MCIO adapting ports is correspondingly connected with an AIC (network card), and four x4 MCIO interfaces of the AIC cooperate to output PCIE signals, so as to realize conversion from a group of x24 UPI buses to a group of x16 PCIE buses.

In other embodiments, the x16 data signal is connected to the PCIE control signal, the connected signal is directly connected to a PCIE adapter, and the PCIE adapter is provided with a PCIE slot of x16, and outputs a PCIE signal. As one configuration mode, four x16 standard PCIE slots may form one PCIE adapter board card, and different PCIE adapter board card settings may provide multiple conversion modes for UPI to PCIE signals.

As described above, when the single-path system is independently operated after the existing multi-path server is split, there is a problem of waste of UPI bus resources. In the embodiment of the application, when the UPI connector of the one-way system is idle, the UPI signal is converted into the PCIE signal by configuring the control signal, so that the UPI bus is temporarily used as the PCIE bus, the resource utilization rate is improved, and the problem of PCIE bus resource shortage is solved. In addition, according to the difference of the data information, the embodiment connects the x16 data signal with the PCIE control signal, and then directly or indirectly connects the PCIE adapter, which has flexible resource allocation capability.

It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts described, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are all preferred embodiments and that the acts referred to are not necessarily required by the embodiments of the present application.

Referring to fig. 3, fig. 3 illustrates a device 30 for converting a UPI to a PCIE according to an embodiment of the present invention, by which the conversion from the UPI to the PCIE can be achieved, and the device described below may refer to the method described above correspondingly. The UPI to PCIE conversion device 30 includes: the motherboard 30, the motherboard 30 is provided with a CPU31, a UPI connector 32, an MCIO connector 33 and an SMB AUX connector 34, and the motherboard 30 and the UPI connector 32 are electrically connected.

In the conversion device 30 of this embodiment, x16 data signals are taken from the UPI connector 32, PCIE control signals including a clock control signal CLK, a reset control signal RST and an in-place control signal PESNT are configured in the MCIO connector 33, the x16 data signals are connected to the PCIE control signals, the connected signals are directly or indirectly connected to a PCIE adapter 36, and SMBUS control signals are connected to the PCIE adapter 36 through the SMB AUX connector 34, so that conversion from UPI to PCIE signals is achieved.

Specifically, as shown in fig. 3, in this embodiment, the x16 data signal is connected to the PCIE control signal, and the connected signal is indirectly connected to the PCIE adapter 36, which may specifically include:

the x16 data signals are distributed into four groups of x4 data signals, each group of x4 data signals is correspondingly connected with a PCIE control signal, the four groups of x4 data signals and PCIE control signals are respectively connected to four x4 MCIO ports 35, the PCIE adapter 36 may set four groups of x4 MCIO adaptation ports 37, signals output by the four groups of x4 MCIO ports 35 are correspondingly connected to the four groups of x4 MCIO adaptation ports 37, each group of x4 MCIO adaptation ports 37 is correspondingly connected with an AIC (network card) 38, and four x4 MCIO interfaces of the AIC38 cooperate to output PCIE signals.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating a conversion apparatus from UPI to PCIE according to another embodiment of the present invention. The difference compared to the conversion device shown in fig. 3 is that the x16 data signal is connected to the PCIE control signal, and the connected signal is directly connected to the PCIE adapter 36. The PCIE adapter 36 is provided with a PCIE slot 39 of x16, and outputs a PCIE signal. It should be noted that, the PCIE adapter 36 may be configured in various manners, and the conversion device is a preferred embodiment, and the UPI is converted into PCIE in various configurations.

The present application also provides an electronic device, in some embodiments, as shown in fig. 5, the electronic device 50 may include an input unit 51, a memory 52, a processor 53, and an output unit 54. The memory 52 stores program instructions executable on the processor 53, which processor 53 invokes program instructions capable of performing methods and/or techniques based on the various embodiments described above.

Of course, the present invention is capable of other various embodiments and its several details are capable of modification and variation in light of the present invention, as will be apparent to those skilled in the art, without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. The UPI to PCIE conversion method is characterized by comprising the following steps:

connecting an SMBUS control signal to the PCIE adapter through an SMB AUX connector, and outputting a PCIE signal by the PCIE adapter;

a PCIE control signal is configured in the MCIO connector, wherein the PCIE control signal comprises a clock control signal CLK, a reset control signal RST and an in-place control signal PESNT;

connecting the x16 data signals with the PCIE control signals and indirectly connecting the connected signals to the PCIE adapter, including the following steps:

respectively connecting signals output by the four x4 MCIO ports to the PCIE adapter;

the PCIE adapter is provided with four groups of x4 MCIO (micro controller input) adaptive ports, signals output by the four groups of x4 MCIO ports are correspondingly connected to the four groups of x4 MCIO adaptive ports respectively, each group of x4 MCIO adaptive ports is correspondingly connected with an AIC, and the four x4 MCIO interfaces of the AIC output PCIE signals in a matched mode;

the x16 data signals are connected with the PCIE control signals, the connected signals are directly connected to a PCIE adapter, the PCIE adapter is provided with a x16 PCIE slot, and PCIE signals are output;

the MCIO connector is an x4 MCIO connector, and the UPI connector, the MCIO connector and the SMB AUX connector are arranged on the main board.

2. The UPI-PCIE conversion device comprises a main board, and is characterized in that a UPI connector, an MCIO connector and an SMB AUX connector are arranged on the main board,

taking x16 data signals from the UPI connector, configuring PCIE control signals in the MCIO connector, wherein the PCIE control signals comprise a clock control signal CLK, a reset control signal RST and an in-place control signal PESNT, connecting the x16 data signals with the PCIE control signals, directly or indirectly connecting the connected signals to a PCIE adapter, and connecting an SMBUS control signal to the PCIE adapter through the SMB AUX connector to realize conversion from UPI to PCIE signals;

connecting the x16 data signal with the PCIE control signal, and indirectly connecting the connected signal to the PCIE adapter specifically includes:

the x16 data signals are distributed into four groups of x4 data signals, each group of x4 data signals is correspondingly connected with a PCIE control signal, the four groups of x4 data signals and the PCIE control signals are respectively connected to four groups of x4 MCIO ports, the PCIE adapter is provided with four groups of x4 MCIO adaptive ports, signals output by the four groups of x4 MCIO ports are correspondingly connected to the four groups of x4 MCIO adaptive ports, each group of x4 MCIO adaptive ports is correspondingly connected with an AIC, and the four x4 MCIO interfaces of the AIC are matched to output PCIE signals;

connecting the x16 data signal with the PCIE control signal, and directly connecting the connected signal to the PCIE adapter specifically includes:

3. An electronic device, comprising: at least one processor, and at least one memory communicatively coupled to the processor;

the memory stores program instructions executable on the processor;

the processor invoking the program instructions is capable of performing the steps of the UPI to PCIE conversion method of claim 1.