CN114281732A - UPI-PCIE conversion method and device and electronic equipment - Google Patents
UPI-PCIE conversion method and device and electronic equipment Download PDFInfo
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Abstract
The embodiment of the application discloses a method for converting UPI to PCIE, which comprises the following steps: taking x16 data signals from a UPI connector, and configuring PCIE control signals in an MCIO connector; connecting the x16 data signal with the PCIE control signal, and directly or indirectly connecting the connected signal to a PCIE adapter; and the SMBUS control signal is connected to the PCIE adapter through the SMB AUX connector, and the PCIE adapter outputs a PCIE signal. According to the method, when the UPI connector of the single-path system is idle, the UPI signal is converted into the PCIE signal through the configuration of the control signal, so that the UPI bus is used as the PCIE bus temporarily, the resource utilization rate is improved, and the problem of resource shortage of the PCIE bus is solved. The application also discloses a UPI-to-PCIE conversion device and electronic equipment, which have the beneficial effects.
Description
Technical Field
The invention relates to the technical field of board card design, in particular to a UPI-to-PCIE conversion method and device and electronic equipment.
Background
The existing server mainly takes two-way, four-way and other multi-ways, and all CPUs are directly connected by adopting a UPI bus. As shown in fig. 1, a schematic diagram of a configuration of UPI and PCIE buses of two servers in the prior art is shown, where the CPUs 0 and 1 of the two servers are interconnected through a 6-way x24 UPI bus, and generally connected directly without a connector in the middle. In the above server, UPI and PCIE are two completely different bus signals, one CPU outputs 6 PCIE signals of x16, and because of the interface limitation of the CPU, the number of PCIE is limited.
In practical application, due to technical verification or other needs, a two-way system or a multi-way system needs to be split into a single-way system sometimes, and since interconnection of CPUs of the two split single-way systems needs to be connected by using a UPI bus, when the single-way system of the main CPU0 runs alone after splitting, the UPI bus is idle because of no interconnection of the CPUs 1, so that UPI bus resources are wasted.
Therefore, in order to solve the problem that the UPI bus resources of the single-channel system are idle, a UPI to PCIE conversion method is provided, so that the UPI bus is temporarily used as the PCIE bus, and the resource utilization rate is improved.
Disclosure of Invention
The invention aims to provide a method and a device for converting a UPI (unified power interface) bus into a PCIE (peripheral component interface express) bus and electronic equipment, which are used for temporarily converting the UPI bus into the PCIE bus through circuit design, relieving the problem of resource shortage of the PCIE bus and improving the resource configuration capability.
In order to achieve the purpose, the invention discloses the following technical scheme:
one aspect of the present invention provides a method for converting a UPI to a PCIE, where the method includes:
taking x16 data signals from a UPI connector, and configuring PCIE control signals in an MCIO connector;
connecting the x16 data signal with the PCIE control signal, and directly or indirectly connecting the connected signal to a PCIE adapter;
and the SMBUS control signal is connected to the PCIE adapter through the SMB AUX connector, and the PCIE adapter outputs a PCIE signal.
In the method for converting UPI to PCIE, further, PCIE control signals are configured in the MCIO connector, where the PCIE control signals include a clock control signal CLK, a reset control signal RST, and an in-place control signal PESNT.
Further, connecting the x16 data signal with the PCIE control signal, and indirectly connecting the connected signal to the PCIE adapter, includes the following steps:
distributing the x16 data signals into four groups of x4 data signals, wherein each group of x4 data signals are respectively and correspondingly connected with the PCIE control signals;
respectively connecting four groups of x4 data signals and PCIE control signals to four x4 MCIO ports;
and respectively connecting the signals output by the four x4 MCIO ports to the PCIE adapter.
Further, the PCIE adapter is provided with four groups of MCIO adaptation ports x4, signals output by the four MCIO ports x4 are respectively and correspondingly connected to the four groups of MCIO adaptation ports x4, the MCIO adaptation port of each group x4 is correspondingly connected to an AIC, and the four x4 MCIO interfaces of the AIC cooperate to output PCIE signals.
Further, the x16 data signal is connected to the PCIE control signal, the connected signal is directly connected to the PCIE adapter, and the PCIE adapter is provided with a PCIE slot of x16 and outputs a PCIE signal.
Further, the MCIO connector is an x4 MCIO connector, and the UPI connector, the MCIO connector and the SMB AUX connector are arranged on the mainboard.
The invention provides a UPI to PCIE conversion device, which comprises a mainboard, wherein the mainboard is provided with a UPI connector, an MCIO connector and an SMB AUX connector,
the method comprises the steps of taking x16 data signals from the UPI connector, configuring PCIE control signals in the MCIO connector, wherein the PCIE control signals comprise clock control signals CLK, reset control signals RST and in-place control signals PESNT, connecting the x16 data signals with the PCIE control signals, directly or indirectly connecting the connected signals to a PCIE adapter, and connecting SMBUS control signals to the PCIE adapter through the SMB AUX connector to realize conversion from UPI to PCIE signals.
The above-mentioned UPI to PCIE conversion apparatus further connects the x16 data signal with the PCIE control signal, and the signal after the connection is indirectly connected to the PCIE adapter, which specifically includes:
the x16 data signals are distributed into four groups of x4 data signals, each group of x4 data signals are respectively and correspondingly connected with PCIE control signals, the four groups of x4 data signals and the PCIE control signals are respectively and correspondingly connected with four x4 MCIO ports, the PCIE adapter is provided with four groups of x4 MCIO adapter ports, signals output by the four x4 MCIO ports are respectively and correspondingly connected with the four groups of x4 MCIO adapter ports, the MCIO adapter port of each group of x4 is correspondingly connected with an AIC, and four x4 MCIO interfaces of the AIC are matched to output PCIE signals.
Further, connecting the x16 data signal with the PCIE control signal, where the connected signal is directly connected to the PCIE adapter, specifically including:
and connecting the x16 data signal with the PCIE control signal, directly connecting the connected signal to a PCIE adapter, wherein the PCIE adapter is provided with a PCIE slot of x16, and outputting a PCIE signal.
In addition, the present invention also provides an electronic device including: at least one processor, and at least one memory communicatively coupled to the processor;
the memory stores program instructions executable on the processor;
the processor calls the program instructions to perform the steps of the UPI to PCIE conversion method described above.
The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
in the embodiment of the application, when the UPI connector of the one-way system is idle, the UPI signal is converted into the PCIE signal by configuring the clock control signal CLK, the reset control signal RST, the in-place control signal PESNT, and the SMBUS control signal, so that the UPI bus is temporarily used as the PCIE bus, the resource utilization rate is improved, and the problem of resource shortage of the PCIE bus is solved.
In addition, according to the embodiment of the present application, after the x16 data signal is connected to the PCIE control signal in a packet manner according to different data information, the x16 data signal is indirectly connected to the PCIE adapter through the MCIO port, so that the resource configuration capability is flexible.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic diagram of a configuration of UPI and PCIE buses of two existing servers;
fig. 2 is a schematic flow chart of a method for converting UPI to PCIE according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a UPI-to-PCIE conversion device according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a UPI-to-PCIE conversion device according to another embodiment of the present application;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It should be noted that references in the specification to "one embodiment," "an example embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not intended to refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
Moreover, where certain terms are used throughout the description and following claims to refer to particular components or features, those skilled in the art will understand that manufacturers may refer to a component or feature by different names or terms. This specification and the claims that follow do not intend to distinguish between components or features that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. In addition, the term "connected" as used herein includes any direct and indirect electrical connection. Indirect electrical connection means include connection by other means.
Referring to fig. 2, fig. 2 is a schematic flowchart illustrating a UPI-to-PCIE conversion method provided in the embodiment of the present invention, including the following steps:
s21, taking x16 data signals from the UPI connector, and configuring PCIE control signals in the MCIO connector;
s22, connecting the x16 data signal with the PCIE control signal, and directly or indirectly connecting the connected signal to a PCIE adapter;
and S23, connecting the SMBUS control signal to the PCIE adapter through the SMB AUX connector, and outputting the PCIE signal by the PCIE adapter.
Specifically, in the above embodiment, the PCIE control signal is configured in the MCIO connector, and the PCIE control signal may include a clock control signal CLK, a reset control signal RST and an in-place control signal PESNT. Preferably, the MCIO connector may be an x4 MCIO connector, and the UPI connector, the MCIO connector, and the SMB AUX connector are disposed on the motherboard.
In some embodiments, the step of connecting the x16 data signals with the PCIE control signals in the step S22, and indirectly connecting the connected signals to the PCIE adapter, may include the following steps:
distributing the x16 data signals into four groups of x4 data signals, wherein each group of x4 data signals are respectively and correspondingly connected with the PCIE control signals;
respectively connecting four groups of x4 data signals and PCIE control signals to four x4 MCIO ports;
and respectively connecting the signals output by the four x4 MCIO ports to the PCIE adapter.
Preferably, the PCIE adapter is provided with four groups of MCIO adaptation ports x4, signals output by the four MCIO ports x4 are respectively and correspondingly connected to the four groups of MCIO adaptation ports x4, the MCIO adaptation port of each group x4 is correspondingly connected to an AIC (network card), and the four x4 MCIO interfaces of the AIC cooperate to output PCIE signals, so that conversion from a group of UPI buses x24 to a group of PCIE buses x16 is realized.
In some other embodiments, the x16 data signal is connected to the PCIE control signal, the connected signal is directly connected to a PCIE adapter, and the PCIE adapter is provided with a PCIE slot of x16 and outputs a PCIE signal. As a configuration mode, four x16 standard PCIE slots may form one PCIE adapter board, and different PCIE adapter board configurations may provide multiple conversion modes for converting UPI to PCIE signals.
As described above, when a single-channel system operates alone after the existing multi-channel server is split, there is a problem of UPI bus resource waste. In the embodiment of the application, when the UPI connector of the one-way system is idle, the control signal is configured to convert the UPI signal into the PCIE signal, so that the UPI bus is temporarily used as the PCIE bus, the resource utilization rate is improved, and the problem of insufficient PCIE bus resources is solved. In addition, according to the difference of the data information, the x16 data signal is directly or indirectly connected to the PCIE adapter after being connected to the PCIE control signal, so that the resource configuration capability is flexible.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the embodiments are not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the embodiments. Further, those skilled in the art will also appreciate that the embodiments described in the specification are presently preferred and that no particular act is required of the embodiments of the application.
Referring to fig. 3, fig. 3 shows a UPI to PCIE conversion apparatus 30 according to an embodiment of the present invention, which can implement conversion from UPI to PCIE, and the apparatus described below may be referred to in correspondence with the above-described method. The UPI to PCIE conversion apparatus 30 includes: the main board 30 is provided with a CPU31, a UPI connector 32, an MCIO connector 33 and an SMB AUX connector 34, and the main board 30 is electrically connected with the UPI connector 32.
In the conversion device 30 in this embodiment, x16 data signals are taken from the UPI connector 32, PCIE control signals including a clock control signal CLK, a reset control signal RST and an in-place control signal PESNT are configured in the MCIO connector 33, the x16 data signals are connected to the PCIE control signals, the connected signals are directly or indirectly connected to the PCIE adapter 36, and the SMBUS control signals are connected to the PCIE adapter 36 through the SMB AUX connector 34, so that conversion from UPI to PCIE signals is realized.
Specifically, as shown in fig. 3, in this embodiment, connecting the x16 data signal with the PCIE control signal, and indirectly connecting the connected signal to the PCIE adapter 36 may specifically include:
the x16 data signals are distributed into four groups of x4 data signals, each group of x4 data signals are respectively and correspondingly connected with PCIE control signals, the four groups of x4 data signals and PCIE control signals are respectively and correspondingly connected to four x4 MCIO ports 35, the PCIE adapter 36 may be provided with four groups of x4 MCIO adaptation ports 37, signals output by the four x4 MCIO ports 35 are respectively and correspondingly connected to the four groups of x4 MCIO adaptation ports 37, the MCIO adaptation ports 37 of each group of x4 are correspondingly connected with one AIC (network card) 38, and the four x4 MCIO interfaces of the AIC38 cooperate to output PCIE signals.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating a UPI to PCIE conversion apparatus according to another embodiment of the present invention. Compared with the conversion apparatus shown in fig. 3, the difference is that the x16 data signal is connected to the PCIE control signal, and the connected signal is directly connected to the PCIE adapter 36. The PCIE adapter 36 is provided with a PCIE slot 39 of x16, and outputs a PCIE signal. It should be noted that the PCIE adapter 36 may be configured in various structural forms, and the UPI is converted into PCIE corresponding to various configuration modes, which is not limited to this, and the foregoing conversion apparatus is a preferred embodiment.
The present application also provides an electronic device, and in some embodiments, as shown in fig. 5, the electronic device 50 may include an input unit 51, a memory 52, a processor 53, and an output unit 54. The memory 52 stores program instructions operable on the processor 53, and the processor 53 calls the program instructions to perform the method and/or the technical solution according to the foregoing embodiments.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A UPI to PCIE conversion method is characterized by comprising the following steps:
taking x16 data signals from a UPI connector, and configuring PCIE control signals in an MCIO connector;
connecting the x16 data signal with the PCIE control signal, and directly or indirectly connecting the connected signal to a PCIE adapter;
and the SMBUS control signal is connected to the PCIE adapter through the SMB AUX connector, and the PCIE adapter outputs a PCIE signal.
2. The method according to claim 1, wherein PCIE control signals are configured in an MCIO connector, and the PCIE control signals include a clock control signal CLK, a reset control signal RST and an in-place control signal PESNT.
3. The method of converting UPI to PCIE of claim 2, wherein the step of connecting the x16 data signal with the PCIE control signal and indirectly connecting the connected signal to the PCIE adapter comprises the steps of:
distributing the x16 data signals into four groups of x4 data signals, wherein each group of x4 data signals are respectively and correspondingly connected with the PCIE control signals;
respectively connecting four groups of x4 data signals and PCIE control signals to four x4 MCIO ports;
and respectively connecting the signals output by the four x4 MCIO ports to the PCIE adapter.
4. The method according to claim 3, wherein the PCIE adapter is provided with four sets of x4 MCIO adaptation ports, signals output by the four x4 MCIO ports are respectively and correspondingly connected to four sets of x4 MCIO adaptation ports, each set of x4 MCIO adaptation ports is correspondingly connected to an AIC, and four x4 MCIO interfaces of the AIC cooperate to output PCIE signals.
5. The method of claim 2, wherein the x16 data signal is connected to the PCIE control signal, the connected signal is directly connected to a PCIE adapter, and the PCIE adapter is provided with a PCIE slot x16 and outputs a PCIE signal.
6. The UPI-to-PCIE conversion method according to claim 1, wherein the MCIO connector is an x4 MCIO connector, and the UPI connector, the MCIO connector and the SMB AUX connector are disposed on a motherboard.
7. A UPI-to-PCIE conversion device comprises a mainboard, and is characterized in that a UPI connector, an MCIO connector and an SMB AUX connector are arranged on the mainboard,
the method comprises the steps of taking x16 data signals from the UPI connector, configuring PCIE control signals in the MCIO connector, wherein the PCIE control signals comprise clock control signals CLK, reset control signals RST and in-place control signals PESNT, connecting the x16 data signals with the PCIE control signals, directly or indirectly connecting the connected signals to a PCIE adapter, and connecting SMBUS control signals to the PCIE adapter through the SMB AUX connector to realize conversion from UPI to PCIE signals.
8. The UPI-to-PCIE conversion device according to claim 7, wherein the x16 data signal is connected to a PCIE control signal, and the connected signal is indirectly connected to a PCIE adapter, specifically comprising:
the x16 data signals are distributed into four groups of x4 data signals, each group of x4 data signals are respectively and correspondingly connected with PCIE control signals, the four groups of x4 data signals and the PCIE control signals are respectively and correspondingly connected with four x4 MCIO ports, the PCIE adapter is provided with four groups of x4 MCIO adapter ports, signals output by the four x4 MCIO ports are respectively and correspondingly connected with the four groups of x4 MCIO adapter ports, the MCIO adapter port of each group of x4 is correspondingly connected with an AIC, and four x4 MCIO interfaces of the AIC are matched to output PCIE signals.
9. The UPI-to-PCIE conversion device according to claim 7, wherein the x16 data signal is connected to a PCIE control signal, and the connected signal is directly connected to a PCIE adapter, which specifically includes:
and connecting the x16 data signal with the PCIE control signal, directly connecting the connected signal to a PCIE adapter, wherein the PCIE adapter is provided with a PCIE slot of x16, and outputting a PCIE signal.
10. An electronic device, comprising: at least one processor, and at least one memory communicatively coupled to the processor;
the memory stores program instructions executable on the processor;
the processor calls the steps of the program instructions capable of performing the UPI to PCIE conversion method of any one of claims 1 to 6.
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| CN202111425431.9A CN114281732B (en) | 2021-11-26 | 2021-11-26 | UPI-PCIE conversion method and device and electronic equipment |
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| CN202111425431.9A CN114281732B (en) | 2021-11-26 | 2021-11-26 | UPI-PCIE conversion method and device and electronic equipment |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170185502A1 (en) * | 2015-12-24 | 2017-06-29 | Intel Corporation | Automated detection of high performance interconnect coupling |
| CN108108324A (en) * | 2018-03-02 | 2018-06-01 | 山东超越数控电子股份有限公司 | A kind of PCIE extended methods and device |
| US20180191523A1 (en) * | 2016-12-29 | 2018-07-05 | Intel Corporation | High speed interconnect with channel extension |
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- 2021-11-26 CN CN202111425431.9A patent/CN114281732B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170185502A1 (en) * | 2015-12-24 | 2017-06-29 | Intel Corporation | Automated detection of high performance interconnect coupling |
| US20180191523A1 (en) * | 2016-12-29 | 2018-07-05 | Intel Corporation | High speed interconnect with channel extension |
| CN108108324A (en) * | 2018-03-02 | 2018-06-01 | 山东超越数控电子股份有限公司 | A kind of PCIE extended methods and device |
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