CN107734499A - Suitable for the wireless isolation base station of the transregional Integrated services access of electric power - Google Patents
Suitable for the wireless isolation base station of the transregional Integrated services access of electric power Download PDFInfo
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- CN107734499A CN107734499A CN201710627576.4A CN201710627576A CN107734499A CN 107734499 A CN107734499 A CN 107734499A CN 201710627576 A CN201710627576 A CN 201710627576A CN 107734499 A CN107734499 A CN 107734499A
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W12/00—Security arrangements; Authentication; Protecting privacy or anonymity
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
- H04W88/08—Access point devices
Abstract
The invention discloses a kind of transregional Integrated services access of electric power wirelessly to isolate base station, it is mainly made up of BBU and RRU two parts, wherein BBU completes base band signal process, and hardware mainly includes CPU, DSP, FPGA and DRAM, Flash for matching etc., and RRU completes radiofrequency signal processing.The present invention is isolated by operational processor, transmission channel is isolated, memory headroom is isolated, the modes such as isolation of eating dishes without rice or wine realize that the approximate physical of different great Qu business is isolated.By the integrated design of CPE and secure accessing unit, the functions such as safety certification, channel encryption, access control are realized.Wireless isolation northbound interface of the base station by isolation, it is connected respectively with production control great Qu and management information great Qu by backbone network, greatly improves the security of communication port and transregional multiple service supporting.
Description
Technical field
The present invention relates to one kind to isolate base station, particularly a kind of wireless isolation suitable for the transregional Integrated services access of electric power
Base station.
Background technology
Electric power wireless private network refers to the cordless communication network for being specific to oneself by Utilities Electric Co.'s investment construction.Wireless private network
Networking flexibility, wire communication cable laid down cost is saved, do not restricted by a grid structure, suitably carry out large area covering, but
Base station selection, antenna holder height acquire a certain degree of difficulty.Electric power wireless private network can be used for intelligent grid it is defeated, become, match somebody with somebody, with etc. each ring
Section, as shown in figure 1, disclosure satisfy that the traffic demands such as command scheduling, video monitoring, power distribution automation, power information collection.
Electric power wireless private network can not only provide a safe and reliable, easily information transfer channel for intelligent grid, moreover it is possible to which meeting should
The electric power WiMAX multi-service communication requirements such as urgency is speedily carried out rescue work, mobile inspection, engineering construction.Air interface is responsible in wireless base station at present
Related institute is functional：
（1）Radio Link maintenance function, the Radio Link between service terminal is kept, establish the connection with core net, born simultaneously
Blame the protocol conversion of data wireless links and IP data quality supervisions；
（2）Radio resource management function, including the foundation and release of Radio Link, the scheduling of Radio Resource and distribution etc.；
（3）Part mobile management function to ps domain, including configurating terminal measure, assess terminal wireless link-quality, decision-making terminal
In switching of minizone etc.；
（4）Security functions, complete the encryption that wave point sends packet.
At present, in power industry wireless base station using soft isolation method, i.e. base station by the functionality of vlan of interchanger,
For the different VLAN of each great Qu delineation of activities, form switch ports themselves and closed from the one-to-one corresponding of different great Qu electric power backbone networks
System, so as to which the network of 2 or multiple great Qu be isolated.And only carry out VLAN division, it is difficult to effectively ensure communication network
Network safety.In addition, electric power terminal communication access net uses the pattern with operation system construction, so that existing terminal communication access net
Show a variety of communication networks and deposit, every kind of communication network resource utilization rate is not high, the phenomenon of network repeated construction.Basis simultaneously
The safety requirements of electric power " security partitioning, network-specific, lateral isolation, longitudinal certification ", transforms electric power wireless base station, makes
Electric power, which wirelessly isolates base station, can support transregional integrated service, while wireless private network security is lifted, avoid network from repeating
Build.
The content of the invention
It is an object of the invention to overcome the deficiencies in the prior art part, and provide a kind of safety for realizing base station level
Subregion does not repartition production control great Qu and management information great Qu base station, but what is merged is applied to electric power with isolating
The wireless isolation base station of transregional Integrated services access.
A kind of wireless isolation base station suitable for the transregional Integrated services access of electric power, include baseband processing unit BBU sums
Word radio frequency unit RRU two parts form, and wherein BBU completes base band signal process, and hardware includes CPU, DSP, FPGA and matching
DRAM, Flash of set, RRU complete radiofrequency signal processing：
CPU is connected with two separate Ethernet interfaces respectively by two groups of serial gigabit media stand-alone interface SGMII,
CPU serially rapidly inputs output interface SRIO by two groups and is connected with DSP, and DSP is connected by two groups of SRIO interfaces with FPGA,
CPU is polycaryon processor core0~core3, and different core handles different tasks respectively, is connected outside CPU pieces a piece of for depositing
The Flash chip of storage system configuration parameter, configuration processor；Four are connected outside CPU pieces to be used to write and read in CPU implementation procedures
Dram chip DRAM0~the DRAM3 for evidence of fetching, inside CPU, there are two dram controllers to control the outer DRAM of two panels piece respectively,
That is dram controller A controls DRAM0, DRAM1, dram controller B control DRAM2, DRAM3, the data of two dram controllers
Bus, address bus, control line are individually separated not reusing, and tetra- kernels of CPU control two DRAM to control by internal bus
Device processed, wherein, core0, core1, core3 perform reading and writing data by dram controller A, and core2 is held by dram controller B
Row reading and writing data；
DSP is polycaryon processor core0~core5, and different core handles different tasks, four are connected outside DSP pieces respectively
Dram chip DRAM0~DRAM3, data are write and read in the process of implementation for DSP, inside DSP, there is a double-speed
Rate synchronous dynamic random storage DDR SDRAM controller, for dram chip outside control sheet, the outer dram chip of four pieces shares
Address bus, the control line of DDR sdram controllers, DDR sdram controller data/address bus be configured to two groups it is separate
Most bit data bus, the outer DRAM0 and DRAM1 of one of which majority bit data bus connection sheet, another group of multidigit data are total
The outer DRAM2 of line connection sheet and DRAM3, DDR sdram controller have two independent chip selection signal interfaces, outside a connection sheet
DRAM0 and DRAM1, outer six kernels of DRAM2 and DRAM3, DSP of another connection sheet control DDR SDRAM by internal bus
Controller, DRAM outside different pieces is enabled by controlling chip selection signal.
The wireless isolation base station of the present invention is applied in communication network frame, can be achieved to believe production control great Qu with management
The isolation in Xi great areas.
Four cores are included in CPU processor, each core has independent I-Cache and D-Cache, for respective core processor
Instruction and computing intermediate link data buffer storage, herein logic isolation used CPU Affinity（CPU maps）Technology, profit
Different great Qu process is tied on different CPU cores with CPU Affinity technologies, specified by code command selection
Space is answered in verification, corresponds to 4 Cache memory spaces respectively for 4 cores, four cores in MDI buses and piece, outside piece by storing
Device carries out data interaction, and different great Qu business is handled on different core.
Six cores include in DSP Processor, by CLASS buses and piece, chip external memory carry out data interaction, difference
Great Qu business is handled on different core.
Transmission channel isolation includes：
1）Ethernet interface is isolated, and is to transmit different great Qu business datums respectively using two independent network interfaces,
2）SGMII interfaces are isolated, and CPU has two groups of SGMII interfaces to be connected respectively with Ethernet interface,
3）SRIO interfaces are isolated, and have two groups of separate SRIO mouths to carry out not between CPU and DSP, between DSP and FPGA
With great Qu business data transmissions.
Memory headroom is isolated：
In CPU, DRAM outside piece can be configured to 2*32bit memory modes by CPU, i.e. two dram controllers in CPU
Chip external memory can be accessed by 32 bit data bus respectively, wherein core2 by dram controller B to DRAM2 outside piece,
DRAM3 is written and read, and core3 is written and read by dram controller A to DRAM0, DRAM1 outside piece, two dram controllers
Data/address bus, address bus, control line are mutually independent not to be multiplexed, core2 and core3 time-sharing multiplexs storage distribution bus,
The different clock cycle completes the interaction such as data, instruction, realizes that different great Qu business datum timesharing is transmitted in bus；
In DPS, core2, core3 are written and read by DDR controller to DRAM outside piece, pass through chip selection signal control sheet
Outer DRAM；Core2 controls chip selection signal B, and enabled piece outer DRAM2, DRAM3 are written and read operation；Core3 controls chip selection signal A,
Enabled piece outer DRAM0, DRAM1 are written and read operation, and enable signal A and enable signal B can not be enabled simultaneously, and the outer DRAM0 of piece,
Common data bus, the arbitration of core2 and core3 time-sharing multiplexs inside and exchange system be not total with piece outer DRAM2, DRAM3 by DRAM1
Line, the interaction such as data, instruction is completed in the different clock cycle, realize that different great Qu business datum timesharing uploads in bus
It is defeated.
Eat dishes without rice or wine to isolate
FPGA is right after realizing that the separation of business data flow, FPGA receive the data from RRU in units of time/frequency source block TFB
Running time-frequency resource is mapped, according to the rule that system is pre-configured -- time/frequency source block, corresponding data are filled out into DSP
Core ID, core corresponding to DSP is sent to by corresponding SRIO interfaces, realizes different great Qu business datum separation.
Described Flash chip is NAND Flash chips.
In summary, present invention advantage following compared with prior art：
The wireless base station in power network is unified integrated by RRU, BBU, core net, interchanger at present, integration apparatus is formed, by right
Interchanger carries out division VLAN in equipment, realizes the separation of different great Qu business, is still logic isolation in the Nature of Separation, for
VLAN attack method can realize the attack to electric power wireless network easily.In order to lift the network security of electric power wireless private network
Property, transregional attack of the different business in base station end is avoided, the hardware of isolation base station wireless to electric power redesigns, can
The physical isolation of Business Stream is realized on hardware corridor.Compared with other existing physics isolation technologies, the transregional integrated service of electric power
The wireless isolation base station of access is designed hardware corridor design directed entirely to power business stream first, and next realizes CPU core
The calculating isolation of level is isolated with storage, and the core level that different great Qu business are carried out using CPU Affinity technologies is mapped.
Brief description of the drawings
Fig. 1 is the communications network architecture diagram of prior art.
Fig. 2 is the wireless isolation BTS hardware logic diagram of the transregional Integrated services access of electric power of the present invention.
Fig. 3 is the communications network architecture diagram using the wireless isolation base station of the transregional Integrated services access of electric power of the present invention.
Fig. 4 is that two dram controllers control the outer DRAM of two pieces respectively in CPU pieces.
Fig. 5 is DDR controller internal logic block diagram inside dsp chip.
Fig. 6 is that terminal distribution running time-frequency resource realizes shunting figure in FPGA soon.
Embodiment
The present invention is described in more detail with reference to embodiment.
Embodiment 1
A kind of wireless isolation base station suitable for the transregional Integrated services access of electric power, penetrated comprising baseband processing unit BBU and numeral
Frequency unit R RU two parts form, and wherein BBU completes base band signal process, and hardware includes CPU, DSP, FPGA and matched
DRAM, Flash, RRU complete radiofrequency signal processing：
CPU is connected with two separate Ethernet interfaces respectively by two groups of SGMII interfaces, and CPU passes through two groups of SRIO interfaces
It is connected with DSP, DSP is connected by two groups of SRIO interfaces with FPGA, and CPU is polycaryon processor core0~core3, different core
Different tasks is handled respectively, is connected outside CPU pieces a piece of for storage system configuration parameter, the NAND Flash cores of configuration processor
Piece；Four dram chip DRAM0~DRAM3 for being used to data are write and read in CPU implementation procedures are connected outside CPU pieces,
Inside CPU, there are two dram controllers to control two panels piece outer DRAM, i.e. dram controller A control DRAM0, DRAM1 respectively,
Dram controller B controls DRAM2, DRAM3, and data/address bus, address bus, the control line of two dram controllers are individually separated not
Multiplexing, tetra- kernels of CPU control two dram controllers by internal bus, wherein, core0, core1, core3 pass through DRAM
Controller A performs reading and writing data, and core2 performs reading and writing data by dram controller B；
DSP is polycaryon processor core0~core5, and different core handles different tasks, four are connected outside DSP pieces respectively
Dram chip DRAM0~DRAM3, data are write and read in the process of implementation for DSP, inside DSP, there is a DDR
Sdram controller, for dram chip outside control sheet, the address that the outer dram chip of four pieces shares DDR sdram controllers is total
Line, control line, DDR sdram controller data/address bus are configured to two groups of 32 separate bit data bus, one of which 32
The outer DRAM0 and DRAM1 of bit data bus connection sheet, the outer DRAM2 of another group of 32 bit data bus connection sheets and DRAM3, DDR
Sdram controller has two independent chip selection signal interfaces, the outer DRAM0 and DRAM1 of a connection sheet, outside another connection sheet
Six kernels of DRAM2 and DRAM3, DSP control DDR sdram controllers by internal bus, are made by controlling chip selection signal
DRAM outside piece that can be different.
The transregional Integrated services access of electric power wirelessly isolates base partition method
（1）Operational processor is isolated：
1）CPU inside structures：Four cores are included in XLS416 processors, each core has independent I-Cache and D-Cache, uses
Instruction and computing intermediate link data buffer storage in respective core processor, logic isolation, can be selected by code command herein
Space is answered in the verification specified, and 4 Cache memory spaces are corresponded to respectively for 4 cores.Four cores by MDI buses and piece, piece
External memory carries out data interaction, and different great Qu business is handled on different core.
2) DSP inside structures：Six cores include in MSC8157 processors, by CLASS buses with piece, piece external memory
Reservoir carries out data interaction, and different great Qu business is handled on different core.
（2）Transmission channel is isolated
The business data flow in Liang Ge great areas：
1）Production control great Qu business data flows have passed through following key component：
Ethernet interface 0
Interface SGMII_0 between Ethernet and CPU
Core2, dram controller B in CPU
CPU pieces outer DRAM2, DRAM3
Interface SRIO_0 between CPU and DSP
Core2, DDR controller in DSP
DSP pieces outer DRAM2, DRAM3
Interface SRIO_0 between DSP and FPGA
Ø FPGA
2）Management information great Qu business data flows have passed through following key component：
Ethernet interface 1
Interface SGMII_1 between Ethernet and CPU
Core3, dram controller A in CPU
CPU pieces outer DRAM0, DRAM1
Interface SRIO_1 between CPU and DSP
Core3, DDR controller in DSP
DSP pieces outer DRAM0, DRAM1
Interface SRIO_1 between DSP and FPGA
Ø FPGA
Transmission channel isolation mainly includes following physical interface and isolated：
1）Ethernet interface is isolated：Two independent network interfaces transmit different great Qu business datums respectively, see appended sheets of drawings 9, chip D6, interface
T1, and appended sheets of drawings 9, chip D5, interface T2.
2）SGMII interfaces are isolated：CPU has two groups of SGMII interfaces to be connected with Ethernet interface.
3）SRIO interfaces are isolated：There are two groups of separate SRIO mouths to carry out between CPU and DSP, between DSP and FPGA
Different great Qu business data transmissions.
Above-mentioned hardware interface is respectively for two groups and separate, it is ensured that data transmission channel is isolated.
（3）Memory headroom is isolated
In CPU, DRAM outside piece can be configured to 2*32bit memory modes by CPU, i.e. two dram controllers in CPU
Chip external memory can be accessed by 32 bit data bus respectively.
Core2 is written and read by dram controller B to DRAM2, DRAM3 outside piece, and core3 passes through A pairs of dram controller
Piece outer DRAM0, DRAM1 are written and read, the data/address bus of two dram controllers（CPU_DDRAD<31…0>、CPU_DDRBD<
31…0>）, address bus（CPU_DDRAA<12…0>、CPU_DDRBA<12…0>）, control line（CPU_DDRA_RAS#、CPU_
DDRB_RAS#, CPU_DDRA_CAS#, CPU_DDRB_CAS#, CPU_DDRA_WE#, CPU_DDRB_WE# etc.）It is mutually independent
It is not multiplexed.Core2 and core3 time-sharing multiplexs storage distribution bus, the interaction such as data, instruction is completed in the different clock cycle,
Realize that different great Qu business datum timesharing is transmitted in bus.
Dram controller A and B have separate data/address bus, address bus, control line respectively in CPU pieces
In DPS, core2, core3 are written and read by DDR controller to DRAM outside piece, pass through chip selection signal（MCS[0:
1]）The outer DRAM of control sheet is enabled.Core2 control chip selection signals B（DSP1_DDR_CS1#）, namely MCS [1], enable outside piece
DRAM2, DRAM3 are written and read operation；Core3 control chip selection signals A（DSP1_DDR_CS0#）, namely MCS [0], enable outside piece
DRAM0, DRAM1 are written and read operation.Enable signal A and enable signal B can not be enabled simultaneously, and piece outer DRAM0, DRAM1 with
Piece outer DRAM2, DRAM3 not common data bus（DSP1_DDR_B_DATA is used respectively<31…0>And DSP1_DDR_A_DATA
<31…0>）.Core2 and arbitration and exchange system bus inside core3 time-sharing multiplexs（CLASS buses）, in different clock weeks
Phase completes the interaction such as data, instruction, realizes that different great Qu business datum timesharing is transmitted in bus.
（4）Eat dishes without rice or wine to isolate
In FPGA, mainly with time/frequency source block（TFB）For unit, the separation of business data flow is realized.Different time-frequencies is provided
Source block distributes to different terminals, and business datum is carried in time/frequency source block by terminal.FPGA receives the data from RRU
Afterwards, running time-frequency resource is mapped, according to the rule that system is pre-configured（Time/frequency source block --- DSP core ID）, will
Corresponding data fill out DSP core ID, are sent to core corresponding to DSP by corresponding SRIO interfaces, realize different great Qu
Business datum separation.
The not described part of the present embodiment is same as the prior art.
In FPGA, mainly with time/frequency source block（TFB）For unit, the separation of business data flow is realized.TFB1、TFB4、TFB6
It is connected with production control great Qu terminal, TFB2, TFB3, TFB5, TFB7 are connected with management information great Qu terminal, will not
Time/frequency source block with great Qu distributes to different terminals, and business datum is carried in time/frequency source block by terminal.FPGA is received
After data from RRU, according to the subregion of business, running time-frequency resource is mapped, according to the rule that system is pre-configured（When
Frequency resource block --- DSP core ID）, corresponding data are filled out into DSP core ID, are sent to by corresponding SRIO interfaces
Core corresponding to DSP, realize different great Qu business datum separation.
Claims (7)
- A kind of 1. wireless isolation base station suitable for the transregional Integrated services access of electric power, it is characterised in that：Include Base-Band Processing list First BBU and digital radio frequency unit RRU two parts composition, wherein BBU complete base band signal process, and hardware includes processor CPU, number Word signal transacting DSP, on-site programmable gate array FPGA and dynamic random access memory DRAM, the flash memory to match Flash, RRU complete radiofrequency signal processing：CPU is connected with two separate Ethernet interfaces respectively by two groups of serial gigabit media stand-alone interface SGMII, CPU serially rapidly inputs output interface SRIO by two groups and is connected with DSP, and DSP is connected by two groups of SRIO interfaces with FPGA, CPU is polycaryon processor core0~core3, and different core handles different tasks respectively, is connected outside CPU pieces a piece of for depositing The Flash chip of storage system configuration parameter, configuration processor；Four are connected outside CPU pieces to be used to write and read in CPU implementation procedures Dram chip DRAM0~the DRAM3 for evidence of fetching, inside CPU, there are two dram controllers to control the outer DRAM of two panels piece respectively, That is dram controller A controls DRAM0, DRAM1, dram controller B control DRAM2, DRAM3, the data of two dram controllers Bus, address bus, control line are individually separated not reusing, and tetra- kernels of CPU control two DRAM to control by internal bus Device processed, wherein, core0, core1, core3 perform reading and writing data by dram controller A, and core2 is held by dram controller B Row reading and writing data；DSP is polycaryon processor core0~core5, and different core handles different tasks, four are connected outside DSP pieces respectively Dram chip DRAM0~DRAM3, data are write and read in the process of implementation for DSP, inside DSP, there is a double-speed Rate synchronous dynamic random storage DDR SDRAM controller, for dram chip outside control sheet, the outer dram chip of four pieces shares Address bus, the control line of DDR sdram controllers, DDR sdram controller data/address bus be configured to two groups it is separate Most bit data bus, the outer DRAM0 and DRAM1 of one of which majority bit data bus connection sheet, another group of multidigit data are total The outer DRAM2 of line connection sheet and DRAM3, DDR sdram controller have two independent chip selection signal interfaces, outside a connection sheet DRAM0 and DRAM1, outer six kernels of DRAM2 and DRAM3, DSP of another connection sheet control DDR SDRAM by internal bus Controller, DRAM outside different pieces is enabled by controlling chip selection signal.
- 2. the wireless isolation base station according to claim 1 suitable for the transregional Integrated services access of electric power, it is characterised in that： Four cores include in CPU processor, each core has independent I-Cache and D-Cache, for respective core processor instruction and Computing intermediate link data buffer storage, herein logic isolation used CPU Affinity technologies, utilize CPU Affinity technologies Different great Qu process is tied on different CPU cores, space is answered in the verification specified by code command selection, for 4 Core corresponds to 4 Cache memory spaces respectively, four cores by MDI buses and piece, chip external memory carry out data interaction, no Business with great Qu is handled on different core.
- 3. the wireless isolation base station according to claim 2 suitable for the transregional Integrated services access of electric power, it is characterised in that： Six cores include in DSP Processor, by CLASS buses and piece, chip external memory progress data interaction, different great Qu industry Business is handled on different core.
- 4. the wireless isolation base station according to claim 3 suitable for the transregional Integrated services access of electric power, it is characterised in that： Transmission channel isolation includes：1）Ethernet interface is isolated, and is to transmit different great Qu business datums respectively using two independent network interfaces,2）SGMII interfaces are isolated, and CPU has two groups of SGMII interfaces to be connected with Ethernet interface,3）SRIO interfaces are isolated, and have two groups of separate SRIO mouths to carry out not between CPU and DSP, between DSP and FPGA With great Qu business data transmissions.
- 5. the wireless isolation base station according to claim 4 suitable for the transregional Integrated services access of electric power, it is characterised in that： Memory headroom is isolated, and in CPU, DRAM outside piece can be configured to 2*32bit memory modes by CPU, i.e. two in CPU Dram controller can access chip external memory by 32 bit data bus respectively, and wherein core2 is by dram controller B to piece Outer DRAM2, DRAM3 are written and read, and core3 is written and read by dram controller A to DRAM0, DRAM1 outside piece, two DRAM Data/address bus, address bus, the control line of controller are mutually independent not to be multiplexed, and core2 distributes with the storage of core3 time-sharing multiplexs Bus, the interaction such as data, instruction is completed in the different clock cycle, realize that different great Qu business datum timesharing uploads in bus It is defeated；In DPS, core2, core3 are written and read by DDR controller to DRAM outside piece, pass through chip selection signal control sheet Outer DRAM；Core2 controls chip selection signal B, and enabled piece outer DRAM2, DRAM3 are written and read operation；Core3 controls chip selection signal A, Enabled piece outer DRAM0, DRAM1 are written and read operation, and enable signal A and enable signal B can not be enabled simultaneously, and the outer DRAM0 of piece, Common data bus, the arbitration of core2 and core3 time-sharing multiplexs inside and exchange system be not total with piece outer DRAM2, DRAM3 by DRAM1 Line, the interaction such as data, instruction is completed in the different clock cycle, realize that different great Qu business datum timesharing uploads in bus It is defeated.
- 6. the wireless isolation base station according to claim 5 suitable for the transregional Integrated services access of electric power, it is characterised in that： Isolation of eating dishes without rice or wine refers to that FPGA in units of time/frequency source block TFB, realizes the separation of business data flow, and FPGA is received from RRU Data after, running time-frequency resource is mapped, according to the rule that system is pre-configured -- time/frequency source block, by corresponding data DSP core ID are filled out, core corresponding to DSP is sent to by corresponding SRIO interfaces, realizes different great Qu business datum Separation.
- 7. the wireless isolation base station according to claim 1 suitable for the transregional Integrated services access of electric power, it is characterised in that： Described Flash chip is NAND Flash chips.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110161913A (en) * | 2019-05-23 | 2019-08-23 | 上海钇莹电器有限公司 | A kind of controller of aluminium electrolytic bath multi-channel data acquisition plate and multi-channel data acquisition method |
| CN111177066A (en) * | 2019-12-29 | 2020-05-19 | 苏州浪潮智能科技有限公司 | Method, device and medium for improving efficiency of accessing off-chip memory |
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