CN108563144A - A kind of missile-borne radar signal processing semi-hardware type simulation test system - Google Patents
A kind of missile-borne radar signal processing semi-hardware type simulation test system Download PDFInfo
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Abstract
The invention belongs to radar signal simulation process fields, disclose a kind of missile-borne radar signal processing semi-hardware type simulation test system, including radar seeker comprehensive test device, analog-to-digital conversion module, FPGA preprocessing modules, DSP imagings module, host computer display terminal；Two-way reference clock is exported by signal source, it gives radar seeker comprehensive test device to be used as all the way and refers to clock, all the way to signal processor as sampling clock, guinea pig echo-signal and frame synchronization and pulse synchronous signal are exported by radar seeker comprehensive test device, analog-to-digital conversion module is completed to sample the A/D of guinea pig echo, FPGA is as preprocessing module, complete the table tennis transmission of data prediction and data, two panels dsp chip completes imaging in DSP imaging modules, another dsp chip completes transmission of the imaging results to host computer, the real-time display imaging result on host computer display terminal.
Description
Technical field
The invention belongs to radar signal simulation processing technology field more particularly to a kind of missile-borne radar signal processing half are in kind
Emulation test system, for fields such as high-speed aircraft imaging tracking guidances.
Background technology
In order to adapt to increasingly complicated battlefield surroundings, modern real time signal processing is calculated in the rapid development of radar science technology
Higher requirements are also raised for method.SAR signal processing technology also becomes the hot spot explored and developed in various countries, however
Theoretical simulation can not be limited to for the performance of signal processing algorithm, need further to verify in practical applications.
In the test verification process of previous SAR signal processing machine, there is following defect：First, signal
The actual performance of processor generally requires outfield experiments verification, and this method is time-consuming and laborious, undoubtedly the R＆D cycle is made to increase, and
It is easy to be influenced by external conditions such as weather；Second is that actual missile-borne signal-processing board is one plate of a bullet again, do not unify
Hardware platform, this brings very big difficulty for the verification of new algorithm；Third, the target seeker system peripheral of all-real object is more, cost compared with
Height, the test verification for signal processing algorithm can bring additional expense.Therefore for Radar Signal Processing HWIL simulation
The structure of test system is very necessary for the emulation testing of laboratory stage signal processor.
Invention content
In view of the above-mentioned problems, the purpose of the present invention is to provide a kind of missile-borne radar signal processing semi-hardware type simulation test systems
System makes laboratory stage test verification be more nearly outfield experiments, for solving the outfield experiments easily affected by environment, development cycle
A series of problems, such as long, of high cost.
Before Radar Signal Processing semi-hardware type simulation test system simulates practical radar by radar seeker comprehensive test device
End output guinea pig echo, completes a series of signal processing algorithm in signal processor, to which checking signal processing is calculated
Whether method performance and signal processing system work are normal.
In order to achieve the above objectives, the present invention is realised by adopting the following technical scheme.
A kind of missile-borne radar signal processing semi-hardware type simulation test system, the system comprises：Signal source of clock, radar are led
Leader comprehensive test device, signal processor and host computer display terminal；The signal processor includes：Analog-to-digital conversion mould
Block, FPGA signal pre-processing modules, DSP imaging modules；
The reference clock output end being arranged on the signal source of clock is set on the radar seeker comprehensive test device
The reference clock input terminal connection set；
When the sampling clock output end being arranged on the signal source of clock and the sampling being arranged on the analog-to-digital conversion module
Clock input terminal connects；
On the analog signal output and the analog-to-digital conversion module being arranged on the radar seeker comprehensive test device
The input end of analog signal of setting connects；
The synchronous signal output end being arranged on the radar seeker comprehensive test device and the FPGA Signal Pretreatments
The synchronous signal input end of module connects；
The digital signal output end of the analog-to-digital conversion module and the digital signal of the FPGA signal pre-processing modules are defeated
Enter end connection；
The digital signal of the digital signal output end of the FPGA signal pre-processing modules and the DSP imagings module
Input terminal connects；
The number that the digital signal output end of the DSP imagings module passes through Ethernet and the host computer display terminal
Word signal input part connects.
It the characteristics of technical solution of the present invention and is further improved to：
(1) the radar seeker comprehensive test device is completed for obtaining emulation radar echo signal from simulation software
The conversion that radar echo signal is emulated to guinea pig echo-signal, and the guinea pig echo-signal is passed through into four tunnels
SMA interfaces are sent to four road input end of analog signal of analog-to-digital conversion module；
The radar seeker comprehensive test device is additionally operable to setting radar return frame synchronizing signal and impulsive synchronization letter
Number, and the radar return frame synchronizing signal and the pulse synchronous signal are sent to FPGA signals by bnc interface and located in advance
Manage module；
The analog-to-digital conversion module, for being amplified successively to the guinea pig echo-signal, single-ended transfer difference behaviour
Make and A/D is sampled, and the digital radar signal obtained after sampling is sent to FPGA signals by 12 LVDS interfaces and is located in advance
Manage module；
The FPGA signal pre-processing modules, for according to the radar return frame synchronizing signal and pulse synchronous signal pair
The digital radar signal carries out the pretreatment operation of Digital Down Convert and pulse compression successively, obtains pretreated digital thunder
DSP imaging modules are sent to by SRIO interfaces table tennis up to signal, and by the pretreated digital radar signal；
The DSP imagings module, for being imaged to the pretreated digital radar signal, and by radar
Image formation result is sent to host computer display terminal by gigabit Ethernet；
The host computer display terminal is used for real-time display radar signal imaging results.
(2) analog-to-digital conversion module includes：Four amplifiers and four A/D converters, four amplifiers and institute
Four A/D converters are stated to be correspondingly connected with；
The amplifier is amplified for the guinea pig echo-signal to input, and single-ended signal is changed into difference
Signal；The amplifier is connect the gain that guinea pig echo-signal is amplified by FPGA signal pre-processing modules by SPI
Mouth is controlled；
The A/D converter samples to obtain digital radar signal for carrying out A/D to amplified differential signal, and will
The digital radar signal is sent to FPGA signal pre-processing modules.
(3) the FPGA signal pre-processing modules include：Data preparation submodule, Digital Down Convert submodule, pulse pressure
Contracting submodule, data buffering submodule and SRIO transmit submodule；
Unsigned number is become having symbol by the data preparation submodule for being arranged to the digital radar signal
Number, and be 16 by 12 Bits Expandings by data bit width, and be 4096 by the data points interception in each pulse repetition period
Point carries out clock domain conversion to data, and is transmitted to Digital Down Converter Module；
The Digital Down Convert submodule, data that treated for receiving data preparation submodule, according to radar return
Frame synchronizing signal and pulse synchronous signal are mixed data, are filtered, and generate radar return frame synchronizing signal and pulse is same
Signal is walked, pulse compression submodule is sent to；
Submodule is compressed in the pulse, data that treated for receiving Digital Down Convert submodule, and is returned according to radar
Wave frame synchronizing signal and pulse synchronous signal carry out 4096 point FFT operations, matched filtering and 4096 point IFFT operations to data,
And radar return frame synchronizing signal and pulse synchronous signal are generated, it is sent to data buffering submodule；
The data buffering submodule for carrying out clock domain conversion to data, and transmits submodule for SRIO and provides arteries and veins
Rush original transmission mark；
The SRIO transmits submodule, the data for receiving data buffering submodule, and detection frame beginning flag is completed
SRIO streams write agreement, and data table tennis is transferred to DSP imaging modules.
(4) the DSP imagings module includes three dsp chips, is denoted as DSP1, DSP2, DSP3 respectively；The DSP1
It is connect with DSP2 by Hyperlink interfaces, the DSP3 is connect by PCI-Express interfaces with DSP2；
FPGA signal pre-processing modules, for sending 4096 pulse datas to DSP1 and then being sent to DSP3 same
The data of data volume, the rotation successively between DSP1 and DSP3 connect the pretreated digital radar signal by SRIO
Mouth table tennis is sent to DSP imaging modules；
The DSP1 and DSP3, for the pretreated number for receiving the transmission of FPGA signal pre-processing modules of rattling
Radar signal；And Doppler center estimation, range walk school are carried out to the pretreated digital radar signal received respectively
Just, the imaging of range curvature correction, secondary range pulse pressure, motion error extraction and compensation, Azimuth Compression and geometric correction
Journey obtains radar signal imaging results, and the radar signal imaging results is sent to DSP2；
Radar signal imaging results are sent to host computer display terminal by the DSP2 by gigabit Ethernet.
(5) DSP2 is connected to gigabit Ethernet conversion chip by SGMII interfaces, and the gigabit Ethernet converts core
Piece passes through RJ45 network interface connections to host computer display terminal.
The present invention has the following advantages：First, the present invention is due to using radar seeker comprehensive test device, the device to have
The solid state disk of 8192GB, amount of storage is big, can be played back to the radar echo signal of the MATALB arbitrary data amounts generated；
Second, radar seeker comprehensive test device of the present invention has the DA chips of four tunnel highest 500MHz, can be generated to MATLAB
The most four roads Radar IF Echo for meeting hardware parameter is played back, and four road signals may be the same or different, can
To be completed at the same time the verification of signal-processing board multichannel；Third, the present invention, should due to using radar seeker comprehensive test device
Device has reference clock input interface all the way, and frame synchronization and all the way impulsive synchronization output interface all the way, echo data is according to upper
It states three kinds of signals to be played back, simulates practical radar front end working condition；4th, fpga chip involved in the present invention selects logic
The more rich Virtex-6 family chips of resource, memory resource, DSP resources, dsp chip also select industry peak performance
TMS320C6678 chips, all plug-in capacity of every DSP are the DDR SDRAM chips of 2GByte, big to handling to meet the system
The requirement of data volume and operation complicated algorithm；5th, the present invention in FPGA preprocessing modules with ping pong scheme and using high speed go here and there
Row communication interface SRIO is completed and DSP1 and DSP3 chip data transmissions, and in addition a piece of DSP2 chips pass through gigabit Ethernet chip
It is communicated with host computer, overcomes the slow disadvantage of prior art transmission rate, improved the real-time of the present invention, meet missile-borne
Radar signal processor system is required to high real-time and quickly；6th, implementation process of the present invention is simple, in laboratory
Test verification can be carried out to the function of signal-processing board, not influenced, used manpower and material resources sparingly by external condition, save outfield
The time cycle of experiment and development cost；7th, present system equipment is less, easy to connect, and cost is relatively low；8th, this hair
It is bright to replace signal-processing board or signal processing algorithm, verification is completed to different signal-processing boards or algorithm, it is versatile.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Obtain other attached drawings according to these attached drawings.
Fig. 1 is the realization structure diagram of missile-borne radar signal processing semi-hardware type simulation test system of the present invention；
Fig. 2 is the connection diagram between the radar seeker comprehensive test device and signal processor of the present invention；
Fig. 3 is the connection diagram between the analog-to-digital conversion module and FPGA preprocessing modules of the present invention；
Fig. 4 is the connection diagram between the DSP imagings module and FPGA preprocessing modules of the present invention；
Fig. 5 is the connection diagram between the host computer display terminal and signal processor of the present invention.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Description that following further describes the present invention with reference to the drawings.
With reference to the accompanying drawings 1, the present invention includes following module altogether：Radar seeker comprehensive test device, signal processor
With host computer display terminal.Wherein：
Radar seeker comprehensive test device is mainly used to generate the guinea pig echo-signal of Multi-path synchronous.Radar is led
It is 500MHz to have the D/A output interfaces of 4 road SMA forms, DA chip maximum slew rates on leader comprehensive test device rear panel,
Resolution ratio is 16bit, all the way external reference clock input interface, all the way frame synchronization output interface and all the way impulsive synchronization output connect
Mouthful.
Radar seeker comprehensive test device mainly has following functions：It is guided for MATLAB artificial echos data to radar
The format conversion of head comprehensive test device echo data；For echo data to radar seeker comprehensive test device solid state disk
Importing and browsing；Setting for radar seeker comprehensive test device playback parameter；For output multi-channel guinea pig
Echo-signal is to signal processor；For exporting radar return frame synchronization and pulse synchronous signal to signal processor.
Signal processor, including analog-to-digital conversion module, FPGA preprocessing modules and DSP imaging modules.
The analog-to-digital conversion module uses four modulus conversion chip ADS5463, but not limited to this chip, chip highest are adopted
Sample rate 500MSPS (per second to sample how many million times), 12 LVDS outputs are unidirectionally connect with radar seeker comprehensive test device,
It is bi-directionally connected with FPGA preprocessing modules, the guinea pig echo for receiving the output of radar seeker comprehensive test device is gone forward side by side
Row sampling, what is provided due to radar seeker comprehensive test device is single-ended signal, and its peak-to-peak value is 1.2Vpp, so first
The analog quantity of acquisition is carried out single-ended signal first with the amplifier AD8370 of ADI companies and changes into differential signal, and is amplified,
And the gain of AD8370 chip signal outputs can be controlled by fpga chip by register value in SPI interface modification piece, and
The AD8370 differential signals exported are exported afterwards and complete analog-to-digital conversion to ADS5463, are finally sent to the data after sampling
FPGA preprocessing modules.
The FPGA preprocessing modules select the Virtex-6 series high-performances XC6VLX240T- of a piece of XILINX companies
The chip of FF1156, but not limited to this chip, the number of logic cells of the chip is up to 241152, DSP48E1 Slice numbers
Amount is up to 768, and speed is up to 600MHz, single-ended pin 600, and various high speed strings may be implemented in high speed serialization transceiver 20
Row bus agreement, the FPGA preprocessing modules are bi-directionally connected with analog-to-digital conversion module respectively, in the two-way company of DSP imaging modules
It connects.
The FPGA preprocessing modules, including data preparation submodule, Digital Down Convert submodule, pulse compression submodule,
Data buffering submodule and SRIO transmit submodule, the data preparation submodule, for what is transmitted to analog-to-digital conversion module
Echo data is arranged, and unsigned number is become signed number, and be 16 by 12 Bits Expandings by data bit width, and will be each
Data points interception in pulse repetition period is 4096 points, carries out clock domain conversion to data, and be transmitted to Digital Down Convert
Module；The Digital Down Convert submodule, data that treated for receiving data preparation submodule, according to synchronizing signal pair
Data are mixed, are filtered, and generate frame synchronization and pulse synchronous signal, are sent to pulse compression submodule；The pulse
Submodule is compressed, data that treated for receiving Digital Down Convert submodule, and data are carried out according to pulse synchronous signal
4096 point FFT operations, matched filtering and 4096 point IFFT operations, and frame synchronization and pulse synchronous signal are generated, it is sent to number
According to buffering submodule；The data buffering submodule carries out clock domain conversion to data, and transmits submodule for SRIO and provide
Pulse original transmission mark；The SRIO transmits submodule, and the data for receiving data buffering submodule are used for detection frame
Beginning flag writes agreement for completing SRIO streams, the table tennis of data is transferred to DSP1 and DSP3 chips, it is to a piece of DSP cores
Piece sends 4096 pulse datas and then sends the data of same data volume to another dsp chip, in two panels dsp chip
Between rotation successively, for complete doorbell interrupt transmission.
The DSP imaging modules select the dsp chip of the model TMS320C6678 of three pieces TI companies, but do not limit to
In the chip, which possesses high-performance fixed point/floating-point CPU core that 8 rates are up to 1.25GHz, has 4096KB's in piece
Multinuclear shared memory, the DDR3 memories of expansible maximum 8GB outside piece, the outer DDR3 operating rates of piece are up to 1600MHz, are gathered around
It is 2GByte to have 4 channels SRIO, compatible 1.25,2.5,3.125 and 5Gbps operating rates, all plug-in capacity of every dsp chip
DDR SDRAM chips, for storing the data and imaging results that FPGA preprocessing modules are sent, DSP1 and DSP3 are used for
Table tennis receives the pretreated data that FPGA preprocessing modules send over；DSP1 and DSP3 estimates for carrying out Doppler center
Meter, Range Walk Correction, range curvature correction, secondary range pulse pressure, motion error extraction and compensation, Azimuth Compression and geometry
Correcting algorithm completes imaging, and imaging results is sent to by Hyperlink interfaces and PCI-Express interfaces
DSP2 chips；DSP2 chips are used to the imaging results that DSP1 and DSP3 is sent being sent to host computer by gigabit Ethernet and show
Terminal.
Host computer display terminal, is bi-directionally connected by cable and signal processor, by DSP2 cores in system implementation process
The SAR image that DSP1 and DSP3 are obtained in DSP imaging modules is sent to host computer by piece by gigabit Ethernet, and upper
Real-time display imaging results in the machine display terminal of position.
Refer to the attached drawing 2, the connection between radar seeker comprehensive test device and signal processor are made further
Bright description.
The radar seeker comprehensive test device has four road SMA form D/A output interfaces：SMA1, SMA2, SMA3, SMA4,
Most four-way coherent signals, the four road A/D that DA output interfaces pass through coaxial wire and analog-to-digital conversion module can be exported simultaneously
Input interface AD1, AD2, AD3, AD4 are connected, radar seeker comprehensive test device reference clock input interface CLK_IN and letter
The output all the way in number source is connected, in addition signal processor AD sampling clock input interface ADC_CLK and signal source export all the way
It is connected, the frame synchronizing signal IPPS_OUT and pulse synchronous signal TRIG_OUT of the radar seeker comprehensive test device pass through
Bnc interface exports, then defeated by the frame synchronization of coaxial wire and signal processor input sync_frame and impulsive synchronization
Enter sync_pulse to be connected, reference is provided for FPGA data pretreatment.
Refer to the attached drawing 3, the connection between analog-to-digital conversion module and FPGA preprocessing modules are further described description.
Analog-to-digital conversion module uses four A/D conversion chips, chip to select the ADS5463 of TI companies, is used for guinea pig
The acquisition of echo signal of intermediate frequency, first we select the amplifier AD8370 of ADI companies that the analog quantity of acquisition is carried out single-ended letter
Number differential signal is changed into, and be amplified, it is defeated to control by SPI interface to change register value in AD8370 pieces by fpga chip
Go out the gain of signal, the specific signal that controls is DATA, CLK, LATCH, and AD8370 chips give differential signal transmission later
ADS5463 carries out A/D samplings by the chip, and sends the data to FPGA preprocessing modules.Modulus conversion chip ADS5463
The main signal line being connect with fpga chip is as follows：ADC_P[11：0]、ADC_N[11：0], it is low-voltage differential signal, is used for
A/D sampled datas are transmitted, and data output mode is ddr mode；OVR_P, OVR_N are data spill over line, are used to refer to
Whether input signal values overflow；DRY_P, DRY_N are ready for data signal line, are used to refer to sampling and have completed.
Refer to the attached drawing 4, the connection between DSP imagings module and FPGA preprocessing modules, which is further described, retouches
It states.
DSP imaging modules select the dsp chip of three pieces model TMS320C6678, three pieces dsp chip to pass through
Serial Rapid IO (SRIO) interfaces are connected with FPGA preprocessing modules, in FPGA, have BANK112-BANK116 this five
A MGT high speeds transceiver module, the present invention in BANK112 be connected with DSP3；BANK113 is connected with DSP1, BANK116 and DSP2 phases
Even, these three SRIO interfaces are set as 4 channels, and the rate in each channel is 3.125GHz, terminal part be data packet source or
Destination, different terminal parts are distinguished with device ID, and the ID number of FPGA is respectively 0xFF, 0x AA, 0x 55, the ID of DSP1
Number it is D1, the ID number of DSP2 is D2, and the ID number of DSP3 is D3.High speed serial communication interface SRIO clock frequencies of the present invention are
125MHz, serial communication interface use following signals line：srio_txp0、srio_txn0、srio_txpl、srio_txn1、
srio_txp2、srio_txn2、srio_txp3、srio_txn3；srio_rxp0、srio_rxn0、srio_rxp1、srio_
Rxn1, srio_rxp2, srio_rxn2, srio_rxp3, srio_rxn3 are serial differential form.It is completed in DSP1 and DSP3
After imaging algorithm, imaging results are sent to DSP2 by Hyperlink interfaces and PCI-Express interfaces, by DSP2
Data are transferred to host computer display terminal from signal-processing board, carry out the real-time display of result.
Refer to the attached drawing 5, the connection between host computer display terminal and signal processor are further described description.
The SGMII interfaces of DSP2 chips are connected on gigabit Ethernet conversion chip, and gigabit Ethernet conversion chip is selected
88EE1111 chips, specific connection use following signals line：DSP2_SGMII1_RXP、DSP2_SGMII1_RXN、DSP2_
SGMII1_TXP, DSP2_SGMII1_TXN, the signal wire are the data line of difference form；DSP2_MDIO turns for Ethernet
Change the two-way IO control lines of chip, the clock line that DSP2_MDC is Ethernet conversion chip, the conversion chip and a RJ45 net
Mouth is connected, and is communicated with host computer by RJ45 connected with network cable, real-time Transmission imaging result.
Operation principle in implementation process of the present invention carries out as described below：
Echo simulation.Self-defined echo parameter is needed according to test, the emulation generation echo data in MATLAB, by data
It is written in the file of the entitled .dat of suffix, data conversion is completed in data conversion software, is added before each pulse data
The header packet information of 32 bytes, this packet header are mainly used for parsing of the internal system hardware for echo simulation data, data conversion
After completion, need to first pass through in the data storage to SSD (solid state disk) that embedded computer will play back, data import it
After need to carry out browsing data in software interface, confirm import data it is errorless after, carry out systematic parameter configuration, including clock
Source, reference clock, pulse recurrence frequency, frame pulse number and pulse width enter playback interfaces, selection playback after being provided with
Pattern, waiting signal processing board power on.
System connects.The reference clock input interface of radar seeker comprehensive test device is led to signal source output interface
Coaxial wire connection is crossed, the AD sampling clocks input interface of signal processor is passed through with signal source another way output interface same
Shaft cable line connects, and radar seeker comprehensive test device DA output interfaces is passed through with signal processor AD input interfaces coaxial
Cable connects, by the frame synchronization of radar seeker comprehensive test device, the frame of impulsive synchronization output interface and signal processor
Synchronous, impulsive synchronization input interface is connected by coaxial wire, and signal processor Ethernet interface is passed through with host computer
Cable connects.
Signal-processing board powers on.The beginning playback button of radar seeker comprehensive test device software interface is clicked, outside
The lower output guinea pig echo-signal of portion's reference clock effect and frame synchronization and pulse synchronous signal, fpga chip pass through SPI
Register value controls the gain of output signal in interface modification AD8370 pieces, and the analog-to-digital conversion module in signal processor adopting
A/D conversions are carried out to the guinea pig echo-signal of input when sample clock arrives, FPGA preprocessing modules are in frame synchronization and pulse
Data prediction is carried out to the data of analog-to-digital conversion module transmission under the guidance of synchronizing signal, realizes Digital Down Convert, quick Fu
To pulse squeeze operation, pretreated data are passed through Serial by subsequent FPGA preprocessing modules for vertical leaf transformation, distance
Rapid IO (SRIO) interfaces are sent to DSP imaging moulds DSP1 and DSP3 in the block, FPGA with ping pong scheme and pre-process mould
Block can send a doorbell interruption in the data for sending 4096 pulse repetition periods, right after DSP1 and DSP3 receive interruption
Pretreated data carry out Doppler center estimation, Range Walk Correction, range curvature correction, secondary range pulse pressure, movement
Estimation error and compensation, Azimuth Compression and geometric correction algorithm, complete imaging, subsequent DSP1 and DSP3 pass through
Result is sent to DSP2 by treated for Hyperlink interfaces and PCI-Express interfaces, will by gigabit Ethernet by DSP2
Imaging result is transferred to host computer display terminal, and carries out real time imagery at host computer display terminal interface.
The application of the present invention is not limited by external condition, can simulate practical radar front end work, this system also has in addition
Reliable and stable, amount of storage is big, the high advantage of transmission rate, is primarily adapted for use in the reality in the fields such as high-speed aircraft imaging tracking guidance
Test the test verification in room stage.
One of ordinary skill in the art will appreciate that：Realize that all or part of step of above method embodiment can pass through
The relevant hardware of program instruction is completed, and program above-mentioned can be stored in computer read/write memory medium, which exists
When execution, step including the steps of the foregoing method embodiments is executed；And storage medium above-mentioned includes：ROM, RAM, magnetic disc or CD
Etc. the various media that can store program code.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (6)
1. a kind of missile-borne radar signal processing semi-hardware type simulation test system, which is characterized in that the system comprises：Clock signal
Source, radar seeker comprehensive test device, signal processor and host computer display terminal；The signal processor includes：Mould
Number conversion module, FPGA signal pre-processing modules, DSP imaging modules；
It is arranged on the reference clock output end and the radar seeker comprehensive test device being arranged on the signal source of clock
Reference clock input terminal connects；
The sampling clock output end being arranged on the signal source of clock and the sampling clock being arranged on the analog-to-digital conversion module are defeated
Enter end connection；
The analog signal output being arranged on the radar seeker comprehensive test device is arranged on the analog-to-digital conversion module
Input end of analog signal connection；
The synchronous signal output end being arranged on the radar seeker comprehensive test device and the FPGA signal pre-processing modules
Synchronous signal input end connection；
The digital signal input end of the digital signal output end of the analog-to-digital conversion module and the FPGA signal pre-processing modules
Connection；
The digital signal output end of the FPGA signal pre-processing modules and the digital signal of the DSP imagings module input
End connection；
The digital signal output end of the DSP imagings module is believed by the number of Ethernet and the host computer display terminal
The connection of number input terminal.
2. a kind of missile-borne radar signal processing semi-hardware type simulation test system according to claim 1, which is characterized in that
The radar seeker comprehensive test device is completed described imitative for obtaining emulation radar echo signal from simulation software
True radar echo signal and is connect the guinea pig echo-signal by four road SMA to the conversion of guinea pig echo-signal
Mouth is sent to four road input end of analog signal of analog-to-digital conversion module；
The radar seeker comprehensive test device is additionally operable to setting radar return frame synchronizing signal and pulse synchronous signal, and
The radar return frame synchronizing signal and the pulse synchronous signal are sent to FPGA Signal Pretreatment moulds by bnc interface
Block；
The analog-to-digital conversion module, for being amplified successively to the guinea pig echo-signal, single-ended transfer difference operation with
And A/D samplings, and the digital radar signal obtained after A/D is sampled is sent to FPGA Signal Pretreatments by 12 LVDS interfaces
Module；
The FPGA signal pre-processing modules are used for according to the radar return frame synchronizing signal and pulse synchronous signal to described
Digital radar signal carries out the pretreatment operation of Digital Down Convert and pulse compression successively, obtains pretreated digital radar letter
Number, and the pretreated digital radar signal is sent to DSP imaging modules by SRIO interfaces table tennis；
The DSP imagings module, for being imaged to the pretreated digital radar signal, and by radar signal
Imaging results are sent to host computer display terminal by gigabit Ethernet；
The host computer display terminal is used for real-time display radar signal imaging results.
3. a kind of missile-borne radar signal processing semi-hardware type simulation test system according to claim 2, which is characterized in that institute
Stating analog-to-digital conversion module includes：Four amplifiers and four A/D converters, four amplifiers are converted with four A/D
Device is correspondingly connected with；
The amplifier is amplified for the guinea pig echo-signal to input, and amplified single-ended signal is changed into
Differential signal；The amplifier is passed through the gain that guinea pig echo-signal is amplified by FPGA signal pre-processing modules
SPI interface is controlled；
The A/D converter samples to obtain digital radar signal for carrying out A/D to amplified differential signal, and will be described
Digital radar signal is sent to FPGA signal pre-processing modules.
4. a kind of missile-borne radar signal processing semi-hardware type simulation test system according to claim 2, which is characterized in that institute
Stating FPGA signal pre-processing modules includes：Data preparation submodule, Digital Down Convert submodule, pulse compression submodule, data
It buffers submodule and SRIO transmits submodule；
Unsigned number is become signed number for being arranged to the digital radar signal by the data preparation submodule,
And by data bit width by 12 Bits Expandings be 16, and by each pulse repetition period data points interception be 4096 points, it is right
Data carry out clock domain conversion, and are transmitted to Digital Down Converter Module；
The Digital Down Convert submodule, data that treated for receiving data preparation submodule are same according to radar return frame
Step signal and pulse synchronous signal are mixed data, are filtered, and generate radar return frame synchronizing signal and impulsive synchronization letter
Number, it is sent to pulse compression submodule；
Submodule is compressed in the pulse, data that treated for receiving Digital Down Convert submodule, and according to radar return frame
Synchronizing signal and pulse synchronous signal carry out 4096 point FFT operations, matched filtering and 4096 point IFFT operations to data, and produce
Raw radar return frame synchronizing signal and pulse synchronous signal, are sent to data buffering submodule；
The data buffering submodule for carrying out clock domain conversion to data, and transmits submodule for SRIO and provides pulse
Begin transmission mark；
The SRIO transmits submodule, the data for receiving data buffering submodule, and detection frame beginning flag completes SRIO streams
Agreement is write, data table tennis is transferred to DSP imaging modules.
5. a kind of missile-borne radar signal processing semi-hardware type simulation test system according to claim 2, which is characterized in that institute
It includes three dsp chips to state DSP imaging modules, is denoted as DSP1, DSP2, DSP3 respectively；The DSP1 passes through Hyperlink
Interface is connect with DSP2, and the DSP3 is connect by PCI-Express interfaces with DSP2；
FPGA signal pre-processing modules, for sending 4096 pulse datas to DSP1 and then sending same data to DSP3
The pretreated digital radar signal is passed through SRIO interface table tennis by the data of amount, the rotation successively between DSP1 and DSP3
Pang be sent to DSP imaging modules；
The DSP1 and DSP3, for the pretreated digital radar for receiving the transmission of FPGA signal pre-processing modules of rattling
Signal；And respectively to the pretreated digital radar signal that receives carry out Doppler center estimation, Range Walk Correction, away from
From curvature correction, the imaging process of secondary range pulse pressure, motion error extraction and compensation, Azimuth Compression and geometric correction, obtain
It is sent to DSP2 to radar signal imaging results, and by the radar signal imaging results；
Radar signal imaging results are sent to host computer display terminal by the DSP2 by gigabit Ethernet.
6. a kind of missile-borne radar signal processing semi-hardware type simulation test system according to claim 5, which is characterized in that institute
It states DSP2 and gigabit Ethernet conversion chip is connected to by SGMII interfaces, the gigabit Ethernet conversion chip passes through RJ45 nets
Mouth is connected to host computer display terminal.
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| CN109194598A (en) * | 2018-11-16 | 2019-01-11 | 上海工程技术大学 | A kind of general PSK modulation demodulation system |
| CN109194598B (en) * | 2018-11-16 | 2020-12-11 | 上海工程技术大学 | General PSK modulation and demodulation system |
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| CN111367259A (en) * | 2020-03-17 | 2020-07-03 | 四川九洲电器集团有限责任公司 | Low-cost digital signal processing module automatic testing device and method |
| CN111650588A (en) * | 2020-07-10 | 2020-09-11 | 国科北方电子科技(北京)有限公司 | Small real-time processing device of SAR (synthetic aperture radar) and RD (RD) algorithm real-time processing method of SAR signals |
| CN111880438B (en) * | 2020-08-21 | 2022-11-15 | 航天科工微电子系统研究院有限公司 | Semi-physical simulation system based on double/multi-base SAR imaging |
| CN111880438A (en) * | 2020-08-21 | 2020-11-03 | 航天科工微电子系统研究院有限公司 | Semi-physical simulation system based on double/multi-base SAR imaging |
| CN112505643A (en) * | 2020-11-03 | 2021-03-16 | 湖北航天技术研究院总体设计所 | Radar and infrared composite seeker open-loop semi-physical simulation method and system |
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| CN112631977A (en) * | 2020-12-17 | 2021-04-09 | 中国科学院光电技术研究所 | Dynamic multi-target electric simulation system |
| CN112631977B (en) * | 2020-12-17 | 2022-12-30 | 中国科学院光电技术研究所 | Dynamic multi-target electric simulation system |
| CN113900089A (en) * | 2021-10-12 | 2022-01-07 | 西安电子科技大学 | FPGA and DSP based agile coherent target detection device and method |
| CN113900089B (en) * | 2021-10-12 | 2024-09-03 | 西安电子科技大学 | Agile phase-change target detection device and method based on FPGA and DSP |
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